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LEGO Star Wars: Droid Tales - Coming to Disney XD
Sat, 2015-02-28 00:12 — News
LEGO Star Wars: Droid Tales, An All-New Series of Event Specials, Acquired by Disney XD
ENFIELD, Conn., Feb. 27, 2015 -- The LEGO Group, world renowned manufacturer of construction toys, today announced that Disney XD has acquired LEGO® Star Wars™: Droid Tales for airing later this year. The animated content series consists of five 22-minute episodes that re-tell the Star Wars saga in chronological order from Star Wars: The Phantom Menace up through Star Wars: Return of the Jedi. Disney XD is also currently home to the animated hit series Star Wars Rebels.
"Since we introduced our first LEGO Star Wars set in 1999, we have seen and heard from countless Star Wars fans who have used LEGO bricks to tell their own version of this timeless story, re-enacting favorite scenes and imagining new story lines," said Jill Wilfert, vice president of licensing and entertainment for The LEGO Group. "LEGO Star Wars: Droid Tales gives us an opportunity to share highlights of the Star Wars story with a sense of humor and excitement that can only be conveyed through the LEGO brick, and will be a fun resource for families as they gear up for the next movie."
As its title suggests, Droid Tales is a re-telling of the Star Wars universe through the eyes of C-3P0 and R2-D2. Following their victory celebration in the Ewok village on Endor, seen at the close of Star Wars: Return of the Jedi, C-3PO and R2-D2 have gathered to regale Luke, Leia, Han, Chewbacca and the other Rebels with the tales of their adventures that led to the events of Star Wars: The Phantom Menace. An accidental kidnapping occurs while the droids are reminiscing and suddenly viewers are taken on a new adventure that leads to encounters with familiar faces and places that prompt the re-telling of the entire saga. The series offers all of the playful humor that viewers expect from LEGO Star Wars.
Information on airdates for each episode is not yet available. Additional LEGO Star Wars activities to get the family caught up will launch throughout the year.
About LEGO Systems, Inc.
LEGO Systems, Inc. is the North American division of The LEGO Group, a privately-held, family-owned company based in Billund, Denmark, one of the world's leading manufacturers of creatively educational play materials for children. The company is committed to the development of children's creative and imaginative abilities, and its employees are guided by the motto adopted in the 1930s by founder Ole Kirk Christiansen: "Only the best is good enough." Visit the virtual LEGO world at www.LEGO.com
About Lucasfilm Ltd.
Lucasfilm Ltd. is one of the world's leading film and entertainment companies. Founded by George Lucas in 1971, it is a privately held, fully-integrated entertainment company. In addition to its motion-picture and television production operations, the company's global activities include Industrial Light & Magic and Skywalker Sound, serving the digital needs of the entertainment industry for visual-effects and audio post-production; LucasArts, a leading developer and publisher of interactive entertainment software worldwide; Lucas Licensing, which manages the global merchandising activities for Lucasfilm's entertainment properties; Lucasfilm Animation, which is currently producing content for film and television, including Star Wars: The Clone Wars, a CG-animated half-hour television series; and Lucas Online creates Internet-based content for Lucasfilm's entertainment properties and businesses. Additionally, Lucasfilm Singapore, produces digital animated content for film and television, as well as visual effects for feature films and multi-platform games. Lucasfilm's motion-picture productions include three of the 20 biggest box-office hits of all time and have received 19 Oscars and more than 60 Academy Award nominations. Lucasfilm's television projects have won 12 Emmy Awards. Lucasfilm Ltd. is headquartered in San Francisco, Calif.
STAR WARS, Star Wars: Rebels and related character names are trademarks and/or copyrights, in the United States and other countries, of Lucasfilm Ltd. and/or its affiliates.
©2015. TM & © Lucasfilm Ltd. All rights reserved.
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DC Designer Series: Wonder Woman by Frank Cho Statue


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Tenneco History
OverviewSalaryRevenue
CEO & Executives
Tenneco Company History Timeline
Tennessee Gas and Transmission Company (completely separate) had been formed in 1940.
The Tennessee division of the Chicago Corporation acquired Tennessee Gas Transmission Company in 1943 to build a natural-gas pipeline 1,265 miles (2,036 km) from Texas to West Virginia.
The first line was completed in October 1944.
Tenneco Inc.,, formerly (1947–66) Tennessee Gas And Transmission Company, diversified American industrial corporation, with major interests in natural-gas pipelines and the construction of heavy equipment.
Foster graduated from Texas A&M University in 1957 with a B.S. in petroleum engineering and B.B.A. in business administration; he joined Tenneco as a junior petroleum engineer in Oklahoma City the same year.
In 1961, Tenneco diversified into chemicals with the purchase of Heyden Newport Chemical Corp. and into paperboard and packaging material with the purchase of Packaging Corporation of America.
In 1966, Tennessee Gas was incorporated as Tenneco, Inc.
In 1967, the company acquired Walker, Inc., a manufacturer of universal-fit exhaust mufflers and pipes.
Management thwarted efforts by shareholders to split and sell the firm's several divisions in 1982.
In 1984, Case parent Tenneco bought selected assets of the International Harvester agriculture division and merged it with J.I. Case.
The farm machinery operations of Navistar were purchased and folded into the Case division in 1985.
All agriculture products are first labeled Case International and later Case IH. Tenneco purchased the articulated 4WD manufacturer Steiger Tractor in 1986, and merged it into Case IH.
In 1988 Tenneco sold off its considerable petroleum- and natural-gas-producing properties in order to concentrate on its diversified industrial operations.
By 1988, the company was losing $2 million per day.
In 1991, Tenneco posted record losses of $723 million.
The automotive division was spun off from Tenneco, Inc. in 1991 along with the packaging, energy, natural gas, and shipbuilding divisions.
The firm sold its products to nearly every original equipment manufacturer in the world, and its sales reached a record $2.94 billion, nearly double the total in 1992.
By 1994, Tenneco decided to begin getting out of the ag business and agreed to sell 35% of the now named Case Corporation.
To bolster its lucrative plastic packaging and consumer products operations, Tenneco paid $1.27 billion for the plastics division of Mobil Chemical Co. in 1995.
The following year, Tenneco divested its insurance arm to I.C.H. Corp. For example, Tenneco sold its Case farm machinery subsidiary in 1995.
However, the firm's divestment efforts continued when El Paso Energy Corp. acquired Tenneco Energy in 1996.
These pipelines were acquired by El Paso Corporation in 1996, and are now owned by Kinder Morgan.
In 1997 Tenneco Automotive held a 25 percent share of the global shocks and mufflers market.
sedgwick, david. "tenneco offspring expected to survive parent's breakup." automotive news, 27 july 1998.
The relationship between Tenneco and Öhlins actually began in 1998 when the two companies began working together to develop electronic valve technology for automotive applications.
In 1998, plans to merge with Tower Automotive Inc. fizzled.
Under the Walker and Monroe brand names, Tenneco Automotive manufactures Sensa-Trac and Reflex shocks and struts, Rancho shock absorbers, Walker Quiet Flow Mufflers (first introduced in 1998), DynoMax performance exhaust products, and Monroe Clevite vibration control components.
By 1998, the firm operated 67 plants, offices, or branches in 21 countries.
Tenneco's history as a stand-alone entity began in 1999, when the current company emerged from a conglomerate formerly consisting of six businesses -- shipbuilding, packaging, farm and construction equipment, gas transmission, automotive and chemicals.
The split was completed in 1999, when Tenneco Automotive Inc. and Pactiv Corp. began trading as independent companies on the New York Stock Exchange.
Among the largest 150 North American automotive parts suppliers, Tenneco Automotive ranked 37th, according to Automotive News in 1999.
The company was acquired by Fiat in 1999 and merged with New Holland Agriculture to form CNH Global.
The newly independent firm has yet to achieve profitability. It posted a $423 million loss on sales of $3.27 billion in 1999.
sherefkin, robert. "caution flag; tenneco is lean and focused, but analysts warn of softening market." automotive news, 13 november 2000.
According to a March 2001 PR Newswire release, "Tenneco Automotive's long-term strategy is to expand its global capabilities through niche acquisitions, joint ventures, and strategic alliances.
Losses increased, however, in 2001 to $130 million as sales fell to $3.36 billion.
Although recessionary economic conditions were largely to blame for Tenneco Automotive's weak financial performance in 2001, the firm's 1.5 billion debt load, the highest in the industry, also posed problems.
A sluggish North American economy undercut revenues in 2001.
A surplus problem in North America prompted auto manufacturers to shut down assembly plants for days and, in some cases, weeks during the first quarter of 2001.
sherefkin, robert. "tenneco, lear post losses; both will close plants." automotive news, 4 february 2002.
Although automakers were able to maintain sales growth throughout the year with no-interest financing programs, many began slowing production in anticipation of reduced demand in 2002.
tenneco automotive inc. home page, 2002. available at http://www.tenneco-automotive.com.
In 2003, Tenneco and Öhlins jointly launched the first CES shock absorbers as standard equipment on the Volvo S60R performance car.
On October 28, 2005 Tenneco Automotive was renamed as Tenneco.
In 2005, the company rebranded its name to Tenneco, to better represent the expanding number of markets it served.
On October 1, 2018, Tenneco Inc. completed its acquisition of Federal-Mogul, a leading global supplier to original equipment manufacturers and the aftermarket.
2020-12-1 PCA Tomahawk Named an Educator of the Year by TEAPIE
"Tenneco Automotive Inc. ." Company Profiles for Students. . Encyclopedia.com. (April 16, 2021). https://www.encyclopedia.com/economics/economics-magazines/tenneco-automotive-inc
Lake Forest, IL
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redpajama_set_name: RedPajamaCommonCrawl


Looking for a business game about a store management? But also want a challenge? Then this game is for you.
Welcome to the world of retail business!
The purpose of this game is to provide an opportunity to learn the ins and outs of a retail business.
However differently from our other retail games, in Budget Retail you will need to manage a company that is located in countries with low level of income.
The name of the game implies that the pricing policy of your merchandise is crucial, since you will be competing with real users who offer the same type of goods for similar prices. In this game you will have to apply different strategies to make profit in highly competitive regions.


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Jobs Work online from anywhere in the world
Industry station
Industry (band)
Industry is the production of goods or services within an economy. The major source of revenue of a group or company is the indicator of its relevant industry. When a large group has multiple sources of revenue generation, it is considered to be working in different industries. Manufacturing industry became a key sector of production and labour in European and North American countries during the Industrial Revolution, upsetting previous mercantile and feudal economies. This occurred through many successive rapid advances in technology, such as the production of steel and coal.
Following the Industrial Revolution, possibly a third of the world's economic output is derived that is from manufacturing industries. Many developed countries and many developing/semi-developed countries (People's Republic of China, India etc.) depend significantly on manufacturing industry. Industries, the countries they reside in, and the economies of those countries are interlinked in a complex web of interdependence.
This page contains text from Wikipedia, the Free Encyclopedia -	https://wn.com/Industry
Industry Metrolink is located at 600 S. Brea Canyon Road in Industry, California. It is owned and operated by the City of Industry. Metro and Foothill Transit provide connecting service at the station with lines 484 and 482, respectively. There are approximately 1,440 parking spaces available. Foothill 482 is a local bus route serving the area There is no rail service to this station on weekends, but connecting buses continue to run with a limited schedule. In 2011, the Industry station had the highest ridership in the Riverside line, averaging 1,378 daily boardings, representing 34.5% of all boardings for the Riverside line.
The City of Industry station opened on June 14, 1993, and built at a cost of $2.4 million. In 1994, the Riverside line, which then ran from downtown Los Angeles to the Industry station, had Metrolink's highest ridership per week, averaging 2,000 passengers. In 2012, 8,000 solar panels were installed to cover 940 parking spaces in an $11 million project that generates 2.2 megawatts (3,000 hp) of electricity per hour. The project also included the installation of 64 electric car charging stations. Most of the funding came from Proposition 1A, although the South Coast Air Quality Management District also provided a $2 million grant.
This page contains text from Wikipedia, the Free Encyclopedia -	https://wn.com/Industry_station
Industry was an American new wave band formed in 1978 in New York as Industrial Complex, their name later changing to Industry. In 1981, the band became commercial but disbanded three years later. Their only album was Stranger to Stranger, released in 1984 which included the hit single, "State of the Nation".
Andrew Geyer - vocals, guitar, tape loops
Mercury Caronia - vocals, drums, bass guitar
Sean Kelly - vocals
Jon Carin - lead vocals, keyboards, synthesizers
Brian Unger - guitar, backing vocals
Mercury Caronia - drums, backing vocals
Rudy Perrone - bass guitar, backing vocals
Mercury Caronia - drums, keyboards, vocals
Andrew Geyer - guitar, tape loops, vocals
Sean Kelly - bass, keyboards, vocals
Steven Northshield - guitar
Industry was founded as Industrial Complex in 1978 by Mercury Caronia (drummer, vocalist, keyboard player, composer and studio engineer), Andrew Geyer (guitarist) and Sean Kelly (bass guitarist and backing vocalist). The band's name was later changed to Industry. Caronia and Geyer worked with experimental electronic music, odd time signatures, tape loops, synthesizers and innovative guitar playing into various methods of recording.
This page contains text from Wikipedia, the Free Encyclopedia -	https://wn.com/Industry_(band)
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heavyindustrynews.net
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oilandfuelindustry.com
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industrymining.com
planetindustry.com
investmentbankingindustry.org
thedairyindustry.com
asiapacificindustry.com
Latest News for: Industry sponsorship
Fed up of constant demands of sponsoring medical conferences, pharma companies urge ministry to intervene
The News International 18 Jul 2019
This requires expensive sponsorships to meet expenses and are more of social family get-together", said an official of the Pakistan Pharmaceutical Manufacturers' Association (PPMA) on Thursday ... A two monthly forum with industry is being appreciated by the PPMA ......
Jostens Creates Championship Bracelet for 2019 World Series of Poker Champion
Omaha World-Herald 18 Jul 2019
"This year's bracelet – like its champion – will be remembered for its unique contribution to the game and to the WSOP tradition.""Poker is a sport, so it is great that a poker player can win a trophy piece of jewelry made by an elite manufacturer in the sports industry," said Simone Ricci, Director of Sponsorships & Events of WSOP....
Healey donates $100,000 to Carriage Museum
Newburyport Daily News 18 Jul 2019
Amesbury Industrial Supply owner Greg Jardis donated approximately 2,300 square feet of space in his large High Street hardware store to the Carriage Museum late last year ... Healey said the Carriage Museum's focus on industrial history inspired him to get involved....
Entire board of greyhound body should resign, says Ross
The Irish Times 17 Jul 2019
The Cabinet has heard calls for the entire board of the Irish Greyhound Board to resign following recent controversy over animal cruelty in the industry ... Barry's Tea, FBD Insurance and animal feed manufacturer Connolly's Red Mills have since pulled their sponsorship of greyhound racing ... "Of course the greyhound industry has been damaged......
Agent Image Signs On As A Headline Sponsor For 2019 Inman Connect Las Vegas Conference
Dothan Eagle 15 Jul 2019
"We are thrilled to be a headlining sponsor for one of the most anticipated industry conferences of the year," says Jon Krabbe, Managing Partner of Agent Image ... Their sponsorship is also a symbol of their strong commitment to the industry, with excellence at the core of what they do," says Emily Paquette, Chief Revenue Officer of Inman....
2 held for masquerading as officials of PM's Office
Hindustan Times 13 Jul 2019
... Khadi and Village Industries Commission (KVIC) of Rs 30 lakh under the guise of sponsorship for a "fashion show" to "promote Khadi products"....
QCrime: Bank Duped of 4.24 cr, Teacher Booked For Marrying Minor
Yahoo Daily News 13 Jul 2019
1. Bank Duped of Rs 4.24 cr in Bogus Personal Loans ... (Source. Hindustan Times). Also Read. QCrime ... 2 ... 3 ... The Delhi Police arrested two persons for impersonating officials of the Prime Minister's Office (PMO) to cheat Khadi and Village Industries Commission (KVIC) of Rs 30 lakh under the guise of sponsorship for a "fashion show" to "promote Khadi products"....
PC giant agrees sponsorship deal with Esports Scotland
Scotsman 11 Jul 2019
James Hood, founder of Esports Scotland, said ... "This sponsorship will allow us to work with an international industry leader to develop the gaming community in Scotland from grass-roots outreach all the way up to the elite and professional levels." ... ....
PotNetwork Holdings Recaps Path to Becoming a Fully Reporting SEC Company
The Record 11 Jul 2019
... Gold, and others) for the past several years has built and maintained a high profile in its industry and with consumers through its presence at innumerable trade shows and expositions, its sponsorship of sporting and entertainment events, and a robust presence on social media....
Chair of Irish Greyhound Board says it's 'understandable' why sponsors withdrew funding
The programme raised concerns around animal welfare issues in the greyhound racing industry ... "It's understandable why people would have withdrawn their sponsorship," he added ... "The withdrawal of sponsorship because of the model of the industry, in fact, affects owners and trainers because sponsorship money goes straight to them," he said....
Mastercard and Evolve Bank & Trust Help Hourly and Gig Workers Get Early Access to Wages
The Oneida Daily Dispatch 10 Jul 2019
PURCHASE, N.Y.--(BUSINESS WIRE)--Jul 10, 2019-- ... debit cards ... MA), www.mastercard.com, is a technology company in the global payments industry ... Evolve is recognized as a global leader in the Payment Processing Industry delivering ACH, Debit/Credit Sponsorship, Card Issuance and unique technology strategies to clients around the world ... INDUSTRY KEYWORD....
With cigarette consumption way down, Big Tobacco is giving away coupons in bars
Vox 10 Jul 2019
The rise of an in-person marketing program like this one highlights how drastically federal regulations and the rise of vaping have changed the American tobacco industry ... A brief history of tobacco marketing and regulations This type of advertising program is not new to the industry....
Irish greyhound industry to bring in new sponsorship model
The Irish greyhound industry is to introduce a new model of sponsorship after losing several sponsors in the aftermath of an RTÉ Investigates programme on the industry. Barry's Tea, FBD Insurance and animal feed manufacturer Connolly's Red Mills pulled their sponsorship of greyhound racing in the past week....


From the 1965 ablum, Father of the Folk Blues. I remember hearing this for the first time in the mid-1970s as a cover by Finnigan & Wood in mechanical drawing class in high school. Powerful then. Powerful now.
This entry was posted in Blues and tagged Son House. Bookmark the permalink.


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Patent application title: Resist Technique
Inventors: R. R. Lee (Hsin-Chu, TW) Buh-Kuan Fang (Zhubei City, TW)
Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
IPC8 Class: AH01L21308FI
Class name: Semiconductor device manufacturing: process chemical etching combined with coating step
The present disclosure provides various methods for removing a resist layer from a wafer. An exemplary method includes performing an etching process to remove a resist layer from a wafer. During the etching process, a first heating process is performed to effect a first graded thermal profile in the resist layer, the first graded thermal profile having a temperature that increases along a direction perpendicular to the wafer. Further during the etching process, and after performing the first heating process, a second heating process is performed to effect a second graded thermal profile in the resist layer, the second graded thermal profile having a temperature that decreases along the direction perpendicular to the wafer. In an example, the method further includes, before performing the etching process, performing an ion implantation process to the wafer using the resist layer as a mask.
1. A method comprising: performing an etching process to remove a resist layer from a wafer, wherein during the etching process: a first heating process is performed to effect a first graded thermal profile in the resist layer, the first graded thermal profile having a temperature that increases along a direction substantially perpendicular to the wafer; and after performing the first heating process, a second heating process is performed to effect a second graded thermal profile in the resist layer, the second graded thermal profile having a temperature that decreases along the direction substantially perpendicular to the wafer.
2. The method of claim 1 wherein: the wafer has a frontside and a backside; the resist layer is disposed over the front side of the wafer; and the first heating process includes heating the resist layer from the front side of the wafer.
3. The method of claim 2 wherein the first heating process further includes cooling the backside of the wafer.
4. The method of claim 2 wherein the second heating process includes heating the resist layer from the backside of the wafer.
5. The method of claim 4 wherein: heating the resist layer from the front side of the wafer includes applying an intermittent heat source to the front side of the wafer; and heating the resist layer from the backside of the wafer includes applying a constant heat source to the backside of the wafer.
6. The method of claim 5 wherein: the resist layer includes a hardened portion; and applying the intermittent heat source to the front side of the wafer includes, during the etching process, cycling the heat source on and off until the hardened portion of the resist layer is substantially removed, thereby leaving a remaining portion of the resist layer.
7. The method of claim 6 wherein the etching process is performed and the constant heat source is applied to the backside of the wafer until the remaining portion of the resist layer is removed.
8. The method of claim 6 wherein the heat source is cycled off before a temperature of the resist layer that is not hardened reaches a popping temperature.
9. The method of claim 1 further including, before performing the etching process, performing an ion implantation process to the wafer using the resist layer as a mask.
10. A method comprising: forming a patterned resist layer over a wafer; and performing an ashing process to remove the patterned resist layer from the wafer, wherein during the ashing process: a first heating process heats the patterned resist layer from the front side of the wafer while maintaining a wafer temperature of the wafer less than a popping temperature of the patterned resist layer, and after performing the first heating process, a second heating process heats the patterned resist layer from the backside of the wafer.
11. The method of claim 10 wherein: heating the patterned resist layer from the front side of the wafer includes applying an intermittent heat source to the front side of the wafer; and heating the patterned resist layer from the backside of the wafer includes applying a constant heat source to the backside of the wafer.
12. The method of claim 11 wherein: the patterned resist layer includes a hardened portion; and applying the intermittent heat source to the front side of the wafer includes, during the ashing process, cycling the heat source on and off until the hardened portion is substantially removed, thereby leaving a remaining portion of the patterned resist layer.
13. The method of claim 12 wherein the ashing process is performed and the constant heat source is applied to the backside of the wafer until the remaining portion is removed.
14. The method of claim 10 wherein maintaining the wafer temperature less than the popping temperature of the patterned resist layer includes maintaining the wafer temperature less than about 90.degree. C.
15. The method of claim 14 wherein the heating the patterned resist layer from the front side of the wafer includes cycling a heat source on and off to raise a temperature of crust of the patterned resist layer to about 100.degree. C. to about 300.degree. C.
16. The method of claim 11 wherein maintaining the wafer temperature less than the popping temperature of the resist layer includes cooling the wafer from the backside to keep a temperature of a non-crust portion of the patterned resist layer less than an associated popping temperature of the non-crust portion.
17. The method of claim 10 further including performing an ion implantation process using the patterned resist layer as a mask.
18. A method comprising: providing a wafer having a front side and a backside; forming a patterned resist layer over the front side of the wafer; performing an ion implantation process on the wafer using the patterned resist layer as a mask, wherein the patterned resist layer includes a crust after the ion implantation process; performing a dry etching process to remove the patterned resist layer from the wafer, wherein: a first heating process is performed during the dry etching process until the crust of the patterned resist layer is substantially removed, thereby leaving a remaining portion of the patterned resist layer, wherein the first heating process includes applying a first heat source to the front side of the wafer, wherein the first heat source is cycled on and off; and a second heating process is performed during the dry etching process to remove the remaining portion of the patterned resist layer, wherein the second heating process includes applying a second heat source to the backside of the wafer.
19. The method of claim 18 wherein the first heating process further includes cooling the wafer from the backside.
20. The method of claim 19 wherein the applying the first heat source to the front side of the wafer and the cooling the wafer from the backside raises a temperature of the crust without raising a temperature of the patterned resist layer above a popping temperature.
[0001] Integrated circuit (IC) technologies are continually progressing to smaller feature sizes, for example, down to 65 nanometers, 45 nanometers, and below. Various patterned resist layers are used to transfer a designed pattern to a wafer to form a desired IC device. For example, various resist layers are used to form multiple material layers of the wafer that combine to form a complementary metal-oxide-semiconductor device. During wafer processing, complete removal of each resist layer from the wafer is desired since resist material remaining on the wafer can cause defects in the fabricated ICs. Such removal is performed carefully to avoid chemically modifying or physically damaging the wafer. Although existing resist removal techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
[0002] The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
[0003] FIG. 1 is a flow chart of a method for removing a resist layer from a wafer according to various aspects of the present disclosure.
[0004] FIGS. 2-6 are various diagrammatic cross-sectional views of a resist layer during various stages of the method of FIG. 1 according to various aspects of the present disclosure.
[0005] The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
[0006] FIG. 1 is a flow chart of a method for removing a resist layer from a wafer according to various aspects of the present disclosure. The method 100 begins at block 110 and block 120 where a wafer having a front side and a backside is provided, and a patterned resist layer is formed over the front side of the wafer. At block 130, an ion implantation process is performed on the wafer using the patterned resist layer as a mask. In an example, a doped region is formed in the wafer using the ion implantation process. After the ion implantation process, the pattered resist layer includes a crust. At block 140, an etching process is performed to remove the patterned resist layer from the wafer. During the etching process, at block 142, a first heating process is performed until the crust is substantially removed. The first heating process heats the pattered resist layer from the front side of the wafer while maintaining a wafer temperature of the wafer less than a popping temperature of the patterned resist layer. During the etching process, at block 144, a second heating process is performed that heats the patterned resist layer from the backside of the wafer. At block 150, fabrication on the wafer is completed. Additional steps can be provided before, during, and after the method 100, and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method 100.
[0007] FIGS. 2-6 are various diagrammatic cross-sectional views of a resist layer during various stages of the method 100 of FIG. 1 according to various aspects of the present disclosure. FIGS. 2-6 have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. In FIG. 2, a wafer 210 having a front side 212 and a backside 214 is provided. The wafer 210 is a substrate (for example, a semiconductor substrate), a mask (also referred to as a photomask or reticle), or any base material on which processing may be conducted to provide layers of material to form various features of an integrated circuit (IC) device. In the depicted embodiment, the wafer 210 is a semiconductor substrate including silicon (in other words, a silicon wafer). Alternatively or additionally, the wafer 210 includes another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the wafer 210 is a semiconductor on insulator (SOI). The wafer 210 may alternatively be referred to as a material layer, or the wafer 210 may include a material layer upon which a resist layer will be formed. In an example, the material layer is a metal layer, a semiconductor layer, or a dielectric layer. In another example, the material layer is a hard mask layer, such as a silicon oxide layer or a silicon nitride layer.
[0008] A patterned resist layer 220 is formed over the wafer 210, particularly over the front side 212 of the wafer 210. The patterned resist layer 220 is also referred to as a photoresist layer, photosensitive layer, imaging layer, patterning layer, or radiation sensitive layer. The patterned resist layer 220 includes a positive-type resist material, a negative-type resist material, other type material, or combination thereof. The patterned resist layer 220 is formed over the wafer 210 by a lithography process. The lithography process includes resist coating (for example, spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the resist, rinsing, drying (for example, hard baking), other suitable processes, or a combination thereof. Alternatively, the lithography process is implemented or replaced by other methods, such as maskless lithography, electron-beam writing, or ion-beam writing. In yet another alternative, the lithography process implements nanoimprint technology to pattern the resist layer. In some examples, the lithography process implements an etching process, such as a dry etching, wet etching, other etching method, or combination thereof. A rinsing process, such as a de-ionized (DI) water rinse, may be performed on the wafer 210 before forming the resist layer 220.
[0009] The patterned resist layer 220 includes an opening that exposes a portion of the wafer 210 as illustrated in FIG. 2. In FIG. 3, a process 230 is performed on the wafer 210 using the patterned resist layer 220 as a mask. In the depicted embodiment, the process 230 is an ion implantation process that forms a doped region 232 in the wafer 210. The ion implantation process implants p-type dopants (such as boron or indium), n-type dopants (such as phosphorous or arsenic), or a combination thereof. In an example, the doped region 232 is a well or a source/drain region of an integrated circuit device, such as a transistor. The ion implantation process is performed at a suitable energy and dosage to achieve desired characteristics of the integrated circuit device. In the present example, the ion implantation process is a high dosage ion implantation process that uses, for example, an implant dosage of greater than or equal to about 3×1010 ions/cm2.
[0010] The process 230 alters the patterned resist layer 220, resulting in an altered portion 220A and an unaltered portion 220B of the patterned resist layer 220. In the present example, the ion implantation process causes physical and chemical changes in the patterned resist layer 220, such that a portion of the patterned resist layer 220 is hardened (designated as portion 220A in FIG. 3). The altered portion 220A is also referred to as a hardened portion or a crust of the patterned resist layer 220. Such physical and chemical changes result from various phenomena including dopants embedded in the patterned resist layer 220 during the ion implantation process, cross-linking of polymer chains of the patterned resist layer 220 during the ion implantation process (caused by the dopants altering polymer properties of the resist material, which carbonizes and hardens portions of the patterned resist layer 220A exposed to the dopants), dopants sputtering atoms from the wafer 210 to the patterned resist layer 220A, other phenomena, or a combination thereof.
[0011] The hardened portion 220A of the patterned resist layer 220 exhibits low reactivity to resist removal processes, particularly plasma ash processes. Accordingly, resist removal processes require high temperatures to effectively remove the hardened portion 220A of the patterned resist layer 220. Resist removal techniques typically achieve such high temperatures by heating the wafer 210 (for example, to temperatures greater than about 250° C.) from the backside, thereby heating the patterned resist layer 220. When the resist layer is heated via heating the backside 214 of the wafer 210 to achieve the high temperatures required for removing the hardened portion 220A, gases and/or pressure accumulates in the portion 220B of the patterned resist layer 220. The gases can explosively erupt, resulting in the resist material "popping" (where the gases (and/or pressure) built up in the portion 220B "pops" through the hardened, crust portion 220A). The popping temperature for the patterned resist layer 220 varies depending on resist type, resist thickness, pattern density, resist formation conditions (for example, post exposure baking conditions), other conditions, or a combination thereof. Further, if the patterned resist layer 220 is subjected to the high temperature environment for too long, portions of the hardened portion 220A may further harden and remain over the wafer 210. Another resist removal technique that adequately removes the patterned resist layer 220 is a chemical stripping process, such as a hydrogen chemical stripping process. Conventional chemical stripping processes undesirably leave a net charge on the wafer 210 that can negatively affect subsequent processing and device performance of a fabricated integrated circuit device. Yet another resist removal technique implements a wet etching process to remove the patterned resist layer 220. Although the wet etching process can adequately remove the hardened portion 220A of the patterned resist layer 220, the wet etching process typically requires spinning the wafer 210 to adequately remove the wet etching solution, which often result in features of the wafer 210 (for example, gate line features) breaking or falling.
[0012] The following discussion, with reference to FIGS. 4-6, provides a resist removal technique for removing the patterned resist layer 220 from the wafer 210 that uses a combination of low temperature and high temperature heating processes to provide adequate heating for effectively removing the hardened, crust portion 220A while preventing or minimizing any popping or further hardening phenomena of the patterned resist layer 220. In FIG. 4, a first resist removal process step is performed to remove a portion of the patterned resist layer 220. The first resist removal process step substantially removes the hardened, crust portion 220A of the patterned resist layer 220. The first resist removal process step includes a resist stripping process 240. In the depicted embodiment, the resist stripping process 240 is a plasma ashing (etching) process having an etching chemistry and etching conditions suitable for removing the patterned resist layer 220. For example, the etching chemistry includes a fluorine-containing gas (such as CF4), an oxygen-containing gas (such as O2), a nitrogen-containing gas (such as N2), other suitable gas, or a combination thereof.
[0013] The first resist removal process step further includes a heating process 250. In the present example, the heating process 250 is performed during the resist stripping process 240. The heating process 250 intermittently heats the patterned resist layer 220 from the front side 212 of the wafer 210. More specifically, a heat source is cycled on and off during the resist stripping process 240 to heat the patterned resist layer 220, particularly the hardened, crust portion 220A. The heat source is cycled on for a time period that sufficiently raises a temperature of the hardened, crust portion 220A to a temperature that facilitates adequate removal of the portion 220A without causing heat to accumulate in the portion 220A (accumulated heat can induce further hardening of the portion 220A and/or hardening of the portion 220B). Raising the temperature of the portion 220A increases an etching rate of the portion 220A. In an example, the heat source is cycled on to raise the temperature of the hardened, crust portion 220A to a temperature of about 100° C. to about 300° C. For example, the heat source is cycled on for about 20 seconds to about 30 seconds to raise the temperature of the hardened, crust portion 220A to a temperature of about 100° C. to about 300° C., and then, the heat source is cycled off until the temperature of the portion 220A and/or portion 220B returns to a temperature that minimizes further hardening of the portion 220A (for example, room temperature). By cycling the heat source on and off, heat accumulation in the patterned resist layer 220 is avoided. Further, during the heating process 250, a temperature of the wafer 210 is maintained at a temperature less than a popping temperature associated with the patterned resist layer 220, particularly a popping temperature of the portion 220B. For example, the wafer 210 is maintained at a temperature less than or equal to about 90° C. In another example, the wafer 210 is maintained at about room temperature (from about 20° C. to about 25° C.). In the depicted embodiment, a chilling process 260 is applied to the backside 214 of the wafer 210 to ensure that the heating process 250 (and/or resist stripping process 240) does not heat the portion 220B of the patterned resist layer 220 to its associated popping temperature.
[0014] The heating process 250 effects a graded thermal profile in the patterned resist layer 220. For example, a temperature of the patterned resist layer 220 increases along a direction substantially perpendicular to the wafer 210. In the depicted embodiment, a surface associated with the front side 212 of the wafer 210 (front surface) and a surface associated with the backside 214 of the wafer 210 (back surface) are substantially parallel to one another and are substantially in an x-y plane, such that a z-direction is substantially perpendicular to the wafer 210. In FIG. 4, the temperature of the patterned resist layer 220 increases along the z-direction, such that at a temperature (T1) of the portion 220B is less than a temperature (T2) of the portion 220A. The graded thermal profile ensures that the portion 220B has a temperature sufficient to facilitate removal of the portion 220A by the etching process while ensuring that the portion 220B has a temperature less than its associated popping temperature. The hardened, crust portion 220A is thus removed without hardening and/or popping issues that often arise during conventional resist removal processes.
[0015] In FIG. 5, a second resist removal process step is performed to remove the remaining portion of the patterned resist layer 220. In the depicted embodiment, the second resist removal process removes the portion 220B and any remaining hardened portion 220A of the patterned resist layer 220. The second resist removal process step includes a resist stripping process 270. In the depicted embodiment, the resist stripping process 270 is a plasma ashing (etching) process having an etching chemistry and etching conditions suitable for removing the remaining patterned resist layer 220 (here, portion 220B and any remaining hardened portion 220A). For example, the etching chemistry includes a fluorine-containing gas (such as CF4), an oxygen-containing gas (such as O2), a nitrogen-containing gas (such as N2), other suitable gas, or combination thereof. In an example, the resist stripping process 240 and the resist stripping process 270 implement the same etching chemistries, such that a continuous flow of gas is maintained during the first and second resist removal process steps. In another example, the resist stripping process 240 implements an etching chemistry different than the resist stripping process 270. Further, the resist stripping process 240 and the resist stripping process 270 can implement same or different etching conditions.
[0016] The second resist removal process step further includes a heating process 280. In the present example, the heating process 280 is performed during the resist stripping process 270. The heating process 280 applies a heat source to the backside 214 of the wafer 210, thereby heating the patterned resist layer 220 from the backside 214 of the wafer 210. In the present example, the wafer temperature is raised to about 100° C. to about 300° C. Raising the temperature of the wafer 210 increases the temperature of the pattered resist layer 220, thereby increasing the etching rate of the patterned photoresist layer 220. The heating process 280 also effects a graded thermal profile in the patterned resist layer 220. For example, in the depicted embodiment, a temperature of the patterned resist layer 220 decreases along the z-direction, such that the temperature (T1) of the pattered resist layer 220 is greater than the temperature (T2) of the pattered resist layer 220. The graded thermal profile ensures that the portion 220B has a temperature sufficient to facilitate removal of the portion 220A by the etching process. The second resist removal process step is performed for a predetermined time or until the patterned resist layer 220 is removed from the wafer 210, as illustrated in FIG. 6. In an example, a cleaning process is performed to remove any residue left on the wafer after the first and second resist removal process steps.
[0017] The first and second resist removal process steps described herein facilitate improved removal of the patterned resist layer 220 when compared to conventional resist removal techniques. The first resist removal process step may be referred to as a low temperature ashing process, and the second resist removal process step may be referred to as a high temperature ashing process. The combined low and high temperature ashing processes of the disclosed resist removal technique prevent or minimize resist residue issues that arise during the conventional resist removal techniques. For example, the combination of front side and backside wafer heating provides sufficient temperatures for increasing the etching rate of the patterned resist layer 220 (particularly the hardened, crust portion 220A) while ensuring that the temperatures do not induce further hardening or popping phenomena of the patterned resist layer 220. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.
[0018] The present disclosure provides many different embodiments for removing a resist layer. An exemplary method includes performing an etching process to remove a resist layer from a wafer. During the etching process, a first heating process is performed to effect a first graded thermal profile in the resist layer, the first graded thermal profile having a temperature that increases along a direction perpendicular to the wafer. Further during the etching process, after performing the first heating process, a second heating process is performed to effect a second graded thermal profile in the resist layer, the second graded thermal profile having a temperature that decreases along the direction perpendicular to the wafer. The wafer has a frontside and a backside, the resist layer is disposed over the front side of the wafer, the first heating process includes heating the resist layer from the front side of the wafer, and the second heating process includes heating the resist layer from the backside of the wafer. In an example, the method further includes, before performing the etching process, performing an ion implantation process to the wafer using the resist layer as a mask.
[0019] In an example, the first heating process further includes cooling the backside of the wafer. In an example, heating the resist layer from the front side of the wafer includes applying an intermittent heat source to the front side of the wafer, and heating the resist layer from the backside of the wafer includes applying a constant heat source to the backside of the wafer. In an example, the resist layer includes a hardened portion, and applying the intermittent heat source to the front side of the wafer includes, during the etching process, cycling the heat source on and off until the hardened portion of the resist layer is substantially removed, thereby leaving a remaining portion of the resist layer. In an example, the etching process is performed and the constant heat source is applied to the backside of the wafer until the remaining portion of the resist layer is removed. In an example, the heat source is cycled off before a temperature of the resist layer that is not hardened reaches a popping temperature.
[0020] In another example, a method includes forming a patterned resist layer over a wafer; and performing an ashing process to remove the patterned resist layer from the wafer. During the ashing process, a first heating process heats the patterned resist layer from the front side of the wafer while maintaining a wafer temperature of the wafer less than a popping temperature of the patterned resist layer, and after performing the first heating process, a second heating process heats the patterned resist layer from the backside of the wafer. In an example, heating the patterned resist layer from the front side of the wafer includes applying an intermittent heat source to the front side of the wafer, and heating the patterned resist layer from the backside of the wafer includes applying a constant heat source to the backside of the wafer. In an example, the patterned resist layer includes a hardened portion, and applying the intermittent heat source to the front side of the wafer includes, during the ashing process, cycling the heat source on and off until the hardened portion is substantially removed, thereby leaving a remaining portion of the patterned resist layer. In an example, the ashing process is performed and the constant heat source is applied to the backside of the wafer until the remaining portion is removed. In an example, maintaining the wafer temperature less than the popping temperature of the patterned resist layer includes maintaining the wafer temperature less than about 90° C.; and heating the patterned resist layer from the front side of the wafer includes cycling a heat source on and off to raise a temperature of crust of the patterned resist layer to about 100° C. to about 300° C. In an example, maintaining the wafer temperature less than the popping temperature of the resist layer includes cooling the wafer from the backside to keep a temperature of a non-crust portion of the patterned resist layer less than an associated popping temperature of the non-crust portion. In an example, the method further includes performing an ion implantation process using the patterned resist layer as a mask
[0021] In yet another example, a method includes providing a wafer having a front side and a backside; forming a patterned resist layer over the front side of the wafer; performing an ion implantation process on the wafer using the patterned resist layer as a mask, wherein the patterned resist layer includes a crust after the ion implantation process; and performing a dry etching process to remove the patterned resist layer from the wafer. A first heating process is performed during the dry etching process until the crust of the patterned resist layer is substantially removed, thereby leaving a remaining portion of the patterned resist layer, wherein the first heating process includes applying a first heat source to the front side of the wafer, wherein the first heat source is cycled on and off. A second heating process is performed during the dry etching process to remove the remaining portion of the patterned resist layer, wherein the second heating process includes applying a second heat source to the backside of the wafer. In an example, the first heating process further includes cooling the wafer from the backside. In an example, applying the first heat source to the front side of the wafer and cooling the wafer from the backside raises a temperature of the crust without raising a temperature of the patterned resist layer above a popping temperature
[0022] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Patent applications by Buh-Kuan Fang, Zhubei City TW
Patent applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Patent applications in class Combined with coating step
Patent applications in all subclasses Combined with coating step
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2014-07-24 High resolution printing technique
2014-09-04 Stress memorization technique
2014-09-04 Resist composition and method for producing semiconductor device
2016-05-26 Method of improving line roughness in substrate processing
2016-05-26 Resist underlayer film-forming composition contaning pyrrole novolac resin
2016-05-19 Air gap formation in interconnection structure by implantation process
2016-05-19 Photoresist pattern trimming methods
2016-05-12 Method for manufacturing silicon carbide semiconductor device
2015-07-02 Metal gate transistor and method for tuning metal gate profile
2013-06-13 Semiconductor structure having a polysilicon structure and method of forming same
2013-04-04 Methods for ion implantation
Top Inventors for class "Semiconductor device manufacturing: process"
1 Shunpei Yamazaki
3 Kangguo Cheng
4 Chen-Hua Yu
5 Devendra K. Sadana


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AAP Teaching Fellowships provide debt relief to young periodontal educators.
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text:
Q: How to prevent frequently visited websites' history get deleted as I cleared the browsing history? I just cleared 15,000 browsing history from Google Chrome, that much histories slow down the browser a lot. After I cleared it, it runs faster, but the search bar doesn't do the shortcut trick anymore (E.g: When I type in letter f, it lists out websites like facebook.com), I know it's because the history is gone, is it any way to prevent frequently visited websites (or manually selected) get deleted as I cleared the browsing history?

A: Okay I found a solution:

*

*Clear Browing History

*Visit all the websites you think you will visit in the future.

*Close the browser.

*Go to "C:\Users\Username\AppData\Local\Google\Chrome\User Data\Default", right click on a file called History, select properties, and check Read-only.

*This will prevent Google Chrome storing browsing history, so I don't need to clear browsing history anymore.

It still writing down the history though, but it won't save the URL typed in the address bar for the prediction service. That's fine for me now, because that's the main issue to me.

redpajama_set_name: RedPajamaStackExchange


text:
Home World Africa news Nelson Mandela suffers from lung infection
Nelson Mandela suffers from lung infection
Nelson Mandela, South Africa's first black president, is being treated for a lung infection, the president's office has said.
This is the first time officials have revealed why Nelson Mandela, 94, was rushed to a military hospital in the capital, Pretoria, on Saturday.
Tests showed a "recurrence of a previous lung infection", presidential spokesman Mac Maharaj said.
Nelson Mandela is responding to his treatment, Mac Maharaj added.
News of the hospital stay has prompted much concern in South Africa.
The former president is regarded by most South Africans as the father of the nation, having inspired them to fight for democracy.
He led the struggle against white-minority rule before being elected the first black president in democratic elections in 1994.
Despite being imprisoned for 27 years by the apartheid government, after his release he forgave his former enemies and urged South Africans of all races to work together and seek reconciliation.
He was awarded the Nobel Peace Prize in 1993.
News that the frail Nelson Mandela has another lung infection is likely to generate considerable anxiety.
Nelson Mandela, South Africa's first black president, is being treated for a lung infection
The officials who have visited Nelson Mandela in hospital since Saturday have all said he is doing well.
He was flown to hospital on Saturday from his home in Qunu village in Eastern Cape province by the military, which is responsible for his healthcare.
Local media reported that the decision to move him was taken so quickly that some family members and his own foundation were initially unaware of it.
But Mac Maharaj has repeatedly said that Nelson Mandela is doing well in hospital and there is no cause for alarm.
Nelson Mandela was last admitted to hospital in February when he was treated for abdominal pain.
In January 2011, he was treated for a serious chest infection.
While in prison in the 1980s, Nelson Mandela was also diagnosed with tuberculosis.
Nelson Mandela retired from public life in 2004 and has been rarely seen in public since.
[youtube j867rpfLHoU]
first black president
lung infection
mac maharaj
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