abstract
the interest in brain-like computation has led to the design of a
plethora of innovative neuromorphic systems. individually, spiking neural
networks (snns), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. despite the popularity of event-driven
snns in software, very few digital hardware architectures are found. this
is because existing hardware solutions for event management scale badly
with the number of events. this paper introduces the structured heap
queue, a pipelined digital hardware data structure, and demonstrates
its suitability for event management. the structured heap queue scales
gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven snns. the scaling is
linear for memory, logarithmic for logic resources and constant for processing time. the use of the structured heap queue is demonstrated on
field-programmable gate array (fpga) with an image segmentation experiment and a snn of 65 536 neurons and 513 184 synapses. events can
be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel
image is segmented in 200 ms.