ITEM 1. BUSINESS
Overview
We are a leading provider of software products that enable the rapid and effective design and verification of large, complex semiconductors used in networking and communications, computer and peripheral, consumer, automotive, military/aerospace and other electronics systems. Our software products perform essential steps in the process of designing and verifying semiconductors that are tailored to perform a specific function including field programmable gate arrays (“FPGAs”) and application specific integrated circuits (“ASICs”), which include a class of ASICs called structured or platform ASICs (“structured ASICs”). We employ proprietary logic synthesis, physical synthesis and debug technology to simplify, improve and accelerate the design and verification of large complex FPGAs and ASICs. We believe our semiconductor design software products, coupled with our responsive customer support, assist our customers to meet performance goals and decrease the time to market of their electronic systems.
Industry Background
Manufacturers of networking and communications, computer and peripheral, consumer, automotive, military/aerospace, digital video, industrial, scientific, medical and test and measurement systems employ a wide variety of advanced semiconductors, including FPGAs and ASICs, in their products. Unlike off the shelf standard function semiconductors, FPGAs and ASICs are tailored to perform specific functions defined by electronic product designers. FPGAs are semiconductors that are customized or programmed to perform a specific function after the semiconductors are manufactured, whereas ASICs are customized during the manufacturing process.
FPGAs and ASICs are used to implement proprietary intellectual property and to provide the equipment manufacturer’s products with enhanced performance, flexibility and differentiation. FPGAs provide equipment manufacturers with the ability to create and modify semiconductor designs quickly and easily. With FPGAs, electronics manufacturers can make changes to the design even after the customer uses the product. This ease of creation and modification helps electronics manufacturers meet time to market requirements by shortening development times. In this respect, FPGAs provide electronic equipment manufacturers the ability to get to market quickly and the flexibility to update their products to address rapidly changing industry and interoperability standards. ASICs, on the other hand, can achieve higher performance, lower power consumption and lower unit cost than FPGAs when produced in volume. However, ASICs generally have longer development cycles as well as lengthy and expensive custom fabrication processes prior to shipment. We believe that the relative ease of use, design flexibility and shortened time to market of FPGAs and the expanded capacity, performance and lower power consumption and unit cost of ASICs will continue to fuel growth in the use of these semiconductors in electronic equipment.
The capacity of FPGAs and ASICs on average has increased due to advanced manufacturing processes. These advanced manufacturing processes help improve performance, lower overall part costs and further expand the breadth of applications for which FPGA and ASIC semiconductors can be used.
Challenges of designing FPGAs and ASICs
As more complex FPGAs and ASICs with higher capacity are used in the design of electronic equipment, these FPGAs and ASICs often require significant resources to design and test their functionality. Large semiconductor designs require more time to develop and test, which may limit the equipment manufacturer’s ability to get to market quickly.
Electronic products are increasingly incorporating digital signal processing (“DSP”) functionality using FPGAs which can offer an order of magnitude performance increase over standard DSP processors. However, an obstacle in implementing DSP functionality in FPGAs is that it is a very time-consuming process to explore different design architectures in order to achieve optimal performance. Traditional techniques for converging on a solution use very iterative and manual methods that frequently do not produce optimal results.
Complex ASIC design, using the traditional cell-based library approach for implementation, has become increasingly costly as a typical 130 nanometer cell-based ASIC design project in 2004 required an investment in excess of $5 million for EDA tools, design resources and initial semiconductor manufacturing costs. In additional to rising costs, the time it takes to complete a typical cell-based ASIC has lengthened as verification of cell-based ASICs has become increasingly difficult. These and other economic forces have resulted in a declining number of cell-based ASIC design starts over the past three years.
Electronic product designers seek design solutions that produce high-performance designs, increase productivity, reduce costs and are easy to learn and use. To achieve these objectives, electronic product designers, including equipment manufacturers using FPGAs and ASICs, have recognized the advantage of certain software solutions which address critical steps in the development cycle.
To date, these software solutions have focused on several functions in the development cycle including:
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Logic synthesis. Logic synthesis software compiles a high level textual description of the desired function of a semiconductor into an optimized network of elements, each of which is known as a logic or memory element. Because the logic and memory elements must interact and exhibit high performance, logic synthesis is critical to reduce the number of required components and improve the frequency at which the semiconductor can be operated.
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Physical synthesis. Physical synthesis software combines the function of logic synthesis software with some of the functions of placement and routing software. Placement and routing software processes the optimized description of the semiconductor created by logic synthesis to place the logic and memory
elements in locations on the semiconductor and to assign routes for wires between those placed elements. The goal is to keep wires short in order to maximize performance. Because a physical synthesis system controls the locations of elements, it can identify performance limitations more easily and fix them with a combination of placement changes and logic synthesis optimizations.
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Verification. Verification software uses the information from the functions and integrity of the semiconductor to test whether it will perform as intended. For example, with ASICs, the designer must verify whether the semiconductor will perform as intended and whether the proposed design works with other components in the electronics system, such as software or a communication module. Mistakes not identified prior to ASIC chip manufacture are costly and can require weeks or months for correction.
Our Solution
Our software solutions improve performance and shorten development times for complex FPGAs and ASICs by simplifying, improving and automating key design planning, custom logic synthesis, physical synthesis and verification functions. Our products utilize a number of sophisticated mathematical algorithms, electrical engineering techniques and advanced software operations.
A key feature of our products is their ability to generate and display concurrently four views of a semiconductor design-the textual design description, a highly abstract graphical representation of the design description, an optimized, detailed diagram showing the various elements of the semiconductor design and a physical representation of the design elements. As the designer changes the textual description, the other three views automatically highlight the selected areas of the design. These alternate representations aid the designer to manipulate and optimize the design and diagnose problems. Our software products also provide the following features and benefits to our customers and their electronic product designers:
Design goal achievement. Our products enable designers to design products quickly that meet or exceed their semiconductor performance and capacity utilization goals. Efficient and cost-effective manufacturing of a semiconductor depends on full utilization of the semiconductor’s capacity. Users specify design constraints through our graphical user interface and then use our products to automatically process the design to achieve function, performance and capacity goals. The complex optimization operations that our products perform employ the most advanced features of the target semiconductor and result in a highly optimized design that improves performance of the electronic equipment. Our solutions may also enable designers to use less costly semiconductors to achieve the same performance goals, thus reducing end system costs.
Custom ASIC synthesis. Today’s cell-based ASIC design and manufacturing processes can be too costly for many low to mid-volume ASIC applications. The semiconductor industry has begun to address this by introducing structured ASICs. These new ASIC devices employ innovative architectures to remove many of the cell-based ASIC verification problems, including clock management, test and power and signal integrity. They come mostly prefabricated, requiring only a few metal/via masks for customization, thus significantly reducing ASIC manufacturing costs and improving time to market. While these new devices deliver a more deterministic and lower cost design alternative than cell-based ASICs, their structure also introduces a reduction in achievable performance and utilization from typical cell-based synthesis tools. To help address this issue, we have worked closely with leading ASIC manufacturers such as Fujitsu Microelectronics, NEC Electronics Corporation and LSI Logic Corporation to provide custom architecture-specific synthesis support for their structured (or platform) ASIC devices. This in turn returns much of this lost performance and utilization moving from a cell-based design methodology as well as providing a more streamlined design flow that accelerates the design process.
Accelerated time to market. Electronic product designers require time efficient solutions. Our products optimize small designs in seconds and large designs in minutes or hours, which we believe is significantly faster than alternative software. Reduced execution time significantly shortens time to market because logic synthesis, physical synthesis and verification are typically performed repeatedly during the design process. Our products allow designers to select an optimal design from various design possibilities in the same amount of time that
alternative software would require to evaluate a single solution. In addition, our physical synthesis products produce design results that correlate well with the completed physical design, thus reducing the number of design iterations typically introduced with design tools that use less accurate statistical wire length models.
Ease of use. Our products are designed to be easy to install, learn and use. The user enters only information that is specific to the design. Our products employ complex algorithms, but their sophistication makes the designers’ work simpler. We believe both experienced and novice users value our products because they provide highly optimized designs that require a minimum level of design tool specific effort as compared with conventional approaches. We believe our solutions’ ease of use and graphical representations make them accessible to a larger group of designers without sacrificing quality of results or achievement of design goals. Our creation of easy to use powerful design tools has the added benefit of reducing the amount of technical support required to assist customers in tool use. Our technical support resources can focus on more design related support, which is of more value to customers.
Optimal product solutions. We believe our products provide significant advantages for designing FPGAs, structured ASICs and cell-based ASICs. Our FPGA solutions can implement optimized designs for the largest available FPGAs. Synplify Pro, our leading FPGA synthesis product, enhances electronic product designer productivity as well as the performance for complex designs. Amplify FPGA Physical Optimizer, our physical synthesis product for FPGAs, incorporates specialized features that can improve performance and provide results that reliably close customer timing requirements. Synplify DSP, our newest product introduced in the third quarter of 2004, is a DSP synthesis tool that performs high-level DSP optimizations from a Math Works Simulink specification. We believe Identify, our FPGA debug product, is the first and only software tool that allows FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their Register Transfer Level (“RTL”) source code and enables functional verification at speeds far faster than traditional RTL simulators.
Certify, our ASIC verification product, includes features that enable designers to functionally validate large designs using high-speed prototypes. Without these prototypes, ASIC designers may not be able to test their designs at or near the ASIC’s performance target prior to chip signoff, thus increasing the likelihood of a design error. Our Fortify family of power planning and analysis products helps create and validate that the ASIC’s power network maintains its voltage integrity during design operation. Synplify ASIC, our cell-based ASIC RTL synthesis product, is capable of implementing ASIC designs and design blocks as large as several million gates in a single operation, saving time and improving results in these more complex semiconductors. In addition, Synplify ASIC often produces designs that are smaller than competing solutions, providing enormous value to customers with high volume applications. Amplify RapidChip and Amplify ISSP, our physical synthesis products for structured ASIC design, are intended specifically to improve utilization and performance and to more efficiently close customer timing requirements. We believe Amplify RapidChip and Amplify ISSP are the first ASIC physical synthesis products that bring custom architecture-specific support while also offering optimal timing correlation to the final routed structured ASIC design. This tight correlation allows LSI, NEC and Fujitsu to more quickly close timing on customer designs in their design centers, ultimately producing completed designs sooner for their customers.
Comprehensive customer support. Because of the complex nature of our customers’ design activities, we believe our support services are valuable to our customers. We emphasize rapid resolution of customer questions by staffing our customer support operation with knowledgeable personnel. We have provided our customer service organization with sufficient resources to assist our staff in responding to customer problems often within 24 hours. We also make available through our web site information regarding support solutions, problem submission and problem status.
Products
FPGA Solutions
Revenue from our software products for use with FPGAs represented 83%, 86% and 93% of our total revenue in 2004, 2003 and 2002, respectively.
Synplify and Synplify Pro Products
In 1995, we introduced Synplify, our logic synthesis product that enables customers to implement their designs in FPGAs quickly and easily. In May 2000, we launched Synplify Pro, our advanced FPGA logic synthesis product incorporating improved productivity features and offering enhanced results. To perform logic synthesis, our Synplify and Synplify Pro products employ proprietary optimization algorithms, which we call Behavior Extracting Synthesis Technology. Our Synplify and Synplify Pro products take advantage of specialized features provided by the FPGA manufacturers that improve performance for a particular design. Logic synthesis software products transform a high level design specification into a format comprised of logic elements and wires interconnecting those elements that is ready for implementation in a semiconductor. Logic synthesis is a primary determinant of design performance. As a result, logic synthesis has a significant impact on the overall performance of the electronic system in which the FPGA resides. We believe that our Synplify and Synplify Pro products have the industry’s highest performance results on the basis of speed and capacity utilization of the resulting FPGA. In addition, our Synplify Pro product automatically identifies and restructures certain types of control circuits to achieve better performance.
Because logic synthesis is performed multiple times during the design process, the less time synthesis requires, the quicker the engineer can complete the design process. We believe our Synplify and Synplify Pro products have the industry’s fastest run times. We employ algorithms that scale linearly in run time with the size of the design. Small designs can be synthesized in seconds and designs for the newest, largest FPGAs can be synthesized in hours or even minutes. Synplify and Synplify Pro require only the input of readily available design data. This information is entered via a simple to use graphical user interface, which allows designers to specify all design constraints in a single location quickly.
HDL Analyst Product
In 1997, we introduced HDL Analyst, a software product that is available as an option to our Synplify product and is incorporated into most of our other products. A key feature of our HDL Analyst product is its ability to generate and display concurrently three views of a semiconductor design-the textual design description, a highly abstract graphical representation of the design description and an optimized, detailed diagram showing the various elements of the semiconductor design. As the designer changes the textual description, the changes are automatically reflected in the other two views. Our HDL Analyst product enables designers to quickly identify performance bottlenecks and identify other opportunities for improvement.
Amplify FPGA Physical Optimizer Product
In March 2000, we introduced Amplify FPGA Physical Optimizer, a software product specifically created for achieving optimum results for FPGA devices. The key innovative and differentiating feature of our Amplify FPGA product is the method by which it uses and improves physical implementation information provided by the designer during the synthesis process to produce an improved design. We believe that Amplify FPGA was the industry’s first commercially available physical synthesis product for FPGA design. In October 2001, we introduced our second generation of Amplify FPGA that utilizes Total Optimization Physical Synthesis, or TOPS, which is based on significant new algorithmic developments that produce precise physical placement while performing optimization of logic on critical paths. By performing detailed placement of logic, the TOPS technology is able to achieve even more predictable timing estimations, thus reducing the number of iterations required to close on timing. The user provides this physical implementation information through a graphical user interface, and our Amplify FPGA product utilizes this information to improve design performance.
We believe Amplify FPGA improves time to market. Without physical optimizations, users must undertake numerous time-consuming iterations of design, constraint and software option changes in hopes of creating a design that has the desired performance and functionality.
FPGA components are sold in performance grades. An FPGA offering marginally higher performance may cost substantially more than the next lower grade. We believe that our Amplify FPGA product assists designers to use less expensive components to meet the same design requirements.
As design sizes increase, there is a trend toward team design of a single FPGA in which portions of the design are allocated to different persons. Amplify FPGA has advanced design planning features that can be used to achieve higher performance and design stability.
Identify Product
In November 2002, we acquired a key RTL debug product from Bridges2Silicon, Inc. which we introduced under a new Synplicity product name, Identify. This product allows engineers to debug their FPGAs directly from their RTL source code during chip operation. Identify’s efficient method of functional hardware debug helps engineering teams avoid what would otherwise be a tedious and costly debug using hardware analyzers.
We believe that Identify is the only software product that allows FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than today’s RTL simulators and enables the use of in-system stimulus for applications-like networking, audio and video and hardware/software co-development. Identify allows designers to directly select signals and conditions in their RTL source code for debugging and the results are viewed directly in the RTL source code. The Identify product can also save results in standard VCD format that can be used with most waveform viewers.
Synplify DSP Product
In July 2004, we introduced Synplify DSP, our first system level synthesis product created to bridge between system level DSP design and analysis and semiconductor hardware design. Synplify DSP performs high-level DSP optimizations from a Simulink specification. These special DSP optimizations allow designers to capture the behavior needed for their DSP algorithm without worrying about the specific implementation in hardware. Synplify DSP automatically produces a highly optimized, technology independent implementation of the design ready for RTL synthesis.
DSP designers are increasingly targeting FPGA hardware for implementation of their high-performance DSP designs. FPGAs can achieve a performance of hundreds of millions of operations per second, which far exceeds the performance available in more traditional DSP processors. Today’s FPGAs also contain large quantities of DSP blocks and multipliers, facilitating efficient and parallel implementation of DSP functions in programmable logic. Through this hardware parallelism, FPGAs can achieve performance levels that exceed the performance available in more traditional DSP processors. Until the introduction of Synplify DSP, however, there has been no automated way to get a design specified at the algorithm level from tools such as MATLAB®/Simulink® by The MathWorks, into high-quality RTL, architecture independent code suitable for semiconductor implementation. A common implementation path has been to hand-code the RTL with numerous iterations between the DSP algorithm architect and the RTL hardware designer, which is error prone and time consuming. We believe Synplify DSP offers the only automated way to fully optimize DSP design expressed in the SimuLink environment into our RTL synthesis tools for FPGA or ASIC design.
ASIC Solutions
Revenue from our software products for use with ASICs represented 17%, 14% and 7% of our total revenue in 2004, 2003 and 2002, respectively.
Certify Product
In 1999, we introduced Certify, a software product for the verification of ASICs using prototypes consisting of multiple FPGAs. Our Certify product enables design teams to create hardware prototypes early in the design process when design changes are easier and less costly. Certify also assists customers in verifying that the final system will work as specified, will work with system level software and will meet customer requirements. Customers who use our Certify product to define their prototypes can begin system integration, software verification, chip verification, system verification and end customer validation earlier than other approaches to functional verification. Certify can process multimillion gate designs in a single pass without the complex scripts commonly required by ASIC synthesis products. We believe Certify is the only product that processes ASIC design and produces multi-FPGA prototypes at the RTL level, enabling rapid iterations of the prototype during the verification stage.
Our Certify product is a verification product incorporating synthesis and enabling the user to create prototypes automatically direct from the user’s textual design specification. The ability to operate the prototype at or near the speed of the final product can be very important for ASIC verification. Other available approaches, such as logic simulation software, emulation systems or reconfigurable prototyping systems, cannot run at a sufficient performance level for many applications, such as mobile telephony, optical switching or streaming video in real time. Our Certify product enables designers to create FPGA-based prototypes that operate at or near the speed of the final product and at substantially higher frequencies than other available approaches by using our proprietary embedded synthesis technology that optimizes the final prototype performance. Certify achieves high performance for a multi-FPGA semiconductor prototype by optimizing all FPGAs in the prototype simultaneously.
The Certify product also includes schematic representations of several commercially available hardware prototyping systems to enable rapid prototype implementation without the need to create and build a custom prototyping platform. By partnering with leading hardware vendors via our “Partners in Prototyping” program, we accelerate prototype implementation and make FPGA-based prototyping accessible to customers who may otherwise be unwilling or unable to develop a custom hardware platform of their own.
Synplify ASIC Product
In June 2001, we introduced Synplify ASIC, our logic synthesis product for ASIC design. Our Synplify ASIC product offers higher design capacity as demonstrated by its ability to process designs or design blocks up to several million gates in a single compilation and often produces better quality of results. The leading competitive offering requires customers to disassemble the design into a large number of smaller blocks, process each of these independently and then reassemble the result. The high level of expertise required for this process is eliminated in the Synplify ASIC synthesis approach. In addition, processing the design as a single entity or as larger block entities reveals further opportunities for optimization, which can improve chip performance and reduce chip costs. We believe our Synplify ASIC product processes designs several times faster and up to 15% smaller than the leading competitive product, reducing the overall cost of an ASIC and yielding substantial cost savings for higher volume applications. In addition to the ease-of-use advantage afforded by its high capacity, we believe our Synplify ASIC product is easy to learn. Synplify ASIC employs an intuitive, graphical user interface and incorporates a high degree of automation.
In April 2003, we introduced the first custom architecture-specific synthesis version of Synplify ASIC for NEC Electronics’ new structured ASIC device, Instant Silicon Solution Platform (“ISSP”). ISSP utilizes a course grained base logic cell which is similar to the logic cell structure used in FPGAs, as opposed to the sea of transistors approach offered in a cell-based ASIC. This type of silicon architecture is not optimized by today’s conventional ASIC synthesis methods that use a simple library approach. We have utilized our FPGA experience in synthesizing logic to FPGA fabrics to optimize and pack logic much more efficiently for the ISSP device. We believe this custom synthesis approach yields substantial quality of results improvements that result in smaller and faster designs.
Amplify RapidChip and Amplify ISSP Product
In December 2003, we released our first physical synthesis product for LSI Logic’s new platform ASIC device called RapidChip. The Amplify RapidChip product is a customized physical synthesis product that uniquely targets LSI Logic’s RapidChip architecture and sets a new standard for ASIC logic designer productivity. In addition to achieving better quality of results compared to other synthesis approaches, the customizations in this physical synthesis technology also provide extremely tight correlation between predicted timing from Amplify RapidChip and the actual completed physical design performed by LSI Logic. This tight correlation eliminates or reduces design iterations between the customer and LSI Logic due to timing closure issues, and allows for rapid ASIC design development.
In May 2004, we released our second physical synthesis product optimized specifically for NEC Electronics’ ISSP. The Amplify ISSP product is a customized physical synthesis product that optimally targets NEC Electronics’ ISSP architecture and offers a new standard for ASIC logic designer productivity. In addition to achieving better quality of results compared to other synthesis approaches, the customizations in this physical synthesis technology also provide extremely tight correlation between predicted timing from Amplify ISSP and the actual completed physical design performed by NEC Electronics’ design centers. This tight correlation eliminates or reduces design iterations between the customer and NEC Electronics due to timing closure issues, and allows for rapid ASIC design development.
We have also been contracted by Fujitsu Microelectronics to customize our Amplify physical synthesis product for their AccelArray structured ASIC solution, which we expect to release in the first half of 2005.
Fortify Products
In July 2002, we acquired key power planning and analysis products from IOTA Technology, Inc. (“IOTA”) which we introduced under a new Synplicity product family name, Fortify. Within this product family are two key products that create and verify an ASIC’s power network for voltage integrity.
PowerPlanner Product. Fortify PowerPlanner allows the physical designer to experiment with various power grid topologies and gain an early insight into the voltage integrity and potential electromigration issues in the design before complete logic implementation. Upon achievement of a successful power grid, PowerPlanner’s integrated PowerRoute technology can create the final power grid for use by chip implementation place-and-route tools.
RealPower Product. Fortify RealPower is a post synthesis and physical implementation power grid verification product. It analyzes the voltage integrity by computing the voltage drop and performs electromigration analysis, each on the individual library cells using its embedded Dynamic Power Calculator. The result is a fast engine that can handle detailed physical information and correct reliability and signal integrity issues before they lead to design revisions or field failures.
Customer support
Our products are designed to be utilized quickly and effectively by our customers and to minimize the level of support from us for the designer to be productive. Our customers use our products along with design software from semiconductor manufacturers and from other third party design software developers. The overall semiconductor design process is complex, and our customers may seek assistance from us with various aspects of our products’ functionality in their semiconductor design process. We believe that high quality customer support of our customers’ activities is important to the success of our business. We have developed and expect to continue to improve our comprehensive support organization to manage customer accounts. We provide support for our products primarily from our Sunnyvale, California and Bangalore, India locations. In the long term, we plan to expand existing, and may establish additional, support sites outside of the United States to support customers in those markets.
We provide technical support to our customers through maintenance services. Time-based licenses include maintenance services for the duration of their respective terms. For each sale of a perpetual or two or three-year term license, the first year of maintenance is generally sold with the license. Thereafter, customers may annually elect to renew maintenance. We price our maintenance service at 15% or 20% of the perpetual list license fee, depending on the product, on a per license basis. Our maintenance service offering provides us with a valuable, ongoing revenue stream.
We believe that the majority of our customers will continue to renew maintenance because the rate of innovation in the semiconductor industry, especially with FPGAs, is high, and equipment manufacturers expect us to support the latest components as soon as they are available. Customers paying maintenance receive software updates for new components when and if we make these updates available. These frequent releases typically include support for new components and enable our customers to optimize their designs or create prototypes using those components. We work closely with leading FPGA and ASIC manufacturers to incorporate support for new components as quickly as possible.
We generally provide our support via electronic mail, our web site and telephone. Our support organization may assist customers with technical support during the customers’ initial product installation and configuration. However, our support organization devotes the majority of its efforts to assisting customers to resolve questions about our products’ functionality that can arise from the customers’ design tasks. Effective execution of these customers’ design tasks requires highly skilled engineers familiar with our customers’ design tasks as well as familiarity with third party products that may be used by the customer in conjunction with our products. Our support staff consists of engineers with substantial design experience.
Customers
As of December 31, 2004, we had over 1,800 active customers. Of that total, more than 280 were first-time customers in 2004. Although in the past our customers were concentrated in the networking and communications industries, in 2004 our customers were more evenly distributed over networking and communications, military and aerospace, computer and peripheral, consumer, semiconductor and other general, medical and industrial industries. Our customers often buy licenses for a single location, department or division, and then, based upon the initial success of the products, later expand their use of our products into other parts of their organizations. We believe we can sell our existing products more extensively within our existing customer base and sell them new products as we expand our product line. We will continue to pursue enterprise-wide sales as appropriate. We have customers throughout North America, principally the United States, as well as in Europe, Japan and other parts of Asia. See Note 11 of the Consolidated Financial Statements for a full description of financial information about geographic areas. See also “Factors Affecting Future Operating Results” regarding the risks associated with our international operations under Management’s Discussion and Analysis of Financial Condition and Results of Operations. In 2004, 2003 and 2002, no end-user customer comprised more than 10% of our revenue.
Marketing and Sales
Marketing
We focus our marketing efforts on creating awareness for our products and generating leads for our sales organization. Our strategy is to distinguish our products by their high level of design performance, ease of use and time to market advantages. We employ a wide variety of communication channels to inform customers and potential customers about our products. These channels include our, or our key partners’, website, print and web advertising, public relations, web-based seminars, live seminars, tradeshows and electronic mail notifications to customers about new product releases.
Sales
We license our software products primarily through our direct sales organization, as well as distributors and other strategic partners.
Direct Sales
Our direct sales efforts target customers who design semiconductors for networking and communications, military/aerospace, computer and peripheral, consumer, automotive, and other electronics systems. As of December 31, 2004, our direct sales staff consisted of 84 employees based in 22 offices. Direct sales accounted for 88% of our total revenue in 2004 and 2003, and 87% of our total revenue in 2002. Each of our sales teams represents a geographic region and includes a sales manager and applications engineer, and may also include an inside sales representative. The direct sales team also relies on distribution and strategic partners for demand creation and leads. Our typical sales cycle varies by product from two weeks to several months, with our ASIC products generally having longer cycles than our FPGA products.
We currently have domestic direct sales offices in Sunnyvale, California; San Diego/Newport Beach, California; Beaverton, Oregon; Woodinville, Washington; Boulder, Colorado; Austin, Texas; Dallas, Texas; Lisle, Illinois; Durham, North Carolina; Bel Air, Maryland; and Andover, Massachusetts. We also have international direct sales/marketing offices in or near Maidenhead, United Kingdom; Aix-en-Provence, France; Venray, Netherlands; Dornach, Germany; Stockholm, Sweden; Netanya, Israel; Bangalore, India; Shanghai, P.R.C; Bejing, P.R.C; Hsinchu City, Taiwan; Seoul, South Korea; and Tokyo, Japan.
Indirect sales
In addition to our direct sales strategy, we have indirect sales channels through distributors. Our relationships with distributors help extend our reach to more customers. Distributors either assist our direct sales staff or are our sole sales and support representatives in territories that include portions of Europe and Asia. Our international distributors typically perform marketing, sales and technical support functions in their respective country or region. We actively train our international distributors in both our products and sales methods. In general, each one may distribute directly to the customer, via other resellers or through a mixture of both channels. Our distributor agreements do not provide for rights of return, stock rotation or price protection for the distributor. Revenue from distribution was 4% of our total revenue in 2004, 5% of our total revenue in 2003 and 6% of our total revenue in 2002. We also generate some revenue through certain FPGA manufacturers as discussed below.
Seasonality
In the past we have experienced fluctuations in the sale of licenses for our products due to seasonality. For example, sales may decline during the summer months, particularly in European markets, and we have experienced and anticipate we will continue to experience relatively lower product bookings in the first quarter of our fiscal year due to patterns in the capital budgeting and purchasing cycles of our current and prospective customers and the economic incentives for our sales force.
Strategic Relationships
Our key strategic partners include certain semiconductor manufacturers and their distributors, and electronic design automation software companies, which provide information and interfacing that assist us with the successful development and distribution of our software solutions.
FPGA manufacturers. These partners work closely with us before each product release to ensure that our design software products perform optimally with their components. We rely on these manufacturers to provide us advance information and answer detailed questions about their components and design software. Partners currently include Actel Corporation, Altera Corporation, Lattice Semiconductor Corporation, QuickLogic Corporation and Xilinx, Inc. Actel, Lattice and QuickLogic also resell a version of our Synplify product. These reselling relationships provide a strong endorsement of our products, expand our sales channels and serve to introduce our products to a large number of potential customers. They generated 8% of our total revenue in 2004 and 7% of our total revenue in 2003 and 2002.
ASIC manufacturers. We also maintain close support relationships with other key semiconductor partners who have presence in the ASIC market. These include AMI Semiconductor, ARM Holdings PLC, ChipX, Faraday Technology Corporation, Fujitsu Microelectronics, IBM Microelectronics, LSI Logic, LightSpeed Semiconductor, NEC Electronics, OKI Electric Industry Co. Ltd., and Virtual Silicon Technology Inc. These ASIC and ASIC library vendors have worked with us to develop and qualify our software into their ASIC design flows. For example, in 2004, we announced a development and marketing agreement with Fujitsu Microelectronics to provide a customized physical synthesis product for their structured ASIC product family.
Electronic design automation (“EDA”) software companies. We work with EDA software partners to integrate our complementary products with theirs to create a more complete, easier to use set of design solutions for the benefit of our mutual customers. Our EDA software partners include those whose products perform functions such as design entry, simulation, system analysis, hardware prototyping and simulation acceleration hardware. We resell versions of Cadence’s Affirma simulators bundled with our products. We also have reselling agreements in place with Aldec Corporation under which they resell our Synplify and HDL Analyst products in combination with their own and we resell their simulation and design entry products, respectively.
Technology
We believe our products are easier to use and produce superior results more rapidly than alternative solutions. In addition, our core technology platform enables us to produce innovative products quickly. Selected features of our technology include:
Behavior Extracting Synthesis Technology. Our products are designed with our proprietary technology to recognize and locate common circuit building blocks within designs and maintain high-level representations of these blocks throughout the synthesis process. Other synthesis products use circuit representations that maintain detailed level representations of the design, but lose important information. By maintaining behavioral information that describes a semiconductor’s function throughout synthesis, we believe our synthesis products make better overall optimizations, which result in better circuit performance.
Physical synthesis innovations. Achieving superior performance in large FPGAs and ASICs requires solving specialized problems not encountered in smaller semiconductors. We have two patents allowed and additional applications submitted related to algorithms that solve many of these problems. These algorithms involve combining synthesis with processes that are normally applied later in the semiconductor design process. This combination is termed physical synthesis. We believe our work with structured ASIC vendors has shown that we can achieve very tight correlation between our estimated results and the actual results.
Fast, memory efficient algorithms. Long run times are a commonly encountered barrier to processing large designs. Because synthesis is performed repeatedly during the design process, fast run times are an important time-to-market determinant. All of the algorithms employed in our products were carefully selected and implemented for fast run times and efficient memory utilization. These algorithms’ run times increase linearly as design size increases, as opposed to nonlinearly with other software products.
Embedded electrical engineering knowledge. Synthesis and optimization of complex circuits are accomplished through a large collection of algorithms and heuristics. For any given circuit, the application of these algorithms requires many decisions, including which algorithms to use and in what order to apply them. Implementing a synthesis product is considerably easier if the user is required to make these types of decisions. However, this places the burden of understanding the effects of synthesis algorithms on the user and results in a product that is difficult to use. Instead, we build products with a level of automation for making these decisions by embedding a high degree of electrical engineering knowledge in the products so that optimization decisions are performed automatically.
Power distribution design and analysis. An important aspect of successful design of complex integrated circuits is the design of the power distribution network. We have proprietary technology for the design and implementation of power distribution for integrated circuits as well as technology for the accurate analysis of voltage drop caused by power usage within local sections of the chip.
Prototyping and Debug. Complex ASIC designs often cannot be adequately verified except with a prototype that operates close to the intended operating speed of the ASIC. We have developed patented technology and products that assist in the implementation of fast prototypes of ASICs, helping the designer implement the ASIC functionality on a set of FPGAs. Once the prototype is in place, understanding the operation of the circuit is often the critical path to success. We have technology and products that help the designer debug a circuit by relating the actual operation of the circuit back to the HDL input used to implement the circuit.
Research and development
We believe that strong product development capabilities are essential to our strategy of enhancing our core technology, developing additional applications and increasing the competitiveness of our product offerings. We have invested significant time and resources in creating a structured process for undertaking all product development projects. This process involves key functional groups within our company and is designed to provide a framework for defining and addressing the steps required to bring product concepts and development projects to market successfully. Our product development strategy emphasizes rapid innovation and product releases.
We have actively recruited key computer engineers and software developers with expertise and degrees in computer science, electrical engineering and other engineering disciplines. As of December 31, 2004, we had 159 employees engaged in research and development activities and related customer support services. Our research and development expenses were $23.5 million in 2004, $21.1 million in 2003 and $19.0 million in 2002.
Intellectual Property
Our software products rely on our internally developed intellectual property and other proprietary rights. We rely primarily on a combination of patent, copyright, trademark and trade secret laws, confidentiality procedures and contractual provisions to protect our intellectual property and other proprietary rights. However, we believe that these measures afford only limited protection. We have filed a number of patent applications and to date have been issued or allowed 23 patents that expire 20 years from their filing dates, the first of which expires in 2018. We license our software products primarily under shrink wrap licenses that are included as part of the product packaging. Shrink wrap licenses are not negotiated with or signed by individual customers, and purport to take effect upon the opening of the product package or use of the software license key. The legal enforceability of shrink wrap licenses is uncertain in many jurisdictions. We also generally enter into confidentiality agreements with our employees and technical consultants. Despite our efforts to protect our proprietary rights, unauthorized parties may attempt to copy aspects of our products or obtain and use information that we regard as proprietary. Policing unauthorized use of our products is difficult and we are unable to determine the extent to which piracy of our software products exists. In addition, the laws of some foreign countries do not protect our proprietary rights as fully as do the laws of the United States.
We are not aware that our products employ technologies that infringe any valid proprietary rights of third parties. We expect that software product developers will increasingly be subject to infringement claims as the number of products and competitors in our industry segment grows and the functionality of products in different industry segments overlaps. From time to time third parties have claimed that our products violate their proprietary rights but none of these claims has resulted in litigation or material expense. Any infringement claims, with or without merit, could:
•
be time-consuming to defend;
•
result in costly litigation or damage awards;
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divert management’s attention and resources;
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cause product shipment delays; or
•
require us to enter into royalty or licensing agreements.
These royalty or licensing agreements may not be available on terms acceptable to us, if at all.
Competition
We conduct business in the EDA software market that is intensely competitive and rapidly evolving. We face competition primarily from EDA software companies that provide software products and product suites to perform a variety of design and verification functions for all types of semiconductors. We have experienced and expect to continue to experience increased competition from current and potential competitors, many of which have significantly greater financial, technical, marketing and other resources and who aggressively offer enterprise-wide annualized subscription model access of product and product suite licenses. Companies offering competitive products vary in scope and breadth. Our competitors include:
•
Semiconductor manufacturers, such as Altera and Xilinx, who develop and market their own synthesis products and other tools;
•
EDA providers of general purpose synthesis and compiler software products such as Cadence, Mentor Graphics Corporation, Synopsys, Inc. and Magma Design Automation, Inc.;
•
EDA providers of software product suites that include design and verification products such as Cadence, Mentor Graphics and Synopsys; and
•
EDA providers of product suites that include verification software and hardware products such as Aptix Corporation, Cadence and Mentor Graphics.
We believe the principal factors that will draw end customers to a semiconductor design software product, including logic synthesis, physical synthesis and verification products, include:
•
high overall quality of implementation results;
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short product run time;
•
ease of learning and use;
•
depth and breadth of product features;
•
high quality customer support;
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frequency of product updates;
•
conformity with industry standards; and
•
competitive pricing.
We believe that we compete favorably on these factors. However, we expect competition in the EDA software market for FPGAs and ASICs to continue as new companies enter the market and current competitors focus on their product lines and services. Many of these potential competitors are likely to enjoy substantial competitive advantages, including greater resources that can be devoted to the development, promotion and sale of their products. In addition, these potential competitors may have more established sales channels, greater software development experience and/or greater name recognition.
Employees
As of December 31, 2004, we had 286 employees, of whom 159 were engaged in research and development and related customer support services, 84 in sales, 14 in marketing and 29 in finance, administration and operations. With the exception of our employees in France, none of our employees is represented by a labor union. We have not experienced any work stoppages and consider our relations with our employees to be good.
Executive Officers
Our officers and their ages as of December 31, 2004 are as follows:
Name
Age
Position
Gary Meyers
Chief Executive Officer, President
Kenneth S. McElvain
Chief Technology Officer, Vice President and Director
Alisa Yaffa
Chairman of the Board of Directors, Vice President of Intellectual Property and Secretary
Douglas S. Miller
Senior Vice President of Finance and Chief Financial Officer
Robert J. Erickson
Senior Vice President of Engineering
Andrew Haines
Vice President of Marketing
Gary Meyers was promoted to President and Chief Operating Officer in August 2004 and in October 2004 assumed the role of Chief Executive Officer. Mr. Meyers has served as our Vice President of Worldwide Sales from November 1999 to October 2004 and was Vice President of North American Sales from January 1999 to November 1999. Mr. Meyers joined Synplicity in January 1998 as Western Area Sales Manager until January 1999. From 1988 through 1997, Mr. Meyers served in various senior sales and marketing roles at LSI Logic, a semiconductor company, including from 1996 to 1997 as Director of Marketing of the Communications Products Division, and from 1994 to 1996 as Major Account Sales Manager. Mr. Meyers holds a Bachelor of Science degree in Electrical Engineering from the University of Maryland and a Masters of Business Administration degree from the University of California at Los Angeles.
Kenneth S. McElvain, one of our co-founders, has served as our Chief Technology Officer, Vice President and Director since inception. Mr. McElvain also served as our President from our inception to January 1996, and our Chief Executive Officer from January 1996 to July 1997. From March 1990 to January 1994, Mr. McElvain was a manager of the logic and timing optimization group and chief architect of the AutoLogic logic synthesis product at Mentor Graphics, a semiconductor design software company. To date, Mr. McElvain has been issued or allowed 14 patents. Mr. McElvain holds a Bachelor of Arts degree in Mathematics and a Bachelor of Science degree in Computer Science from Washington State University.
Alisa Yaffa, one of our co-founders, has served as our Chairman of the Board of Directors, Vice President of Intellectual Property and Secretary since March 1997, October 1998 and our inception, respectively. Ms. Yaffa also served as our Chief Executive Officer from our inception to January 1996 and our President from January 1996 to July 1997. From inception to October 1998, Ms. Yaffa served as our Chief Financial Officer. Prior to joining our company, Ms. Yaffa served in various technical and marketing roles at Cadence, Mentor Graphics, EDA Systems, Inc., a design framework software company, and VLSI Technology, Inc., a semiconductor manufacturer that was subsequently acquired by Philips Semiconductor. Ms. Yaffa holds a Bachelor of Arts degree in Applied Mathematics and Computer Science from University of California at Berkeley.
Douglas S. Miller was promoted to Senior Vice President of Finance in September 2004 and has served as our Vice President of Finance and Chief Financial Officer since October 1998. From June 1998 to September 1998, Mr. Miller was a self-employed financial consultant. From April 1997 to May 1998, Mr. Miller served as Vice President and Chief Financial Officer of 3Dlabs, Inc. a graphics semiconductor company. From October 1991 to April 1997, Mr. Miller served as a partner at Ernst & Young LLP, a professional services organization,
and from July 1985 to September 1991, Mr. Miller served as a manager at Ernst & Young LLP. Mr. Miller is a certified public accountant. He holds a Bachelor of Science degree in Accounting from Santa Clara University.
Robert J. Erickson was promoted to Senior Vice President of Engineering in September 2004 and has served as our Vice President of Engineering since April 1998. From June 1997 to April 1998, Mr. Erickson was a principal of Vermilion DA, a semiconductor design software consulting firm. From May 1984 to June 1997, Mr. Erickson served in various positions including a director of engineering at Mentor Graphics. Mr. Erickson holds Bachelor of Arts degrees in Physics and Electrical Engineering from Rice University and a Master of Science degree in Electrical Engineering from Stanford University.
Andrew Haines re-joined Synplicity as Vice president of Marketing in September 2004. Mr. Haines served as Vice President of Operations of Catalytic Inc. from January 2004 to September 2004 and Senior Vice president of Marketing of ARC International from October 2002 to October 2003. Mr. Haines originally joined us in 1996 as our Vice President of Marketing and remained in that capacity until 2002, when he departed to pursue interests in the semiconductor intellectual property industry. Before joining Synplicity in 1996, Mr. Haines was president and founder of Page Mill Marketing. Mr. Haines holds a Bachelor of Science in Physics from the University of Wisconsin.
ITEM 2.
ITEM 2. PROPERTIES
Our principal offices are located in a leased 66,000 square foot facility in Sunnyvale, California which houses all of our marketing, administration and finance employees, the majority of our research and development and related customer support service employees, and some sales employees. In addition, we lease a 7,900 square foot development and support center in Bangalore, India; a 3,500 square foot sales office in Andover, Massachusetts; a 3,400 square foot sales office in Tokyo, Japan; a 2,300 square foot sales office in Maidenhead, United Kingdom; a 1,900 square foot sales office in Beaverton, Oregon; a 1,700 square foot sales office in Austin, Texas; a 1,600 square foot development office in Montpellier, France; a 1,500 square foot sales office in Hsinchu City, Taiwan; and a 1,300 square foot sales office in Bangalore, India. We also lease sales or development offices of 1,000 square feet or less, in or near Newport Beach and San Diego, California; Woodinville, Washington; Lisle, Illinois; Durham, North Carolina; Bel Air, Maryland; Boulder, Colorado; Dornach, Germany; Aix-en-Provence France; Venray, Netherlands; Stockholm, Sweden; Netanya, Israel; Seoul, South Korea; and Shanghai, P.R.C. The leases for our Andover, Austin, Bangalore, Beaverton, Boulder, Dornach, Maidenhead, Montpellier, Netanya, Shanghai, Sunnyvale, Tokyo, Venray, and Woodinville offices are more than 12 months in duration. The rest of our office leases are not more than 12 months in duration. We expect that our current leased facilities will be sufficient for our needs during 2005. However, we may choose to expand certain existing sales and/or development offices or establish new ones during the year.
ITEM 3.
ITEM 3. LEGAL PROCEEDINGS
We are not currently involved in any material litigation.
ITEM 4.
ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS
None.
PART II
ITEM 5.
ITEM 5. MARKET FOR REGISTRANT’S COMMON EQUITY, RELATED STOCKHOLDER MATTERS AND ISSUER PURCHASES OF EQUITY SECURITIES
PRICE RANGE OF SYNPLICITY COMMON STOCK
Our common stock has been traded on the Nasdaq National Market under the symbol “SYNP” since October 12, 2000. The following table sets forth for the period indicated the high and low closing sale prices for the common stock, as reported by the Nasdaq National Market.
On December 31, 2004, the last reported sale price of our common stock on the Nasdaq National Market was $5.98 per share. As of February 10, 2005 there were 102 holders of record of our common stock.
The information required by this Item regarding equity compensation plans is incorporated by reference under the section entitled “Executive Compensation - Equity Compensation Plan Information” that is contained in our Proxy Statement for our 2005 Annual Meeting of Shareholders, to be filed by us with the SEC within 120 days of the end of our fiscal year pursuant to General Instruction G(3) of Form 10-K (“Proxy Statement”).
DIVIDEND POLICY
To date, we have paid no cash dividends on our common stock, and have no current intentions to do so.
ISSUER PURCHASES OF EQUITY SECURITIES
The following table provides information with respect to purchases we made of our common stock during 2004 pursuant to our stock repurchase program:
(A) In May 2004, our Board of Directors authorized a stock repurchase program of up to one million shares of our common stock over a 12 month period. Shares will be repurchased in the open market at times and prices we consider appropriate. The timing of purchases and the exact number of shares to be purchased will depend on market conditions.
ITEM 6:
ITEM 6: SELECTED FINANCIAL DATA
The selected consolidated financial data below should be read in conjunction with “Management’s Discussion and Analysis of Financial Condition and Results of Operations” and our consolidated financial statements and notes thereto. The selected consolidated statement of operations data for the years ended December 31, 2004, 2003 and 2002 and the selected consolidated balance sheet data as of December 31, 2004 and 2003 are derived from, and are qualified by reference to, the audited consolidated financial statements included elsewhere in this Annual Report on Form 10-K.
The selected consolidated statement of operations data for the years ended December 31, 2001 and 2000 and the selected consolidated balance sheet data as of December 31, 2002, 2001 and 2000 are derived from, and qualified by reference to, audited consolidated financial statements that are not included in this Annual Report on Form 10-K.
The historical results presented below are not necessarily indicative of future results.
ITEM 7.
ITEM 7. MANAGEMENT’S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS
Certain statements in this “Management’s Discussion and Analysis of Financial Condition and Results of Operations” are forward-looking statements. These statements relate to future events or our future financial performance and involve known and unknown risks, uncertainties and other factors that may cause our or our industry’s actual results, levels of activity, performance or achievements to be materially different from any future results, levels of activity, performance or achievements expressed or implied by the forward-looking statements. These risks and other factors include those listed under “Factors Affecting Future Operating Results” and elsewhere in this Annual Report on Form 10-K. In some cases, you can identify forward-looking statements by terminology such as “may,” “will,” “should,” “expects,” “plans,” “anticipates,” “believes,” “estimates,” “predicts,” “potential,” “continue” or the negative of these terms or other comparable terminology. Forward-looking statements include, but are not limited to: the statements under “Critical Accounting Policies and Estimates” regarding the financial statements included in this Annual Report, statements under “Revenue Recognition” regarding time-based licenses and statements under “Allowance for Doubtful Accounts” regarding additional allowances for doubtful accounts; the statements under “Years Ended December 31, 2004 and 2003-Cost of revenue” regarding cost of maintenance revenue; the statements under “Years Ended December 31, 2004 and 2003-Operating expenses” regarding future operating expenses; the statements under “Years Ended December 31, 2004 and 2003-Income Taxes” regarding federal net operating loss and tax credit carry forwards; the statements under “Liquidity and Capital Resources” concerning the sufficiency of our available resources to meet cash requirements and the factors which will determine our future cash requirements; and the statements in “Factors Affecting Future Operating Results.” These statements are only predictions. In evaluating these statements, you should specifically consider various factors, including the risks outlined under “Factors Affecting Future Operating Results.” Actual events or results may differ materially.
Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements. Moreover, neither we nor any other person assumes responsibility for the accuracy and completeness of these forward-looking statements. We are under no duty to update any of the forward-looking statements after the date of this Annual Report on Form 10-K to conform our prior statements to actual results. Moreover, neither we nor any other person assumes responsibility for the accuracy and completeness of these statements. These forward-looking statements are made in reliance upon the safe harbor provision of The Private Securities Litigation Reform Act of 1995.
You should read the following discussion and analysis in conjunction with our financial statements and the related notes thereto included in this Annual Report on Form 10-K.
Overview
We operate in one segment, the development and licensing of software products that are used in the design and verification of semiconductors. We market and sell our products throughout North America, principally the United States, as well as in Europe, Japan and other parts of Asia. Our revenue from sales outside North America represented 42%, 41% and 30% of our total revenue in 2004, 2003 and 2002, respectively.
Our products include:
•
our Synplify product, an FPGA logic synthesis product;
•
our Synplify Pro product, an advanced FPGA logic synthesis product;
•
our HDL Analyst product, a complementary product to Synplify which provides graphical representation and design analysis;
•
our Certify product, a product for verification of ASICs by synthesizing multi-FPGA prototypes;
•
our Amplify Physical Optimizer product, a physical synthesis product for FPGAs;
•
our Synplify ASIC product, a timing-driven ASIC synthesis product optimized to improve productivity;
•
our Fortify family of power grid design solutions;
•
our Identify product, a product that assists in debugging hardware directly in the RTL source code;
•
our Amplify RapidChip Physical Optimizer product, a customized physical synthesis product for LSI Logic’s platform ASIC;
•
our Amplify ISSP Physical Optimizer product, a customized physical synthesis product for NEC Electronics’ structured ASIC; and
•
our Synplify DSP product, a solution for implementing DSP designs in FPGAs
The majority of our sales are perpetual licenses to use our software products and related maintenance services, and therefore our revenue consists of license and maintenance revenue. Maintenance services include unspecified product updates when and if available, electronic, internet-based technical support and telephone support. Historically, we have generated the majority of our total revenue from licenses. However, as a result of our growing installed customer base, maintenance revenue has increased as a percent of total revenue. We also sell time-based licenses to use our software products, which have represented a growing proportion of total revenue. Time-based licenses include maintenance services for the duration of their respective terms. Additionally, from time to time we provide custom software development services to our customers, revenue from which is recorded in license revenue.
2004 Highlights
Worldwide economic conditions improved in 2004. We experienced strengthening in our FPGA and ASIC synthesis businesses, including the emerging structured ASIC segment of our ASIC synthesis business. Maintenance revenue grew as our customer base increased and maintenance renewal rates increased. While we maintained our cost control measures, we also incurred significant expenses for higher compensation due to additional employees and removal of salary reductions, as well as increased commission expense from the sales force exceeding quota targets. Additionally, we incurred higher expenses for compliance with corporate governance regulations. Financial highlights for the year are as follows:
•
Total revenue for 2004 was $57.0 million, a 15% increase from $49.6 million for 2003
•
License revenue for 2004 was $31.7 million, a 14% increase from $27.7 million for 2003
•
Time-based license revenue as a percentage of our license revenue for the year 2004 was 39%, an increase from 29% for 2003
•
Maintenance revenue for 2004 was $25.2 million, a 16% increase from $21.8 million for 2003
•
Net income for 2004 was $2.2 million, up from a $377,000 net loss for 2003
•
Diluted net income per share for 2004 was $0.08 compared to a $0.01 loss for 2003
•
Working capital for 2004 grew to $37.5 million from $34.0 million for 2003
Critical Accounting Policies and Estimates
Our discussion and analysis of our financial condition and results of operations are based upon our audited consolidated financial statements, which have been prepared in accordance with U.S. generally accepted accounting principles. The preparation of these financial statements requires us to make estimates and judgments that affect the reported amounts of assets, liabilities, revenues, expenses and related disclosure of contingent
assets and liabilities. We base our estimates on historical experience and on various other assumptions that are believed to be reasonable under the circumstances, and we evaluate these estimates on an on-going basis. Actual results may differ from these estimates under different assumptions or conditions.
Revenue Recognition
For each sale of a perpetual license, the first year of maintenance is generally sold with the license. We defer the recognition of license and maintenance revenue until:
•
a purchase order is received from the customer,
•
delivery of the product and perpetual license key has occurred,
•
the fee is fixed or determinable,
•
collection of the fee is probable, and
•
we have no remaining obligations other than maintenance
Once all of the above conditions have been met, license revenue is recognized based upon the residual method after all elements other than maintenance have been delivered in accordance with AICPA Statement of Position 98-9, Modification of SOP No. 97-2 with Respect to Certain Transactions. Maintenance revenue is recognized on a straight-line basis over the maintenance period since customers under maintenance agreements receive unspecified product updates, electronic, internet-based technical support and telephone support throughout their maintenance period, which is typically one year. The majority of our customers also purchase maintenance renewals annually on a stand alone basis at either 15 or 20% of the perpetual license list price, depending on the product, which establishes vendor specific objective evidence (“VSOE”) of the fair value of maintenance.
We also offer two-year and three-year term licenses for certain products under which the customer purchases the first year of maintenance with the license and can renew maintenance in each of the following one or two years. Revenue from term licenses is recognized in the same manner as revenue from perpetual licenses as VSOE of the fair value of maintenance is established by the maintenance renewal pricing at either 15 or 20% of the perpetual license list price, depending on the product.
We assess whether the fee is fixed or determinable for sales with non-standard payment terms by evaluating our history of collections from these customers. In no case will we deem a fee to be fixed or determinable where the fee is due after the expiration of the license or more than 12 months after delivery. We make judgments as to whether collection of the fee is probable based on the analysis provided by our credit review procedures. Revenue on arrangements to end-user customers that have met all of the revenue recognition criteria except probability of collection is recognized as collection becomes reasonably assured, which is generally as payments are received.
Revenue on sales to distributors is considered to have met the probability of collection criterion when the distributor has resold the product to an end user and either we have received payment for the product or we assess that we have a substantial and sustained history of collections from the distributor.
We also sell time-based licenses to use our software products for specified periods of time. Time-based licenses include maintenance services for the duration of their respective terms. Revenue from time-based licenses is allocated between license and maintenance revenue in similar proportion to perpetual license transactions, and recognized on a straight-line basis over the period of the license as we do not have VSOE of the fair value of maintenance for time-based licenses since it is not priced or offered separately. In addition, we have provided a version of one of our products to certain FPGA manufacturers for distribution to their customers. As part of this arrangement we have certain maintenance and support obligations to the FPGA manufacturers. Revenue on this arrangement is also allocated to license and maintenance revenue and recognized on a straight-line basis over the period of each arrangement, as we do not have VSOE of fair value of maintenance for these arrangements since it is not priced or offered separately.
Furthermore, we may sell time-based licenses combined in an order with perpetual or term licenses. For these transactions, we recognize revenue from the entire transaction straight-line over the term of the longest time-based license in the transaction, as generally we do not have VSOE on time-based licenses.
We have entered into agreements with semiconductor manufacturers LSI Logic, NEC Electronics and Fujitsu Microelectronics to customize our ASIC synthesis or physical synthesis tools for certain of their products. When time-based licenses are being purchased as part of the agreement, once the contract has been signed, delivery of the customized product has occurred, collection of the fee is probable and we have no remaining obligations other than maintenance, we recognize revenue from both the development and license fees on a straight-line basis over the period of the licenses since we do not have VSOE of fair value of the time-based licenses. When licenses are not being purchased as part of the agreement, once the contract has been signed, we recognize revenue from the development fees on a percentage of completion basis. Revenue recognized from these arrangements represents less than 10% of total revenue and is recorded in license revenue.
Goodwill and Intangible Assets
In accordance with Statement of Financial Accounting Standards No. 142, Goodwill and Other Intangible Assets, goodwill is not amortized but is tested for impairment using a fair value approach. Goodwill is tested for impairment annually during the fourth quarter as well as whenever indicators of impairment exist. In accordance with the provisions of Statement of Financial Accounting Standards No. 144, Accounting for the Impairment or Disposal of Long-Lived Assets, long-lived assets, including intangible assets and property and equipment, are reviewed for impairment whenever events or changes in circumstances indicate that their carrying amount may not be recoverable. Recoverability of a long lived asset other than goodwill is measured by comparison of its carrying amount to the expected future undiscounted cash flows that the asset is expected to generate. An impairment charge is recorded if the carrying amount of the asset exceeds the sum of the expected undiscounted cash flows. Any impairment to be recognized is measured by the amount by which the carrying amount of the asset exceeds its fair value. Fair value is determined based on discounted cash flows or appraised values, depending upon the nature of the assets. Significant management judgment is required in forecasting future operating results and cash flows and, should different conditions prevail or judgments be made, material write-downs of net intangible assets and/or goodwill could occur. Our intangible assets are being amortized using the straight-line method over the estimated useful life of five years.
Allowance for Doubtful Accounts
We maintain and update quarterly an allowance for doubtful accounts for estimated losses resulting from the failure of our customers to make required payments. The balance in the allowance account is comprised of a specific reserve for any particular receivable when collectibility is not probable and a provision for non-specific accounts based on a specified range of percentages derived from historical experience applied to the outstanding balance in each aged group. If after pursuing collection efforts on a specifically reserved receivable, payment is not expected, the receivable is deemed uncollectible and is written off. Such losses have not been material in any year; however, if the financial condition of our customers deteriorates, resulting in an impairment of their ability to make payments, additional allowances may be required. The table in Schedule II, Valuation and Qualifying Accounts and Reserves of this annual report provides a roll forward of the changes in the allowance for doubtful accounts.
Valuation Allowance for Deferred Tax Assets
We evaluate the need for a valuation allowance for deferred tax assets in accordance with the requirements of Statement of Financial Accounting Standards No. 109 (“SFAS 109”) and such evaluations are based on available evidence of whether it is more likely than not that some portion or all of the deferred tax assets will not be realized. Our evaluation for the year ending December 31, 2004 was based on the cumulative pre-tax losses we have sustained in the three years ended December 31, 2004.
Results of Operations
The following table sets forth the results of our operations expressed as a percent of total revenue. Our historical operating results are not necessarily indicative of the results for any future period.
Years Ended December 31, 2004 and
Total revenue
Our total revenue increased by 15% to $57.0 million for 2004 from $49.6 million for 2003.
License revenue. License revenue increased by 14% to $31.7 million for 2004 from $27.7 million for 2003. This increase was primarily due to an increase in sales of our products, principally our FPGA products, as well as license revenue recognized from our development agreements for the structured ASIC market.
Maintenance revenue. Our maintenance revenue increased by 16% to $25.2 million for 2004, from $21.8 million for 2003. This increase was attributable to higher maintenance renewal rates compared to 2003, higher product sales and higher overall maintenance prices. In addition, we continued to have customers return to active maintenance and pay back-maintenance charges, which are recognized when the maintenance is renewed.
Cost of revenue
Cost of license revenue. Cost of license revenue includes product packaging, software documentation, other costs associated with shipping, royalties due from us to third parties and engineering costs directly associated with our development agreements with NEC Electronics and Fujitsu Microelectronics. Our cost of
license revenue increased to $553,000 for 2004 from $488,000 for 2003. This increase was due to the engineering costs associated with the NEC Electronics and Fujitsu Microelectronics agreements. As a percent of license revenue, the cost of license revenue remained at 2% for 2004 and 2003.
Cost of maintenance revenue. Cost of maintenance revenue consists primarily of personnel and other expenses related to providing maintenance support to our customers. Cost of maintenance revenue increased to $2.5 million in 2004 from $2.1 million for 2003. This increase was primarily due to higher compensation expense from additional employees, as well as the removal of the remaining employee salary reductions. As a percent of maintenance revenue, the cost of maintenance revenue remained at 10% for 2004 and 2003. As many of our products are becoming more mature, customer support now requires a lower percentage of total engineering effort and we expect that cost of maintenance revenue in 2005 will be lower than 2004.
Amortization of intangible assets. Amortization of intangible assets of $890,000 and $891,000 during 2004 and 2003, respectively, reflects the amortization of intangible assets acquired as part of our purchases of products and technology from IOTA and Bridges2Silicon over a five-year useful life.
Operating expenses
Research and development. Our research and development expenses increased 12% to $23.5 million for 2004 from $21.1 million for 2003. This increase was primarily due to additional employees and associated hiring costs and removal of the remaining employee salary reductions. As a percent of total revenue, research and development expenses decreased to 41% for 2004 compared with 42% for 2003, due to higher total revenue. We expect that research and development expenses in 2005 will be higher than 2004 as we hire additional employees, primarily in Bangalore, India, as well as implement worldwide salary increases.
Sales and marketing. Our sales and marketing expenses increased 6% to $21.9 million for 2004 from $20.7 million for 2003. This increase was primarily due to the impact of accelerated commission rates and bonuses for sales teams that exceeded target quotas for the year and removal of the remaining employee salary reductions. As a percent of total revenue, sales and marketing expenses decreased to 39% in 2004 from 42% for 2003 primarily due to higher total revenue. We expect that sales and marketing expenses in 2005 will be higher than 2004 due to worldwide salary increases, the hiring of additional sales personnel, primarily in the international locations, as well as increased marketing activity.
General and administrative. Our general and administrative expenses increased 18% to $5.6 million for 2004 from $4.7 million for 2003. This increase was mainly due to the higher costs associated with corporate governance compliance and removal of remaining employee salary reductions. As a percent of total revenue, general and administrative expenses remained at 10% for 2004 and 2003. We expect that general and administrative expenses in 2005 will be higher than 2004 due to worldwide salary increases and continued compliance with corporate governance requirements.
Stock-based compensation. Stock-based compensation expense was $186,000 for 2004 and $443,000 for 2003. Stock-based compensation expense for 2004 related to the following: cost of maintenance revenue of $3,000, research and development expenses of $53,000, sales and marketing expenses of $51,000 and general and administrative expenses of $79,000. Stock-based compensation expense for 2003 related to the following: cost of maintenance revenue of $9,000, research and development expenses of $145,000, sales and marketing expenses of $129,000 and general and administrative expenses of $160,000. The remaining deferred stock-based compensation at December 31, 2004 is expected to be amortized as follows: $69,000 in 2005 and $19,000 in 2006. The amount of stock-based compensation expense to be recorded in future periods could decrease if options for which accrued but unearned compensation has been recorded are forfeited .
Other income, net
Other income, net increased 4% to $604,000 for 2004 from $581,000 for 2003 as a result of higher interest rates earned on investments.
Income Taxes
We recorded an income tax provision of $232,000 for 2004 which primarily represented foreign income taxes. Our income tax provision in 2004 included reversals of certain tax accruals established in prior years resulting from the final filing of our 2003 worldwide tax returns and the completion of several international transfer pricing studies that supported filed positions. Our provision for income taxes in 2004 differed from the tax provision that would have been derived from applying the federal statutory rate to the income before taxes primarily due to foreign income taxes and an increase in the valuation allowance for deferred tax assets. We recorded an income tax provision of $35,000 in 2003. Our provision for income taxes in 2003 differed from the tax provision that would have been derived from applying the federal statutory rate to the loss before taxes primarily due to foreign and state income taxes.
As of December 31, 2004, we had deferred tax assets of approximately $10.7 million. Management has evaluated the need for a valuation allowance for deferred tax assets in accordance with the requirements of SFAS 109. Based on the cumulative pre-tax losses we have sustained in the three years ended December 31, 2004, a valuation allowance in an amount equal to our net deferred tax assets of December 31, 2004 was recorded. The valuation allowance increased by approximately $1.2 million in 2004 and decreased by approximately $7,000 in 2003.
As of December 31, 2004, we had federal net operating loss carryforwards of approximately $7.6 million. We also had federal and state tax credit carryforwards of approximately $3.8 million and $4.1 million, respectively. The federal net operating loss and tax credit carryforwards will expire beginning in 2012, if not utilized. The state tax credits carry forward indefinitely.
Utilization of the net operating loss carryforwards and tax credit carryforwards may be subject to a substantial annual limitation due to the ownership change limitations provided by the Internal Revenue Code of 1986, as amended, and similar state provisions. The annual limitation may result in the expiration of net operating loss carryforwards and tax credit carryforwards before utilization.
Years Ended December 31, 2003 and 2002
Total revenue
Our total revenue increased by 9% to $49.6 million for 2003 from $45.6 million for 2002.
License revenue. License revenue increased by 7% to $27.7 million for 2003 from $25.8 million for 2002. This increase was due to higher international license revenue as well as higher revenue from our ASIC products, including the recognition of revenue received from our agreements with NEC Electronics and LSI Logic to customize our ASIC synthesis products. This increase was partially offset by lower license revenue in the United States due to the effect of the economic downturn on sales of our FPGA products.
Maintenance revenue. Our maintenance revenue increased by 10% to $21.8 million for 2003 from $19.8 million for 2002. This increase was attributable to maintenance being recognized in 2003 from license sales that occurred in 2002 and 2003 and renewals of maintenance on a larger installed license base.
Cost of revenue
Cost of license revenue. Cost of license revenue includes product packaging, software documentation, other costs associated with shipping, royalties due from us to third parties and engineering costs directly associated with our development agreement with NEC for which revenue is being recognized on a percentage of completion basis. Our cost of license revenue increased to $488,000 for 2003 from $227,000 for 2002. As a percent of license revenue, the cost of license revenue increased to 2% in 2003 from 1% in 2002.
Cost of maintenance revenue. Cost of maintenance revenue consists primarily of personnel and other expenses related to providing maintenance support to our customers. Cost of maintenance revenue increased to $2.1 million in 2003 from $1.9 million for 2002. As a percent of maintenance revenue, the cost of maintenance revenue increased to 10% for 2003 from 9% for 2002. These increases were primarily due to higher compensation expense from additional employees as well as the partial removal of salary reductions that were implemented in the first quarter of 2002.
Amortization of intangible assets. Amortization of intangible assets of $891,000 and $322,000 during 2003 and 2002, respectively, reflects the amortization of intangible assets acquired as part of our purchases of products and technology from IOTA and Bridges2Silicon over a five-year useful life.
Operating expenses
Research and development. Our research and development expenses increased 11% to $21.1 million for 2003 from $19.0 million for 2002. These increases were primarily due to additional employees, associated hiring costs, the partial removal of salary reductions implemented in the first quarter of 2002 and additional patent activity. As a percent of total revenue, research and development expenses remained at 42% for 2003 and 2002.
Sales and marketing. Our sales and marketing expenses increased 3% to $20.7 million for 2003 from $20.1 million for 2002. This increase was primarily due to higher commission expense, the partial removal of salary reductions and foreign exchange rate losses. As a percent of total revenue, sales and marketing expenses decreased to 42% in 2003 from 44% for 2002 primarily due to higher total revenue.
General and administrative. Our general and administrative expenses increased 4% to $4.7 million for 2003 from $4.6 million for 2002. These increases were mainly due to the partial removal of salary reductions as well as compensation to the independent members of our Board of Directors, partially offset by the recovery of certain bad debt allowances. As a percent of total revenue, general and administrative expenses remained at 10% for 2003 and 2002.
Stock-based compensation. Stock-based compensation expense was $443,000 for 2003 and $542,000 for 2002. Stock-based compensation expense for 2003 related to the following: cost of maintenance revenue of $9,000, research and development expenses of $145,000, sales and marketing expenses of $129,000 and general and administrative expenses of $160,000. Stock-based compensation expense for 2002 related to the following: cost of maintenance revenue of $14,000, research and development expenses of $218,000, sales and marketing expenses of $106,000 and general and administrative expenses of $204,000.
Acquired in-process research and development. We had no acquired in-process research and development expense in 2003. We incurred acquired in-process research and development expense of $2.8 million during 2002 in connection with the write-off of research and development assets acquired in connection with our product and technology acquisitions during 2002.
Other income, net
Other income, net decreased 35% to $581,000 for 2003 from $900,000 for 2002 as a result of the decrease in interest rates earned on investments.
Income Taxes
We recorded an income tax provision of $35,000 for 2003 which primarily represented foreign income taxes. Our provision for income taxes in 2003 differed from the tax provision that would have been derived from applying the federal statutory rate to the loss before taxes primarily due to foreign income taxes and an decrease
in the valuation allowance for deferred tax assets. We recorded an income tax provision of $358,000 in 2002. Our provision for income taxes in 2002 differed from the tax provision that would have been derived from applying the federal statutory rate to the income before taxes primarily due to foreign and state income taxes.
As of December 31, 2003, we had deferred tax assets of approximately $9.5 million. Based on the cumulative pre-tax losses we had sustained in the three years ended December 31, 2003, a valuation allowance in an amount equal to our net deferred tax assets as of December 31, 2003 was recorded. The valuation allowance decreased by approximately $7,000 in 2003 and increased by approximately $4.3 million in 2002. As of December 31, 2003, we had federal net operating loss carryforwards of approximately $10.7 million. We also had federal and state tax credit carryforwards of approximately $3.0 million and $2.7 million, respectively.
Liquidity and Capital Resources
As of December 31, 2004, we had cash and cash equivalents of $9.2 million, short-term investments of $39.4 million, an accumulated deficit of $14.0 million and working capital of $37.5 million. Net cash provided by operating activities was $4.9 million, $5.9 million and $2.9 million for 2004, 2003 and 2002, respectively. The decrease in net cash provided by operating activities in 2004 from 2003 was primarily due to the accounts receivable from significant sales at the end of December and the amortization of the existing deferred stock compensation, offset by net income in 2004 versus a net loss in 2003. The decrease in net cash provided by operating activities in 2003 from 2002 was primarily due to a lower net loss in 2003 and a higher increase in deferred revenue in 2003.
Net cash used in investing activities was $415,000, $10.3 million and $10.7 million for 2004, 2003 and 2002, respectively. Net cash used in investing activities during 2004 was mainly for purchases of computers offset by investment maturities net of investment purchases. Net cash used in investing activities during 2003 was mainly for investments as well as purchases of computers, software and furniture. Net cash used in investing activities during 2002 was mainly for acquisitions of products and technology as well as purchases of computers, software and furniture. We expect to use approximately $2.2 million of cash to purchase property and equipment during 2005.
Net cash provided by financing activities was $506,000, $298,000, and $19,000 for 2004, 2003 and 2002, respectively. In 2004, 2003 and 2002, net cash provided by financing activities was from the sale of common stock as employees exercised stock options and purchased shares through our employee stock purchase plan, offset by repurchases of our stock.
Our future liquidity and capital requirements will depend on numerous factors, including:
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the amount, type and timing of product license sales;
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the extent to which our existing and new products gain market acceptance;
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the extent to which customers continue to renew annual maintenance;
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the timing of customer payments on outstanding receivables;
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the cost and timing of product development efforts and the success of these efforts;
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the cost and timing of sales and marketing activities;
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any acquisitions of products or technologies;
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any stock repurchases if a stock repurchase program is authorized; and
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the availability of financing.
We believe that our cash and short-term investments balance of $48.6 million as of December 31, 2004 will be sufficient to meet our operating and capital requirements through at least the next 12 months. However, it is possible that we may require additional financing within this period. We intend to continue to invest in the
development of new products and enhancements to our existing products. In addition, even if we have sufficient funds to meet our anticipated cash needs in the next 12 months, we may need or choose to raise additional funds beyond this time. We may be required to raise those funds through public or private financings, strategic relationships or other arrangements. We cannot assure that such funding, if needed, will be available on terms attractive to us, or at all. Furthermore, any additional equity financing may be dilutive to shareholders, and debt financing, if available, may involve restrictive covenants. If we fail to raise capital when needed, our failure could have a negative impact on our profitability and our ability to pursue our business strategy.
Contractual Obligations
The following summarizes our contractual obligations as of December 31, 2004, and the effect such obligations are expected to have on our liquidity and cash flow in future periods (in thousands):
(1) Purchase obligations exclude agreements that are cancelable without penalty.
Off-Balance Sheet Arrangements
We do not have any off-balance sheet arrangements that have, or are reasonably likely to have, a current or future effect on our financial condition, changes in financial condition, revenues or expenses, results of operations, liquidity, capital expenditures or capital resources that are material to investors.
Recent Accounting Pronouncement
See Note 1 of the Consolidated Financial Statements for a full description of the recent accounting pronouncement including the expected date of adoption and effect on results of operations and financial condition.
Factors Affecting Future Operating Results
Our sales and operating results have in the past been, and may in the future be, negatively impacted by deteriorating economic conditions in the United States and other major countries in which we operate
Although revenue increased in our United States operations in 2004, we have in the past experienced negative effects from economic downturns in the United States and other countries. In particular, the slowing of the EDA industry in periods of 2004 and over the last few years has negatively impacted our business. As recently as the third quarter of 2004, we have seen customers tightly control spending and reduce or delay purchase orders. Additionally, in an effort to reduce spending, some customers have been seeking time-based agreements which cause us to recognize revenue on a straight-line basis over the term of the license, thus reducing near-term revenue. Economic downturns and industry slowdowns could reemerge, and may extend to other geographic regions. A worsening of economic conditions in the United States, or extension of such conditions to other geographic regions or industries would adversely affect our business.
Changes to our international sales personnel and channels have affected and may in the future negatively affect sales
For the majority of our international revenue, we depend on a relatively small number of sales professionals in each country in which we operate. As a result, turnover of even a small number of employees in a specific
country may have a significant impact on sales in that region and our Company as a whole. Specifically, we experienced turnover in Asian countries in 2004 that had an adverse affect on our bookings and revenues. Additionally, any modifications or terminations of distributor relationships may have a negative impact on sales.
We have a history of losses and may experience losses in the future, which could result in the market price of our common stock declining
Although we had net income of $2.2 million in 2004, we had a net loss of $377,000 in 2003 and have had significant net losses in the past, including a net loss of $3.3 million in 2002. We expect to continue to incur significant levels of operating expenses. If revenue does not increase or declines, we may not be able to control our costs in order to achieve profitability. If we are not profitable, the market price of our common stock may decline, perhaps substantially. Our expenses may increase in the next 12 months as we:
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hire additional employees;
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increase compensation for existing employees;
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increase marketing efforts; and
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maintain compliance with future corporate governance regulations
Any failure to increase our new product bookings and revenue as we implement our product and distribution strategies would also harm our ability to achieve or maintain profitability and could negatively impact the market price of our common stock.
The structured ASIC market is new and our future growth and profitability are dependent on its development
A new breed of ASIC devices called structured ASICs has emerged. In 2003 we introduced the first custom architecture-specific synthesis tool for NEC Electronics’ new structured ASIC device as well as our first physical synthesis product for LSI Logic’s new platform ASIC device. In 2004, we customized our physical synthesis product for NEC Electronics’ structured ASIC device, as well as entered into a new development project with NEC Electronics where we will help develop a new capability for our structured ASIC product. In addition, we are currently working on a customized physical synthesis product for Fujitsu Microelectronics’ structured ASIC device. We are investing significant resources in customizing our products for this new market. Failure of the structured ASIC market to develop, or our failure to penetrate that market, would have a material adverse affect on our revenue and operating results.
We have relied and expect to continue to rely on sales of our Synplify, Synplify Pro and HDL Analyst products for a substantial portion of our license revenue, and a decline in sales of these products could cause our license revenue to decline
Historically, we have derived a significant majority of our revenue from sales of our Synplify, Synplify Pro and HDL Analyst products. License revenue for our Synplify, Synplify Pro and HDL Analyst products accounted for 68%, 73% and 81% of our total license revenue in 2004, 2003 and 2002, respectively. We expect that revenue from these products will continue to account for a majority of our license revenue for at least the next 12 months. License revenue of our Synplify, Synplify Pro and HDL Analyst products in dollars decreased each year from 2002 through 2004 and may continue to decrease. Any factors which continue to adversely affect the pricing of, or demand for, our Synplify, Synplify Pro and HDL Analyst products could cause our license revenue to decline and our business to suffer. Factors that may affect sales of our Synplify, Synplify Pro and HDL Analyst products, some of which are beyond our control, include the following:
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overall market conditions, including a worsening economic downturn in both domestic and foreign markets;
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the performance, quality and total cost of our software products relative to other logic synthesis products for FPGAs, including those offered at little or no cost by FPGA manufacturers;
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the quality and performance of our sales teams in individual geographic locations;
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the growth, changing technological requirements and degree of competition in the programmable semiconductor market, particularly with respect to FPGAs; and
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the maintenance and enhancement of our existing relationships with leading manufacturers of FPGAs, which may provide us advance information or detailed data about those vendors’ FPGAs and software.
Our near-term revenue could decline as a result of increases in sales of time-based licenses
We have seen an increase in the number and dollar amount of time-based license agreements. Time-based license revenue accounted for approximately 39% and 29% of our total license revenue in 2004 and 2003, respectively. This trend may continue since customers may prefer time-based licenses over perpetual licenses for our newer, higher-priced products and customers who previously purchased perpetual licenses may choose to convert to time-based licenses. Time-based license agreements generally have terms from one to three years and we recognize revenue from them on a straight-line basis over the term of the licenses. Increases in time-based licenses could affect our near-term revenue growth due to the delayed timing of revenue recognition for such licenses. If our average selling price of time-based licenses decreases, or if customers do not renew such licenses, our revenue could also decline. Any decline in our revenue, or lack of significant growth in our revenue, could result in a decrease in our stock price because our revenue may fail to meet the expectations of our stockholders and the investment community.
Our revenue could decline substantially if our existing customers do not continue to purchase additional licenses or maintenance from us, or if existing agreements with FPGA manufacturers are canceled
We rely on sales of additional licenses to our existing customers, as well as annual maintenance renewals for our products. Additional license sales to our existing customers represented 78% of our license sales in 2004 and 2003, and 73% of our license sales in 2002. If we fail to sell additional licenses for our products to our existing customers, we would experience a material decline in revenue. Even if we are successful in selling our products to new customers, the level of our revenue could be harmed if our existing customers do not continue to purchase a substantial number of additional licenses from us or fail to renew their maintenance. Our success in generating revenue from existing customers is dependent on maintaining our relationships with those customers as well as increased need for and usage of our products by those customers. Additionally, we experienced lower rates of maintenance renewal during 2003 and 2002 compared to prior years including, but not limited to, the effects of customers’ inability to renew maintenance on some or all of their licenses due to business conditions or budget restrictions. We have seen an improvement in our maintenance renewal rates for 2004 compared to 2003. However, if we were to again experience declines in maintenance renewal rates, our maintenance revenue could stop growing or decrease.
We have agreements with certain FPGA manufacturers to resell a version of our Synplify product. Some of these agreements allow for cancellation with a notice period. Revenue recognized from these agreements generated 8% of our revenue in 2004 and 7% of our revenue in 2003 and 2002. If these agreements were canceled or not renewed, our revenue could decline.
We may not succeed in developing, marketing and selling new or enhanced commercially acceptable logic synthesis, physical synthesis and verification products, and our operating results may decline as a result
We develop logic synthesis, physical synthesis and verification products that leverage our core capabilities. We also develop new features for our existing products. In addition, we have entered into agreements with semiconductor manufacturers to develop customized tools for certain of their structured ASIC products. Customizing products and developing new features for existing products that meet the needs of electronic product
designers require significant investments in research and development. If we fail to introduce customized products or enhanced versions of existing products that are commercially acceptable in a timely and cost-effective manner, our business could be negatively affected. Growing competition, technological changes and other market factors that negatively affect the demand for FPGAs and ASICs could also adversely affect our revenue. Our future growth and profitability will depend in large part on our ability to gain market acceptance of our products outside of our Synplify, Synplify Pro and HDL Analyst products, especially our ASIC products including structured ASICs, as well as recently introduced products, such as our Synplify DSP product. We cannot be certain that our newer products, our entry into the ASIC logic synthesis product market or other new markets, or our acquired products, will be successful. If customers do not widely adopt such products, our operating results could decline.
Our quarterly operating results and stock price may fluctuate because our ability to accurately forecast our quarterly sales is limited, our costs are relatively fixed in the short term and we expect our business to be affected by seasonality
Our ability to accurately forecast quarterly sales is limited, which makes it difficult to predict the quarterly revenue that we will recognize. In addition, the time required to initiate and complete a sale for our FPGA products is relatively short, and our ability to foresee and react to changes in customer demand for our products may be limited and therefore inaccurate. Most of our costs are for personnel and facilities, which are relatively fixed in the short term. If we have a shortfall in revenue in relation to our expectations, we may be unable to reduce our expenses quickly to avoid lower quarterly operating results. Consequently, our quarterly operating results could fluctuate, and the fluctuations could adversely affect the market price of our common stock. In addition, in the past we have experienced fluctuations in the sale of licenses for our products due to seasonality. For example, sales may decline during the summer months, particularly in European markets, and we have experienced and anticipate we will continue to experience relatively lower product bookings in our first quarter due to patterns in the capital budgeting and purchasing cycles of our current and prospective customers and the economic incentives for our sales force. These factors may lead to fluctuations in our quarterly operating results.
If we experience an increase in the length of our sales cycle, our quarterly operating results could become more unpredictable and our stock price may decline as a result
We experience sales cycles, or the time between an initial customer contact and completion of a sale, of generally two weeks to several months for our FPGA products, depending on the product. When the recent economic downturn began, we experienced an increase in the length of our sales cycle which has since stabilized. If we experience such an increase in the length of our sales cycle again, our quarterly operating results could suffer and our stock price could decline as a result. The sales cycles for certain of our ASIC products, including Certify and Synplify ASIC are substantially longer than those of our FPGA products, which could result in additional unpredictability of our quarterly revenue, especially if interest in our ASIC products increase. In addition, the timing of product releases from competitors as well as releases of our own products can cause sales cycles to increase as customers evaluate the new products.
We depend on our marketing, product development and sales relationships with leading FPGA manufacturers, and if these relationships suffer, we may have difficulty introducing and selling our FPGA synthesis products and our revenue could decline
We believe that our success in maintaining acceptance in the FPGA market depends in part on our ability to maintain or further develop our strategic marketing, product development and sales relationships with leading FPGA manufacturers, including Altera and Xilinx. We believe our relationships with leading FPGA manufacturers are important in validating our technology, facilitating broad market acceptance of our FPGA synthesis products and enhancing our sales, marketing and distribution capabilities. For example, we attempt to coordinate our product offerings with future releases of Altera’s and Xilinx’s FPGA components and software. If we are unable to maintain or enhance our existing relationships with Altera and Xilinx and develop a similar
relationship with other major FPGA vendors, we may have difficulty selling our FPGA synthesis products or we may not be able to introduce products on a timely basis that capitalize on new FPGA component characteristics or software feature enhancements.
We have been experiencing and may continue to experience increased competition as a result of FPGA manufacturers competing in the design software market or investing in emerging software companies
FPGA manufacturers currently compete in the FPGA design software market by licensing their own synthesis products at little or no cost and/or by distributing our competitors’ products. For example, both Altera and Xilinx sell synthesis products that are competitive with our Synplify and Synplify Pro products and adversely impact the price or market for our FPGA synthesis products or harm our business and financial prospects. FPGA manufacturers may also choose to assist, through financial, equity investment or other support, emerging EDA software companies whose products could compete with or outperform ours. An increase in the number of our competitors or the quality and availability of competing products could reduce the value of our products in the market place and adversely affect our business.
We rely on our marketing, sales and product and library support relationships with leading ASIC manufacturers, and if we fail to maintain or expand such relationships, we may have difficulty selling our ASIC products and our revenue could be negatively impacted
We believe that our success in penetrating the ASIC market depends in part on our ability to develop strategic marketing, sales and product and library support relationships with leading ASIC manufacturers. We believe relationships with leading ASIC manufacturers are important in validating our technology, facilitating market acceptance of our ASIC products and enhancing our sales, marketing and distribution capabilities. Relationships we have established to date include ARM Holdings PLC (which recently acquired Artisan Components), Fujitsu Microelectronics, IBM Microelectronics, LSI Logic, NEC Electronics, and Virtual Silicon Technology Inc. These ASIC and ASIC library vendors have worked with us to develop and qualify our software into all or a portion of their ASIC design flows. If we are unable to sustain these relationships or develop relationships with other key ASIC manufacturers or do not do so in a timely manner, we may have difficulty selling our ASIC products. In addition, we may not be able to enhance our products in a timely manner to capitalize on new ASIC component characteristics or software feature enhancements, which could negatively impact our revenue growth.
As we enter into development agreements with semiconductor manufacturers for our structured ASIC products, our revenue could become more unpredictable
We have entered, and expect to continue to enter, into development agreements with semiconductor manufacturers to customize our ASIC synthesis or physical synthesis tools for certain of their products. The timing of revenue recognition on these agreements may be affected by the following factors which involve uncertainty:
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our development schedule;
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our product’s performance;
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delivery of our product;
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customer acceptance of our product, which may not occur until some time after we first deliver the product; and
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timing of payments which are associated with product acceptance.
Difficulties in predicting revenue from these arrangements may cause revenue to vary from our forecasts, and as a result, may cause our operating results to decline. In addition, failure to enter into new development arrangements that replace revenue recognized from past development arrangements could cause total revenues to decline.
Our officers and persons affiliated with our directors hold a substantial portion of our stock and could reject mergers or other business combinations that a shareholder may believe to be desirable
As of December 31, 2004, our directors, officers and individuals or entities affiliated with our directors owned 50% of our outstanding common stock as a group. Acting together, these shareholders would be able to significantly influence all matters that our shareholders vote upon, including the election of directors or the rejection of a merger or other business combination that other shareholders may believe to be desirable.
Our common stock may be subject to substantial price and volume fluctuations due to a number of factors, many of which will be beyond our control, which may prevent our shareholders from reselling our common stock at a profit
The securities markets have experienced significant price and volume fluctuations over recent years and the market prices of the securities of technology companies have been especially volatile. For example, our stock had closing prices ranging between a high of $8.75 and a low of $2.98 during the 24 months ended December 31, 2004. This market volatility, as well as general economic, market or political conditions including the war in Iraq, terrorist activity or other acts of violence could reduce the market price of our common stock regardless of our operating performance. Furthermore, because our stock generally trades at relatively low volumes, any sudden increase in trading volumes can cause significant volatility in the stock price. In addition, our operating results could be below the expectations of investment analysts and investors, and in response, the market price of our common stock could decrease significantly. In the past, companies that have experienced volatility in the market price of their stock have been the object of securities class action litigation. If we were the object of securities class action litigation, it could result in substantial costs, liabilities and a diversion of management’s attention and resources.
We may not be able to effectively compete against other providers of products that design FPGAs and ASICs as a result of their greater financial resources, product offerings and distribution channels, which could cause our sales to decline
We face significant competition from larger companies that market suites of semiconductor design software products that address all or almost all steps of semiconductor design or which incorporate intellectual property components for semiconductors. These competitors have greater financial resources and name recognition than we do. We believe that Cadence, Mentor Graphics, Synopsys and Magma, each of which is also currently competing with us by marketing certain logic synthesis or verification products, could provide suites of products or individual products that include the functionality we currently provide in our products and at lower prices, or may otherwise have more favorable relationships with customers. If these or other vendors provide lower cost logic synthesis, physical synthesis or verification products that outperform our products in addition to having broader applications of their existing product lines, our products could become difficult to sell. In addition, we believe our ASIC synthesis and physical synthesis products must provide substantially higher quality and value to potential customers for us to be successful in obtaining meaningful market share in the ASIC software tools market. Even if our competitors’ standard products offer functionality equivalent to that of our products, we face a substantial risk that a significant number of customers would elect to pay a premium for similar functionality rather than purchase products from a less well-known vendor. Increased competition may negatively affect our business and future operating results by leading to price or market share reductions, or higher selling expenses.
Our revenue could be reduced if larger semiconductor design software companies make acquisitions in order to join their extensive distribution capabilities with our competitors’ products
Larger semiconductor design software vendors, such as Cadence, Mentor Graphics, Synopsys and Magma, may acquire or establish cooperative relationships with other companies that may offer or develop competitive products . Because larger semiconductor design software vendors have significant financial and organizational resources, they may be able to further penetrate the logic synthesis, physical synthesis or verification markets by
leveraging the technology and expertise of smaller companies and utilizing their own extensive distribution channels. We expect that the semiconductor design software product industry will continue to consolidate, as evidenced by recently announced acquisitions of Nassda Corporation by Synopsys and Verisity Ltd. by Cadence. It is possible that new competitors or alliances among competitors may emerge and rapidly acquire significant market share, which would harm our business and financial prospects.
Our revenue may decline if other vendors’ products are no longer compatible with ours or other vendors bundle their products with those of our competitors and sell them at lower prices
Our ability to sell our products depends in part on the compatibility of our products with other vendors’ semiconductor design software and verification products. These vendors may change their products so that they will no longer be compatible with our products or may restrict our access to their products, either physically or economically. Some vendors already bundle their products with other logic synthesis, physical synthesis or verification products and sell the bundle at lower prices, and more vendors may do so in the future. As a result, any of these factors may negatively affect our ability to offer commercially viable or competitive products or may reduce sales of, or increase costs for, our products.
We may not be able to preserve the value of our products’ intellectual property rights and other vendors could challenge our intellectual property rights
Our products are differentiated from those of our competitors by our internally developed technology that is incorporated into our products. If we fail to protect our intellectual property rights, other vendors could sell logic synthesis, physical synthesis or verification products with features similar to ours, which could reduce demand for our products. We protect our intellectual property rights through a combination of copyright, trade secret and trademark laws. We have filed a number of patent applications and to date have been issued or allowed 23 patents, all of which are U.S. patents. We generally enter into confidentiality or license agreements with our employees, consultants and corporate partners, and generally seek to control access to our intellectual property rights and the distribution of our logic synthesis, physical synthesis and verification products, documentation and other proprietary information. However, we believe that these measures afford only limited protection. There is the possibility that the validity of some of our patents may be challenged in the future. Others may develop technologies that are similar or superior to our technology or design around the copyrights and trade secrets we own. Despite our efforts to protect our proprietary rights, unauthorized parties may attempt to copy or otherwise improperly obtain and use our products or technology. Policing unauthorized use of our products is difficult and expensive, and we cannot be certain that the steps we have taken will prevent misappropriation of our technology, particularly in foreign countries where the laws may not protect our proprietary rights as fully as those in the United States. For example, with respect to our sales and support operations in India, Indian laws do not protect proprietary rights to the same extent as the United States, and Indian statutory law does not protect service marks. Our means of protecting our proprietary rights may be inadequate.
Our operating results would suffer if we were subject to a protracted infringement claim or a significant damage award
Although we have not been subject to infringement litigation in the past, substantial litigation and threats of litigation regarding intellectual property rights exist in our industry. We expect that logic synthesis, physical synthesis and verification products may be increasingly subject to third-party infringement claims as the number of competitors in our industry segment grows and the functionality of products in different industry segments overlaps. We are not aware that our products employ technology that infringes any valid proprietary rights of third parties. However, third parties may claim that we infringe their intellectual property rights. Any claims, with or without merit, could:
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be time consuming to defend;
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result in costly litigation and/or damage awards;
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divert our management’s attention and resources;
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cause product shipment delays; or
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require us to seek to enter into royalty or licensing agreements.
These royalty or licensing agreements may not be available on terms acceptable to us, if at all. A successful claim of product infringement against us or our failure to license the infringed or similar technology could adversely affect our business because we would not be able to sell the impacted product without exposing ourselves to litigation risk and damages. Furthermore, redevelopment of the product so as to avoid infringement would cause us to incur significant additional expense. Although we maintain general business insurance, it does not cover infringement claims. We would be required to pay any damages and legal expenses from a successful claim ourselves. In addition, because we also provide standard warranties against and indemnification for the potential infringement of third party intellectual property rights to our customers, we would be financially exposed to satisfy these obligations to our customers.
Significant errors in our products or the failure of our products to conform to specifications could result in our customers demanding refunds from us or asserting claims for damages against us
Because our logic synthesis, physical synthesis and verification products are complex, our products could fail to perform as anticipated or produce semiconductors that contain errors which go undetected at any point in the customers’ design cycle. While we continually test our products for errors and work with users through our customer support service organization to identify and correct errors in our software and other product problems, errors in our products may be found in the future. Although a number of these errors may prove to be immaterial, many of these errors could be significant. The detection of any significant errors may result in:
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the loss of or delay in market acceptance and sales of our products;
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delays in shipping dates for our products;
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diversion of development resources from new products to fix errors in existing products;
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injury to our reputation;
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costs of corrective actions or returns of defective products;
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reduction in rates of maintenance renewals; or
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product liability claims or damage awards.
We warrant that our products will operate in accordance with certain specifications. If our products fail to conform to these specifications, customers could demand a refund for the purchase price or assert and collect on claims for damages. Although we maintain general business insurance, our coverage does not extend to product liability claims and we cannot assure that our resources would be sufficient to pay a damages award if one were to arise.
Moreover, because our products are used in connection with other vendors’ products that are used to design complex FPGAs and ASICs, significant liability claims may be asserted against us if our products do not work properly, individually or with other vendors’ products. Our agreements with customers typically contain provisions intended to limit our exposure to liability claims. However, these limitations may not preclude all potential claims and we do not insure against such liabilities. Regardless of their merit, liability claims could require us to spend significant time and money in litigation and divert management’s attention from other business pursuits. If successful, a product liability claim could require us to pay significant damages. Any claim, whether or not successful, could seriously damage our reputation and our business.
As we expand our international operations, we are subject to additional risks and exposures, including economic conditions in foreign locations, foreign exchange rate fluctuations, political and regulatory conditions and other risks
Customers outside North America accounted for approximately $24.2, $20.5 million and $13.5 million of our total revenue in 2004, 2003 and 2002, respectively. Although international revenue has grown over the last few years, we experienced effects of the economic downturn during 2002 in parts of Europe and Japan, and experienced negative effects from the SARS epidemic on our Asia business during 2003. A return of such economic conditions, or an extension of such conditions to other international locations, would adversely impact our business.
We have international offices in the United Kingdom, France, Germany, the Netherlands, Sweden, Israel, India, Japan, Korea, Taiwan and the People’s Republic of China. We also rely on indirect sales in Asia, Europe and elsewhere. Our sales contracts generally provide for payment for our products in U.S. dollars. However, direct sales to our customers in Japan are in yen and we expect all such future sales there will be denominated in yen. We enter into foreign currency forward exchange contracts designed to reduce our exposure to changes in the Japanese yen. Our expenses incurred in foreign locations are generally denominated in the respective local currency, and as a result, our future revenue and expense levels from international operations may be unpredictable due to exchange rate fluctuations. Although we have increased our international sales activities, we still have limited experience in marketing and directly selling our products internationally. Our international operations may be subject to other risks, including:
•
relatively higher personnel and operating costs which may not result in additional revenue;
•
revenue may not be sufficient to cover the expenses associated with establishing a new or expanded international location;
•
the impact of local economic conditions, such as interest rate increases or inflation, which may lead to higher cost of capital and lower demand for products;
•
greater difficulty in accounts receivable collection and longer collection periods;
•
unexpected changes in regulatory requirements, including tariffs, government ownership of communications systems or laws relating to use of and sales over the internet;
•
difficulties and costs of staffing and managing foreign operations;
•
reduced protection for intellectual property rights in some countries;
•
potentially adverse tax consequences, including taxes due on the exercise of stock options or purchase of shares under employee plans by foreign employees and the impact of expiry of tax holidays or applicability of withholding or value added taxes;
•
foreign currency fluctuations;
•
political instability, which may limit the design of FPGAs and/or ASICs in Asia or reduce government or private sector spending on networking and communications equipment; and
•
the impact of epidemic situations such as the SARS epidemic that occurred in 2003.
We may not be successful in integrating the businesses or technologies that we may acquire, or the expected benefits may not be realized as projected
In 2002, we acquired products and technology from IOTA and Bridges2Silicon. We may make additional acquisitions in the future as a part of our efforts to increase revenue and expand our product offerings. In addition to added direct costs, acquisitions pose a number of risks, including:
•
integration of the acquired products and employees into our business;
•
integration of sales channels and training of our sales force for new product offerings;
•
failure to realize expected synergies;
•
failure of acquired products to achieve projected sales;
•
assumption of unknown liabilities; and
•
failure to understand and compete effectively in markets in which we have limited experience.
While we make efforts to analyze acquisition candidates carefully, we cannot be certain that any completed acquisitions will positively impact our business. Future acquisitions could also subject us to significant asset impairment or restructuring charges.
We rely on the services of key personnel, particularly those in our engineering and sales organizations whose knowledge of our business and technical expertise would be difficult to replace, and turnover or other personnel issues in those organizations could negatively impact our revenue
Our products and technologies are complex and we rely on experienced and knowledgeable research and development and sales personnel. We depend substantially on the continued service of Gary Meyers, our President and Chief Executive Officer, and Kenneth S. McElvain, our Chief Technology Officer, Vice President and a founder. We also depend on our sales personnel, particularly in certain areas of Europe and Asia where we employ a relatively small sales team. For example, we recently experienced weakness in certain of our Asian sales locations due to reorganization within our Asia sales force. There are a limited number of qualified people with the technical skills and understanding of FPGAs and ASICs and/or EDA software necessary to our business, and if we are unable to retain or find suitable replacements for any turnover in our engineering and sales organizations, our business could be adversely affected.
Modifications to our effective tax rates or government reviews of our tax returns could affect our results of operations
We are subject to income and transaction taxes in the United States and in multiple foreign locations. Determining our worldwide provision for income taxes involves judgment and estimates and we cannot be certain that no subsequent adjustments will be needed should updated information become available. Future effective tax rates could be affected by changes in our foreign tax estimates, the valuation of our deferred tax assets and liabilities, or changes in tax laws or the interpretation of such tax laws. We have been subject to tax audits in the past including income, sales and property tax audits, and may be subject to additional domestic and international tax audits in the future. For example, we are currently undergoing an audit of our United States federal income tax return for 2002. Although we believe our tax estimates are reasonable, we cannot be certain that the results of this audit or any other audit will not require any adjustments to our historical income tax provisions and accruals. If additional taxes are assessed during this audit or a future audit, our operating results or financial position could be materially affected.
Proposed changes in financial accounting standards related to equity compensation will cause us to record additional expense in the future, which would result in a reduction in our net income
In December 2004, the Financial Accounting Standards Board issued Statement of Financial Accounting Standards No. 123 (revised 2004), Share-Based Payment (“SFAS 123R”), which will be effective in the third quarter of 2005. SFAS 123R will result in our recognition of substantial compensation expense relating to our employee stock options and employee stock purchase plan. We currently use the intrinsic value method to measure compensation expense for stock-based awards to our employees. Under this standard, we generally do not recognize any compensation related to stock option grants we issue under our stock option plans or related to the discounts we provide under our employee stock purchase plan. Under the new standard, we are required to adopt a fair-value-based method for measuring the compensation expense related to employee stock awards; this will lead to substantial additional compensation expense and therefore will have a material adverse effect on our reported results of operations. The Stock-Based Compensation section of the footnotes to the Consolidated Financial Statements shown below provides our pro forma net income and earnings per share as if we had used a fair-value-based method similar to the methods required under SFAS 123R to measure the compensation expense for employee stock awards during 2004, 2003 and 2002.
Corporate governance regulations have recently increased our costs as a result of attaining compliance, which could further increase our expenses if changes occur within our business
Changes in laws and regulations affecting public companies, including the provisions of the Sarbanes-Oxley Act of 2002, have imposed new requirements on us and on our officers, directors, attorneys and independent accountants. In order to comply with these new rules, we have added internal resources and have utilized additional outside legal, accounting and advisory services, which have increased and are likely to continue increasing our operating expenses. In particular, we expect to incur additional administrative expenses as we maintain compliance with Section 404 of the Sarbanes-Oxley Act, which requires management to report on, and our Independent Registered Public Accounting Firm to attest to, our internal controls. In addition, if we undergo significant modifications to our structure through personnel or system changes, acquisitions, or otherwise, it may be increasingly difficult to maintain compliance with the existing and evolving corporate governance regulations.
ITEM 7A.
ITEM 7A. QUANTITATIVE AND QUALITATIVE DISCLOSURES ABOUT MARKET RISK
We develop products in the United States and sell those products primarily in North America, Europe and Japan. Our revenue from sales outside North America was 42%, 41% and 30% of our total revenue in 2004, 2003 and 2002, respectively. As a result, our financial results could be affected by factors such as changes in foreign currency exchange rates or weak economic conditions in foreign markets. With the exception of sales in Japan, our sales are generally made in U.S. dollars, thus a strengthening of the U.S. dollar could make our products less competitive in foreign markets. The functional currency of our foreign subsidiaries excluding Japan is the U.S. dollar. The functional currency of our Japanese subsidiary is the yen. The effects of translation of our foreign subsidiaries for which the U.S. dollar is the functional currency are included in the results of operations, and to date have not been material. The effects of translation of our Japanese subsidiary are included in shareholders’ equity and to date have not been material. Historically, our exposure to foreign exchange fluctuations has been minimal. If foreign currency rates were to fluctuate by 100 basis points from rates as of December 31, 2004, the effect on our operating results and financial position would not be material. However, as our international sales and operations have expanded, our exposure to foreign currency fluctuations has increased, particularly in Japan. In January 2003, we began entering into foreign currency forward exchange contracts designed to reduce our exposure to changes in the Japanese yen. The outstanding forward contracts generally have maturities of approximately one month from the date into which they were entered and are entered into at or near the end of the month . These contracts are remeasured monthly using spot rates, with any gain or loss from rate fluctuations recorded in the statement of operations. The changes in the values of the forward contracts were not material for the year ended December 31, 2004.
Our interest income is sensitive to changes in the general level of U.S. interest rates, particularly since the majority of our investments are in short-term instruments. Due to the nature of our short-term investments, we have concluded that we do not have material market risk exposure. If market interest rates were to change immediately and uniformly by 100 basis points from levels as of December 31, 2004, the change in the fair value of our investment portfolio would not be material.
Our investment policy requires us to invest funds in excess of current operating requirements in:
•
obligations of the U.S. government and its agencies;
•
investment grade state and local government obligations;
•
securities of U.S. corporations rated A1 or P1 by Standard & Poors’ or the Moody’s equivalents; and/or money market funds, deposits or notes issued or guaranteed by U.S. and non-U.S. commercial banks meeting certain credit rating and net worth requirements with maturities of less than two years.
As of December 31, 2004, our cash equivalents consisted primarily of U.S. government agency notes, money market funds and certificates of deposit and our short-term investments consisted of U.S. government agency notes, corporate notes, bankers acceptance, and certificates of deposit.
ITEM 8.
ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA
Our consolidated financial statements and the independent auditors’ report appear on pages 48 through 69 of this Annual Report.
Quarterly Data (unaudited)
ITEM 9.
ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND FINANCIAL DISCLOSURE
Not applicable.
ITEM 9A.
ITEM 9A. CONTROLS AND PROCEDURES
(a) Evaluation of disclosure controls and procedures.
We have carried out an evaluation, under the supervision and with the participation of our management, including our Chief Executive Officer and our Chief Financial Officer, of the effectiveness of the design and operation of our disclosure controls and procedures (as defined in Rules 13a-15(e) and 15d-15(e) under the Exchange Act) as of the end of the period covered by this Annual Report on Form 10-K. Based upon that evaluation, our Chief Executive Officer and our Chief Financial Officer concluded that our disclosure controls and procedures are effective to ensure that material information required to be disclosed by us in the reports that we file or submit under the Exchange Act is recorded, processed, summarized and reported within the time periods specified in the Securities and Exchange Commission rules and forms.
(b) Reports of Internal Control over Financial Reporting
Report of Synplicity Inc. Management on Internal Control over Financial Reporting
Our management is responsible for establishing and maintaining adequate internal control over financial reporting. Our internal control system was designed to provide reasonable assurance to our management and board of directors regarding the preparation and fair presentation of published financial statements. All internal control systems, no matter how well designed, have inherent limitations. Therefore, even those systems determined to be effective can provide only reasonable assurance with respect to financial statement preparation and presentation. Our management assessed the effectiveness of our internal control over financial reporting as of December 31, 2004. In making this assessment, it used the criteria set forth by the Committee of Sponsoring Organizations of the Treadway Commission (COSO) in Internal Control-Integrated Framework. Based on our
management’s assessment, it believes that, as of December 31, 2004, our internal control over financial reporting was effective based on those criteria. Our independent registered public accounting firm has issued an attestation report on management’s assessment of our internal control over financial reporting, which appears below.
Report of Independent Registered Public Accounting Firm
To the Board of Directors and Shareholders of Synplicity, Inc.
We have audited management’s assessment, included in the accompanying Report of Synplicity Inc. (the “Company”) Management on Internal Control over Financial Reporting, that the Company maintained effective internal control over financial reporting as of December 31, 2004, based on criteria established in Internal Control-Integrated Framework issued by the Committee of Sponsoring Organizations of the Treadway Commission (the COSO criteria). The Company’s management is responsible for maintaining effective internal control over financial reporting and for its assessment of the effectiveness of internal control over financial reporting. Our responsibility is to express an opinion on management’s assessment and an opinion on the effectiveness of the company’s internal control over financial reporting based on our audit.
We conducted our audit in accordance with the standards of the Public Company Accounting Oversight Board (United States). Those standards require that we plan and perform the audit to obtain reasonable assurance about whether effective internal control over financial reporting was maintained in all material respects. Our audit included obtaining an understanding of internal control over financial reporting, evaluating management’s assessment, testing and evaluating the design and operating effectiveness of internal control, and performing such other procedures as we considered necessary in the circumstances. We believe that our audit provides a reasonable basis for our opinion.
A company’s internal control over financial reporting is a process designed to provide reasonable assurance regarding the reliability of financial reporting and the preparation of financial statements for external purposes in accordance with generally accepted accounting principles. A company’s internal control over financial reporting includes those policies and procedures that (1) pertain to the maintenance of records that, in reasonable detail, accurately and fairly reflect the transactions and dispositions of the assets of the company; (2) provide reasonable assurance that transactions are recorded as necessary to permit preparation of financial statements in accordance with generally accepted accounting principles, and that receipts and expenditures of the company are being made only in accordance with authorizations of management and directors of the company; and (3) provide reasonable assurance regarding prevention or timely detection of unauthorized acquisition, use, or disposition of the company’s assets that could have a material effect on the financial statements.
Because of its inherent limitations, internal control over financial reporting may not prevent or detect misstatements. Also, projections of any evaluation of effectiveness to future periods are subject to the risk that controls may become inadequate because of changes in conditions, or that the degree of compliance with the policies or procedures may deteriorate.
In our opinion, management’s assessment that Synplicity, Inc. maintained effective internal control over financial reporting as of December 31, 2004, is fairly stated, in all material respects, based on the COSO criteria. Also, in our opinion, Synplicity, Inc. maintained, in all material respects, effective internal control over financial reporting as of December 31, 2004, based on the COSO criteria.
We also have audited, in accordance with the standards of the Public Company Accounting Oversight Board (United States), the consolidated balance sheets of Synplicity, Inc. as of December 31, 2004 and 2003, and the related consolidated statements of income, shareholders’ equity, and cash flows for each of the three years in the period ended December 31, 2004, and our report dated March 2, 2005 expressed an unqualified opinion thereon.
Palo Alto, California
March 2, 2005
(c) Changes in internal control over financial reporting.
There were no changes in our internal control over financial reporting (as defined in Rule 13a-15(f) of the Exchange Act) during the quarter ended December 31, 2004 that had materially affected, or are reasonably likely to materially affect, our internal control over financial reporting.
ITEM 9B.
ITEM 9B. OTHER INFORMATION
Not applicable.
PART III
ITEM 10.
ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT
The information required by this item is incorporated by reference from the sections captioned “Proposal One-Election of Directors” and “Section 16(a) Beneficial Ownership Reporting Compliance” contained in our Proxy Statement. Certain information required by this item concerning executive officers is set forth in Part I of this Annual Report in “Business-Management.”
We have adopted a code of ethics that applies to principal executive officers, senior financial officers and Section 16 officers (including our Chief Executive Officer and Chief Financial Officer). We have posted this code of ethics on our website at www.synplicity.com on our Investor Relations page. We intend to satisfy the disclosure requirement under Item 10 of Form 8-K regarding any amendments to or waivers from the code of ethics by posting such information on our website at www.synplicity.com.
ITEM 11.
ITEM 11. EXECUTIVE COMPENSATION
The information required by this item is incorporated by reference from the section captioned “Executive Compensation” contained in our Proxy Statement.
ITEM 12.
ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT
The information required by this item is incorporated by reference from the sections captioned “Principal Shareholders” and “Executive Compensation-Equity Compensation Plan Information” contained in our Proxy Statement.
ITEM 13.
ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS
The information required by this item is incorporated by reference from the sections captioned “Compensation Committee Interlocks and Insider Participation” and “Related Party Transactions” contained in our Proxy Statement.
ITEM 14.
ITEM 14. PRINCIPAL ACCOUNTANT FEES AND SERVICES.
The information required by this item is incorporated by reference from the section captioned “Proposal Two-Ratification of Appointment of the Independent Registered Public Accounting Firm” contained in our Proxy Statement.
PART IV
ITEM 15.
ITEM 15. EXHIBITS AND FINANCIAL STATEMENT SCHEDULES AND REPORTS ON FORM 8-K.
(a)(1) Financial Statements
The following consolidated financial statements are included in this Annual Report on Form 10-K:
Page
Report of Independent Registered Public Accounting Firm
Consolidated Financial Statements:
Consolidated Balance Sheets
Consolidated Statements of Operations
Consolidated Statements of Shareholders’ Equity
Consolidated Statements of Cash Flows
Notes to Consolidated Financial Statements
(a)(2) Financial Statement Schedules
Schedule II-Valuation and Qualifying Accounts and Reserves (see page 71)
Schedules not listed above have been omitted because the information required to be set forth therein is not applicable or is shown in the financial statements or notes thereto.
(a)(3) Exhibits
(1) Portions of the exhibit have been omitted pursuant to a request for confidential treatment and the omitted portions have been separately filed with the Commission.
(2) Filed as an exhibit to the Company’s Registration Statement on Form S-1 (File No. 333-42146) as declared effective by the Securities and Exchange Commission on October 12, 2000.
(3) Filed as an exhibit to the Company’s Annual Report on Form 10-K for the fiscal year ended December 31, 2000.
(4) Filed as an exhibit to the Company’s Annual Report on Form 10-K for the fiscal year ended December 31, 2001.
(5) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended September 30, 2002.
(6) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended March 31, 2003.
(7) Filed as an exhibit to the Company’s Annual Report on Form 10-K for the fiscal year ended December 31, 2003.
(8) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended March 31, 2004.
(9) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended June 30, 2004.
(10) Filed as an exhibit to the Company’s 8-K filed September 22, 2004.
(11) Filed as an exhibit to the Company’s 8-K filed October 4, 2004.
(12) Indicates a management contract or compensatory plan or arrangement.
(b) Exhibits. See Item 15(a)(3) above.
(c) Financial Statement Schedules. See Item 15(a)(2) above.
REPORT OF INDEPENDENT REGISTERED PUBLIC ACCOUNTING FIRM
The Board of Directors and Shareholders
Synplicity, Inc.
We have audited the accompanying consolidated balance sheets of Synplicity, Inc. (the “Company”) as of December 31, 2004 and 2003, and the related consolidated statements of operations, shareholders’ equity, and cash flows for each of the three years in the period ended December 31, 2004. Our audits also included the financial statement schedule listed in the index appearing under Item 15(a)(2) of the Annual Report on Form 10-K for the year ended December 31, 2004. The financial statements and schedule are the responsibility of the Company’s management. Our responsibility is to express an opinion on these financial statements and schedule based on our audits.
We conducted our audits in accordance with standards of the Public Company Oversight Board (United States). Those standards require that we plan and perform the audit to obtain reasonable assurance about whether the financial statements are free of material misstatement. An audit includes examining, on a test basis, evidence supporting the amounts and disclosures in the financial statements. An audit also includes assessing the accounting principles used and significant estimates made by management, as well as evaluating the overall financial statement presentation. We believe that our audits provide a reasonable basis for our opinion.
In our opinion, the financial statements referred to above present fairly, in all material respects, the consolidated financial position of the Company at December 31, 2004 and 2003, and the consolidated results of its operations and its cash flows for each of the three years in the period ended December 31, 2004, in conformity with U.S. generally accepted accounting principles. Also, in our opinion, the related financial statement schedule, when considered in relation to the basic financial statements taken as a whole, presents fairly in all material respects the information set forth therein.
We also have audited, in accordance with the standards of the Public Company Accounting Oversight Board (United States), the effectiveness of the Company’s internal control over financial reporting as of December 31, 2004, based on criteria established in Internal Control-Integrated Framework issued by the Committee of Sponsoring Organizations of the Treadway Commission and our report dated March 2, 2005 expressed an unqualified opinion thereon.
Palo Alto, California
March 2, 2005
SYNPLICITY, INC.
CONSOLIDATED BALANCE SHEETS
(in thousands, except share data)
The accompanying notes are an integral part of the condensed consolidated financial statements.
SYNPLICITY, INC.
CONSOLIDATED STATEMENTS OF OPERATIONS
(in thousands, except per share data)
The accompanying notes are an integral part of the condensed consolidated financial statements.
SYNPLICITY, INC.
CONSOLIDATED STATEMENTS OF SHAREHOLDERS’ EQUITY
(in thousands)
The accompanying notes are an integral part of the condensed consolidated financial statements.
SYNPLICITY, INC.
CONSOLIDATED STATEMENTS OF CASH FLOWS
(in thousands)
The accompanying notes are an integral part of the condensed consolidated financial statements.
SYNPLICITY, INC.
NOTES TO CONSOLIDATED FINANCIAL STATEMENTS
Note 1. Significant Accounting Policies
Organization and Business
Synplicity Inc. (“we” or “us”) was incorporated on February 1, 1994 in the State of California. We are a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer, automotive, military/aerospace and other electronics systems.
Principles of Consolidation
The consolidated financial statements include the accounts of our company and our wholly owned subsidiaries. All significant intercompany balances and transactions have been eliminated.
Foreign Currency Translation
The functional currency of our foreign subsidiaries is the U.S. dollar, with the exception of our Japanese subsidiary for which the yen is its functional currency. For our foreign subsidiaries for which the U.S. dollar is the functional currency, assets and liabilities denominated in foreign currencies are translated at the month-end exchange rate, except for non-monetary assets and liabilities such as property and equipment, which are translated at historical rates. Revenue and expenses are translated at the average exchange rate for the period, except for expenses related to those balance sheet items that are translated using historical rates. Adjustments resulting from these translations are included in our results of operations. For our Japanese subsidiary, assets and liabilities are denominated in yen and translated at the month-end exchange rate, and equity balances are translated at historical rates. Revenue and expenses are translated at the average exchange rate for the period. Adjustments resulting from these translations are included in shareholders’ equity.
Derivative Instruments
In January 2003, we began entering into foreign currency forward exchange contracts designed to reduce our exposure to changes in the Japanese yen. The outstanding forward contracts generally have maturities of approximately one month from the date into which they were entered and are entered into at or near the end of the month. These contracts are remeasured monthly using spot rates, with any gain or loss from rate fluctuations recorded in the statement of operations. The changes in the values of the forward contracts were not material for 2003 and 2004.
Use of Estimates
The preparation of consolidated financial statements in conformity with generally accepted accounting principles requires management to make estimates and assumptions that affect the amounts reported in the financial statements and the accompanying notes. For example, estimates and assumptions are used in recognizing or deferring revenue and in maintaining our allowance for doubtful accounts. Actual results could differ from these estimates.
Reclassifications
Certain amounts reported in the consolidated financial statements as of December 31, 2002 have been reclassified to conform with the presentation adopted to report 2003 and 2004 results.
SYNPLICITY, INC.
NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Concentration of Credit Risk
We distribute our products through our direct sales force and third-party distributors throughout North America, principally the United States, as well as in Europe, Japan and the rest of Asia. We generally do not require collateral. We maintain and update quarterly an allowance for doubtful accounts for estimated potential credit losses, and such losses in 2004 and 2003 were not material. No customer or distributor accounted for 10% or more of total revenue for the years ended December 31, 2004, 2003 and 2002. Sales to customers outside of North America accounted for $24.2 million, $20.5 million and $13.5 million of our total revenue in 2004, 2003 and 2002, respectively.
In accordance with our investment policy, we invest only in high credit quality debt instruments held by reputable financial institutions.
Cash Equivalents and Investments
All of our cash equivalents and investments are classified as available-for-sale and are reported at fair value. Unrealized gains and losses (determined as the difference between the recorded amount of the investment and its fair value) are reported in shareholders’ equity as a component of accumulated other comprehensive income (loss), net of tax, if any. The fair value of the investments is based on quoted market prices. Realized gains and losses are included in other income and to date have not been material. Investments that have maturities of three months or less at the date of purchase are considered cash equivalents, while investments that have maturities greater than three months at the date of purchase are considered either short-term investments if they mature within 12 months of the balance sheet date, or long-term investments if they mature beyond 12 months of the balance sheet date. The cost of securities sold is based upon the specific identification method.
Accounts Receivable
Our receivables are recorded when billed and represent claims against third parties that will be settled in cash. The carrying value of our receivables, net of the allowance for doubtful accounts, represents their estimated net realizable value.
Allowance for Doubtful Accounts.
We maintain and update quarterly an allowance for doubtful accounts for estimated losses resulting from the failure of our customers to make required payments. The balance in the allowance account is comprised of a specific reserve for any particular receivable when collectibility is not probable, and a provision for non-specific accounts based on a specified range of percentages derived from historical experience applied to the outstanding balance in each aged group. If after pursuing collection efforts on a specifically reserved receivable and payment is not expected, the receivable is deemed uncollectible and is written off. Such losses have not been material in any year.
Property and Equipment
Property and equipment are stated at cost, less accumulated depreciation. Depreciation is provided using the straight-line method over the estimated useful lives of the respective assets, generally three years to seven years.
Impairment of Long-Lived Assets
In accordance with the provisions of Statement of Financial Accounting Standards No. 144, Accounting for the Impairment or Disposal of Long-Lived Assets (“SFAS 144”), we review long-lived assets, including property and equipment and intangible assets, for impairment whenever events or changes in business circumstances
SYNPLICITY, INC.
NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
indicate that the carrying amounts of the assets may not be fully recoverable. Under SFAS 144, an impairment loss would be recognized when estimated undiscounted future cash flows expected to result from the use of the asset and its eventual disposition are less than its carrying amount. Impairment, if any, is assessed using discounted cash flows. Through December 31, 2004, we did not have any such impairment losses.
Revenue Recognition
For each sale of a perpetual license, the first year of maintenance is generally sold with the license. We defer the recognition of license and maintenance revenue until:
•
a purchase order is received from the customer,
•
delivery of the product and perpetual license key has occurred,
•
the fee is fixed or determinable,
•
collection of the fee is probable and
•
we have no remaining obligations other than maintenance.
Once all of the above conditions have been met, license revenue is recognized based upon the residual method after all elements other than maintenance have been delivered in accordance with AICPA Statement of Position 98-9, Modification of SOP No. 97-2 with Respect to Certain Transactions. Maintenance revenue is recognized on a straight-line basis over the maintenance period since customers under maintenance agreements receive unspecified product updates, electronic, internet-based technical support and telephone support throughout their maintenance period, which is typically one year. The majority of our customers also purchase maintenance renewals annually on a stand alone basis at either 15 or 20% of the perpetual license list price, depending on the product, which establishes vendor specific objective evidence (“VSOE”) of the fair value of maintenance.
We also offer two-year and three-year term licenses for certain products under which the customer purchases the first year of maintenance with the license and can renew maintenance in each of the following one or two years. Revenue from term licenses is recognized in the same manner as revenue from perpetual licenses as VSOE of the fair value of maintenance is established by the maintenance renewal pricing at either 15 or 20% of the perpetual license list price, depending on the product.
We assess whether the fee is fixed or determinable for sales with non-standard payment terms by evaluating our history of collections from these customers and/or their current financial standing. In no case will we deem a fee to be fixed or determinable where the fee is due after the expiration of the license or more than 12 months after delivery. We make judgments as to whether collection of the fee is probable based on the analysis provided by our credit review procedures. Revenue on arrangements to end-user customers that have met all of the revenue recognition criteria except probability of collection is recognized as collection becomes reasonably assured, which is generally as payments are received.
Revenue on sales to distributors is considered to have met the probability of collection criterion when the distributor has resold the product to an end user and either we have received payment for the product or we assess that we have a substantial and sustained history of collections from the distributor.
We also sell time-based licenses to use our software products for specified periods of time. Time-based licenses include maintenance services for the duration of their respective terms. Revenue from time-based licenses is allocated between license and maintenance revenue in similar proportion to perpetual license transactions, and recognized on a straight-line basis over the period of the license as we do not have VSOE of the
SYNPLICITY, INC.
NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
fair value of maintenance for time-based licenses since it is not priced or offered separately. In addition, we have provided a version of one of our products to certain field programmable gate array (“FPGA”) manufacturers for distribution to their customers. As part of this arrangement we have certain maintenance and support obligations to the FPGA manufacturers. Revenue on this arrangement is also allocated to license and maintenance revenue and recognized on a straight-line basis over the period of each arrangement, as we do not have VSOE of fair value of maintenance for these arrangements since it is not priced or offered separately.
Furthermore, we may sell time-based licenses combined in an order with perpetual or term licenses. For these transactions, we recognize revenue from the entire transaction straight-line over the term of the time-based license in the transaction, as generally we do not have VSOE on time-based licenses.
We have entered into agreements with semiconductor manufacturers LSI Logic Corporation, NEC Electronics Corporation and Fujitsu Microelectronics to customize our ASIC synthesis or physical synthesis tools for certain of their products. When time-based licenses are being purchased as part of the agreement, once the contract has been signed, delivery of the customized product has occurred, collection of the fee is probable and we have no remaining obligations other than maintenance, we recognize revenue from both the development and license fees on a straight-line basis over the period of the licenses since we do not have VSOE of fair value of the time-based licenses. When licenses are not being purchased as part of the agreement, once the contract has been signed, we recognize revenue from the development fees on a percentage of completion basis. Revenue recognized from these arrangements represents less than 10% of total revenue and is recorded in license revenue.
Goodwill and Intangible Assets
In accordance with Statement of Financial Accounting Standards No. 142, Goodwill and Other Intangible Assets (“SFAS 142”), goodwill is not amortized but is tested for impairment using a fair value approach. Goodwill is tested for impairment annually during the fourth quarter as well as whenever indicators of impairment exist. In accordance with the provisions of Statement of Financial Accounting Standards No. 144, Accounting for the Impairment or Disposal of Long-Lived Assets (“SFAS 144”), long-lived assets, including intangible assets and property and equipment, are reviewed for impairment whenever events or changes in circumstances indicate that their carrying amount may not be recoverable. Recoverability of a long lived asset other than goodwill is measured by comparison of its carrying amount to the expected future undiscounted cash flows that the asset is expected to generate. An impairment charge is recorded if the carrying amount of the asset exceeds the sum of the expected undiscounted cash flows. Any impairment to be recognized is measured by the amount by which the carrying amount of the asset exceeds its fair value. Fair value is determined based on discounted cash flows or appraised values, depending upon the nature of the assets. Significant management judgment is required in forecasting future operating results and cash flows and, should different conditions prevail or judgments be made, material write-downs of net intangible assets and/or goodwill could occur; however, no impairment to date has been recorded. Our intangible assets are being amortized using the straight-line method over the estimated useful life of five years.
Product Development Costs
Statement of Financial Accounting Standards No. 86, Accounting for the Costs of Computer Software to Be Sold, Leased, or Otherwise Marketed, requires capitalization of certain software development costs subsequent to the establishment of technological feasibility. Based on our product development process, technological feasibility is established upon completion of a working model. Costs we incurred between completion of the working model and the point at which the product is ready for general release have been insignificant. Therefore, all product development costs have been charged to operations as incurred.
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Advertising
Costs related to advertising are expensed as incurred. Advertising expense for 2004, 2003 and 2002 was $121,000, $147,000 and $301,000, respectively.
Guarantees
We generally warrant that the program portion of our software will perform substantially in accordance with certain specifications for a period of 90 days. Our liability for a breach of this warranty is either a return of the license and maintenance fees or providing a fix, patch, work-around, or replacement of the software.
We provide standard warranties against and indemnification for the potential infringement of third party intellectual property rights to our customers relating to the use of our products. We also have indemnification agreements with members of our board of directors, certain officers and employees under which we may be required to indemnify such persons for liabilities arising out of their duties to us. Our bylaws also provide for indemnification to directors, officers and employees. The terms of such obligations vary. Generally, the maximum obligation is the amount permitted by law.
Historically, costs related to these guarantees have not been significant and we are unable to estimate the potential impact of these guarantees on our future results of operations. No liabilities were recorded for these guarantees on our balance sheet as of December 31, 2004.
Accumulated Other Comprehensive Income
We apply Statement of Financial Accounting Standards No. 130, Reporting Comprehensive Income (“SFAS 130”). SFAS 130 establishes rules for the reporting and display of comprehensive income and its components, which include unrealized gains and losses on available-for-sale securities and foreign currency translation adjustments. For 2004, 2003 and 2002, the components of comprehensive income (loss) have been included in the Statement of Shareholders’ Equity. The components of accumulated other comprehensive loss are as follows (in thousands):
Segment Information
We follow Statement of Financial Accounting Standards No. 131, Disclosures About Segments of an Enterprise and Related Information (“SFAS 131”). SFAS 131 establishes standards for the way that public business enterprises report information about operating segments in interim financial reports. SFAS 131 also establishes standards for related disclosures about products and services, geographic areas and major customers. We operate in only one industry segment, the development and licensing of software products that are used in the design and verification of semiconductors. We market and sell our products throughout North America, principally the United States, as well as in Europe, Japan and the rest of Asia.
Stock-Based Compensation
As permitted by Statement of Financial Accounting Standards No. 123, Accounting for Stock-Based Compensation (“SFAS 123”), as amended by Statement of Financial Accounting Standards No. 148, Accounting for Stock-Based Compensation-Transition and Disclosure, we have elected the disclosure-only alternative under
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
SFAS 123 and have elected to account for employee stock based compensation in accordance with the intrinsic value method under Accounting Principles Board Opinion No. 25, Accounting for Stock Issued to Employees (“APB 25”), as amended. Under APB 25, when the exercise price of our employee stock options equals or exceeds the market price of the underlying stock on the date of grant, no compensation expense is recognized.
Any deferred stock compensation calculated according to APB 25 is amortized over the vesting period of the individual option, generally four years, using the graded vesting method. The graded vesting method provides for vesting of portions for the overall awards at interim dates and results in greater stock-based compensation expense in earlier years than the straight-line vesting method.
Pro forma information regarding net income (loss) has been determined as if we had accounted for our employee stock options under the fair value method prescribed by SFAS 123. The resulting effect on pro forma net income (loss) disclosed is not likely to be representative of the effects on net income (loss) on a pro forma basis in future years, due to additional grants and years of vesting in subsequent years. For each of the three years ended December 31, 2004, the fair value of our stock-based awards to employees was estimated at the date of grant using the Black-Scholes option pricing model, assuming no expected dividends and the following weighted-average assumptions:
For pro forma purposes, the estimated fair value of our stock-based awards to employees is amortized over the awards’ vesting period. Pro forma information follows (in thousands, except per share data):
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Recently Issued Accounting Standard
In December 2004, the Financial Accounting Standards Board issued Statement of Financial Accounting Standards No. 123 (revised 2004), Share-Based Payments (“SFAS 123R”), which will be effective in the third quarter of 2005. SFAS 123R will result in our recognition of substantial compensation expense relating to our employee stock options and employee stock purchase plan. We currently use the intrinsic value method to measure compensation expense for stock-based awards to our employees. Under this standard, we generally do not recognize any compensation related to stock option grants we issue under our stock option plans or related to the discounts we provide under our employee stock purchase plan. Under the new standard, we are required to adopt a fair-value-based method for measuring the compensation expense related to employee stock awards; this will lead to substantial additional compensation expense and therefore will have a material adverse effect on our reported results of operations. The Stock-Based Compensation section shown above provides our pro forma net income and earnings per share as if we had used a fair-value-based method similar to the methods required under SFAS 123R to measure the compensation expense for employee stock awards during 2004, 2003 and 2002.
Note 2. Financial Instruments
Available-for-sale securities were as follows as of December 31, 2004 and 2003 (in thousands):
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Note 3. Property and Equipment
Property and equipment consisted of the following (in thousands):
Note 4. Commitments and Contingencies
Accrued Liabilities and Leases
Accrued liabilities are comprised primarily of fees to external service providers and other accrued liabilities.
We lease our corporate facility in Sunnyvale, California and lease a number of sales or development offices in various states as well as in certain other countries. In September 2002, we entered into a new corporate facility lease in Sunnyvale, California, which expires in August 2007 and has an option to extend the lease by five years. Additionally, a number of our other leases contain various renewal options. We also have operating leases for automobiles, computers and office equipment and we have purchase commitments primarily related to software and telephone services. Additionally, we had certain equipment under a lease financing agreement as described below.
In November 1999, we entered into an equipment lease financing agreement with a lessor that provided for leasing of up to $1.5 million of equipment, including up to $450,000 of software and tenant improvements. All scheduled leases were payable in 36 equal monthly installments. Based on the terms of the individual leases, the leases were treated as either operating or capital. Additionally, we granted the lessor fully vested warrants to purchase up to 14,035 shares of common stock at $4.28 per share, which were exercised during 2001. As of December 31, 2004, no remaining capital lease obligation existed under this agreement and the availability of additional borrowings had been terminated. The capital equipment was previously written off and the operating leases expired in 2004.
Rent expense was approximately $2.6 million for 2004 and $2.7 million for 2003 and 2002.
Future Payments
Our future minimum payments at December 31, 2004 are as follows (in thousands):
(1) Purchase obligations exclude agreements that are cancelable without penalty.
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Legal Proceedings
From time to time, we have been subject to legal proceedings and claims in the ordinary course of business. We are not currently aware of any legal proceedings or claims that we believe will have, individually or in the aggregate, a material adverse effect on our business, results of operations or financial condition.
Note 5. Related Party Transactions
In September 1998, we loaned one of our officers $312,000 through the issuance of two full-recourse notes. The notes were repaid in full in 2003.
During 2004, 2003 and 2002, we incurred expenses of approximately $90,000, $92,000 and $90,000, respectively, for certain technical software development consulting services provided to us by the father of one of our officers.
Note 6. Net Income (Loss) Per Share
Basic net income (loss) per share is computed using the weighted-average number of shares of common stock outstanding during the period, less the weighted-average number of shares of common stock that are subject to repurchase. Diluted net income (loss) per share includes the impact of options to purchase common stock, if dilutive, using the treasury stock method.
The following table presents the calculation of basic and diluted net income (loss) per share (in thousands, except per share data):
We have excluded weighted average outstanding stock options, which aggregated 2,769,537 from the calculation of diluted net income per share for 2004, because such securities were antidilutive. We have excluded all weighted average outstanding stock options and shares subject to repurchase by us from the calculation of
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
diluted net loss per share for 2003 and 2002, which aggregated 4,457,921 shares and 4,811,876 shares, respectively, because all such securities were antidilutive. Such securities, had they been dilutive, would have been included in the computation of diluted net income (loss) per share using the treasury stock method.
Note 7. Acquisitions
IOTA Technology, Inc.
In July 2002, we completed an acquisition of key products and technology from IOTA Technology, Inc. (“IOTA”), which we accounted for as a business acquisition per the guidelines of Emerging Issues Task Force 98-3, Determining Whether a Nonmonetary Transaction Involves Receipt of Productive Assets or of a Business (“EITF 98-3”). We acquired signal integrity and power analysis technology, power planning and analysis products, as well as additional deep submicron intellectual property. The estimated synergistic value of the acquired signal integrity and power analysis technology with our existing products on the date of acquisition contributed to goodwill. IOTA’s results of operations were included in our statements of operations from the date of acquisition.
The total purchase price was approximately $5.6 million, comprised of the following: (a) $4.1 million in cash, (b) 300,000 shares of our common stock valued at approximately $1.4 million based on the average closing market price of our common stock over the two trading-day period prior to and including July 2, 2002 and (c) approximately $100,000 of acquisition-related costs. Of the 300,000 shares of our common stock that were issued, 100,000 were held in escrow until they were released in January 2004.
The purchase price was allocated based on the estimated fair value of net tangible and intangible assets acquired, assumed liabilities and in-process research and development. The fair value of significant assets acquired was determined with the assistance of an independent valuation. The intangible assets subject to amortization are being amortized on a straight-line basis over five years. As of the acquisition date, technological feasibility of the in-process technology had not been established and the technology had no alternative future use. Therefore, the $1.7 million assigned to in-process research and development assets was expensed at the date of acquisition. The amount of the purchase price allocated to in-process research and development was determined based on the estimated stage of development of each in-process research and development project at the date of acquisition and estimated cash flows resulting from the expected revenue generated from such projects, with the net cash flows discounted to present value at a 27% discount rate.
The following table summarizes the estimated fair values of the assets acquired and liabilities assumed at the date of the acquisition (in thousands):
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Bridges2Silicon, Inc.
In November 2002, we completed a product and technology acquisition from Bridges2Silicon, Inc. We acquired their FPGA RTL debug product, core technology and other intellectual property. As the product and technology acquired did not constitute a business per the guidelines of EITF 98-3, we accounted for the transaction as an acquisition of assets.
The total purchase price was approximately $2.6 million, comprised of $2.5 million in cash and approximately $100,000 of acquisition-related costs.
The purchase price was allocated based on the estimated fair value of net tangible and intangible assets acquired, assumed liabilities and in-process research and development. The fair value of significant assets acquired was determined with the assistance of an independent valuation. The intangible assets subject to amortization are being amortized on a straight-line basis over five years. As of the acquisition date, technological feasibility of the in-process technology had not been established and the technology had no alternative future use. Therefore, the $400,000 assigned to in-process research and development assets was expensed at the date of acquisition. The amount of the purchase price allocated to in-process research and development was determined based on the estimated stage of development of each in-process research and development project at the date of acquisition and estimated cash flows resulting from the expected revenue generated from such projects, with the net cash flows discounted to present value at a 28% discount rate.
The following table summarizes the estimated fair values of the assets acquired at the date of the acquisition (in thousands):
In December 2002, we acquired certain ASIC technology for $700,000 in cash, which we have used as part of product development efforts. At the date of acquisition, technological feasibility of the technology had not been established and the technology had no alternative future use. Therefore, the $700,000 was assigned to in-process research and development assets and was expensed at the date of acquisition.
Note 8. Goodwill and Intangible Assets
The following summarizes our intangible assets as of December 31, 2004 (in thousands):
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
The following summarizes our actual and estimated amortization expense related to the above intangible assets (in thousands):
We recorded $1.3 million in goodwill during 2002 as a result of our acquisition of products and technology from IOTA. To date, we have not recognized any impairment losses on goodwill.
Note 9. Shareholders’ Equity
Common Stock
We reserved shares of common stock for issuance at December 31, 2004 as follows:
To date, we have sold a total of 1,560,668 shares of common stock to employees in connection with restricted stock purchase agreements. These agreements allow us to repurchase unvested shares in the event that the employee is no longer employed by us. In 2004, no shares were subject to repurchase. In 2003, 1,111 shares were subject to repurchase.
2000 Employee Stock Purchase Plan
In 2000, the Board of Directors adopted the 2000 Employee Stock Purchase Plan (the “Purchase Plan”). A total of 666,666 shares of our common stock were initially reserved for issuance under the Purchase Plan. The Purchase Plan permits eligible employees to purchase common stock at a discount up to a maximum of 12% of their compensation through payroll deductions during defined offering periods. The Purchase Plan is implemented in a series of overlapping 24 month offering periods, and each offering period consists of four six-month purchase periods. The price at which stock is purchased under the Purchase Plan is equal to 85% of the fair market value of the common stock on the first day of the offering period or the last day of the purchase period, whichever is lower. In addition, the Purchase Plan provides for annual increases in the number of shares available for issuance under the Purchase Plan on the first business day of each year, equal to the least of 666,666 shares, 2.0% of the outstanding shares of common stock on the last day of the prior fiscal year or such amount as may be determined by the Board. The Purchase Plan will terminate in April 2010.
During 2004, 2003 and 2002 we issued 357,974, 296,212 and 291,200 shares, respectively, of our common stock under the Purchase Plan.
Stock Options
As described below, we have two stock option plans (collectively, the “Option Plans”) under which incentive stock options and/or nonstatutory options may be granted to our employees, consultants and directors. Options are granted under the Option Plans at prices not less than the fair value on the date of the grant. Stock options to new employees generally vest and become exercisable in the amount of 25% of the total number of shares after one
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
year and on a ratable basis over the subsequent 36 months. The options generally expire in ten years. However, in the case of incentive stock options granted to an optionee who, at the time the option is granted, owns stock representing more than 10% of the voting power of any class of our stock, the term of the option is five years from the date of grant and the per share exercise price is 110% of the fair market value on the date of grant.
In 2000, our Board of Directors adopted the 2000 Stock Option Plan (the “2000 Plan”) and authorized an initial amount of 2,666,666 shares of common stock for grant under the 2000 Plan. The authorized shares available for issuance increase on the first business day of each year by the least of 2,333,333 shares, 5% of the outstanding shares of common stock on the last day of the prior fiscal year or such amount as may be determined by our Board. The 2000 Plan will terminate in April 2010.
In 2000, our Board of Directors adopted the 2000 Director Option Plan (the “Director Plan”) and authorized an initial amount of 100,000 shares of common stock for grant under the Director Plan. Each nonemployee director who does not own, or represent a party who owns, 1% or more of our outstanding common stock is automatically granted a nonstatutory stock option to purchase 40,000 shares of common stock on the date on which such person first becomes a director. At the first board meeting following each annual shareholders meeting, each nonemployee director then in office for over six months is automatically granted a nonstatutory option to purchase an additional 10,000 shares of common stock. The Director Plan will terminate in April 2010, unless terminated earlier in accordance with the provisions of the Director Plan. In addition, the Director Plan provides for annual increases in the number of shares available for issuance on the first business day of each year equal to the least of 100,000 shares, 0.15% of the outstanding shares of common stock on the last day of the prior fiscal year or such amount as may be determined by our Board.
A summary of option activity under the Option Plans follows:
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
The weighted average fair values at the grant-date of options granted during the three years ended December 31, 2004 were the following:
The following table summarizes information about all stock options outstanding at December 31, 2004:
Stock-Based Compensation
We have deferred stock-based compensation on pre-IPO stock option grants representing the difference between the exercise prices and the deemed fair value of our common stock on the dates these stock options were granted. Deferred stock-based compensation is being amortized by charges to operations on a graded vesting method over the vesting periods of the respective options, generally four years. We recorded amortization of deferred stock-based compensation of approximately $186,000, $443,000 and $542,000 for 2004, 2003 and 2002, respectively. We recorded reductions to deferred stock-based compensation of $1,000, $13,000 and $228,000 for 2004, 2003 and 2002, respectively, as a result of stock options that were canceled prior to vesting. The corresponding deferred stock compensation expense adjustment for the difference between the graded vesting method and the straight-line method for the cancellation of the unvested options was not significant for 2004, 2003 and 2002. At December 31, 2004, we had a total of $88,000 remaining to be amortized over the corresponding vesting period of the respective options. The remaining deferred stock-based compensation at December 31, 2004 is expected to be amortized as follows: $69,000 in 2005 and $19,000 in 2006. Subsequent terminations of option holders may reduce or cause a credit to future stock-based compensation.
Stock Repurchase Program
In May 2004, our Board of Directors authorized a stock repurchase program of up to one million shares of our common stock over a 12-month period. Shares are repurchased in the open market at times and prices we consider appropriate. The timing of purchases and the number of shares to be purchased depend on market conditions. In accordance with our insider trading policy, we are restricted from repurchasing shares when we are
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
in possession of material inside information and when our trading window closes. From May 2004 to December 31, 2004, we repurchased a total of 274,510 shares at an average price of $4.90. Repurchased shares of our common stock are no longer deemed outstanding.
In October 2001, our Board of Directors authorized a stock repurchase program of up to one million shares of our common stock over a 12-month period. In October 2002, our Board of Directors authorized an extension of this stock repurchase program until October 2003, which has since expired. Shares were repurchased in the open market at times and prices we considered appropriate. The timing of purchases and the exact number of shares to be purchased depended on market conditions. Repurchased shares of our common stock are no longer deemed outstanding. Under this program, we repurchased a total of 804,413 shares at an average price of $4.28 per share.
Note 10. Income Taxes
Income (loss) before income taxes consists of the following (in thousands):
The provision for income taxes differs from the amount computed by applying the statutory federal income tax rate to income (loss) before income taxes. The sources and tax effects of the differences are as follows (in thousands):
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
As of December 31, 2004, we had federal net operating loss carryforwards of approximately $7.6 million. We also had federal and state tax credit carryforwards of approximately $3.8 million and $4.1 million, respectively. The federal net operating loss carryforwards and tax credit carryforwards will expire beginning in 2012 if not utilized. The state tax credits carry forward indefinitely. Utilization of the net operating loss carryforwards and tax credit carryforwards may be subject to a substantial annual limitation due to the ownership change limitations provided by the Internal Revenue Code of 1986, as amended, and similar state provisions. The annual limitation may result in the expiration of net operating loss carryforwards and tax credit carryforwards before utilization.
Deferred income taxes reflect the net tax effects of temporary differences between the carrying amounts of assets for financial reporting and the amount used for income tax purposes. Significant components of deferred tax assets are as follows (in thousands):
As of December 31, 2004, we had deferred tax assets of approximately $10.7 million. We have evaluated the need for a valuation allowance for deferred tax assets in accordance with the requirements of Statement of Financial Accounting Standards No. 109. Based on the cumulative pre-tax losses we sustained in the three years ended December 31, 2004, a valuation allowance in an amount equal to our net deferred tax assets as of December 31, 2004 was recorded. The valuation allowance increased by approximately $1.2 million in 2004 from 2003 and decreased by approximately $7,000 in 2003 from 2002.
As of December 31, 2004, approximately $750,000 of the valuation allowance reflected above related to the tax benefits of stock option deductions, which will be credited to equity when realized.
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NOTES TO CONSOLIDATED FINANCIAL STATEMENTS-(Continued)
Note 11. Industry and Geographic Segment Information
The following table presents enterprise-wide sales to external customers and long-lived assets by geographic areas (in thousands):
Revenue by geographic area is based on the location of the customer.
Note 12. Employee Benefit Plan
We have a 401(k) Plan in which all United States employees who are age 21 or over are eligible to participate. Participants may defer up to 15% of their gross salary into the 401(k) Plan, subject to certain 401(k) Plan restrictions. We provide matching contributions of 50% of the first 4% contributed by the participants up to a maximum of $1,000 per employee per year, which totaled $146,000, $142,000 and $174,000 for 2004, 2003 and 2002, respectively.
SIGNATURES
Pursuant to the requirements of Section 13 or 15(d) of the Securities Exchange Act of 1934, the registrant has duly caused this report to be signed on its behalf by the undersigned, thereunto duly authorized.
SYNPLICITY, INC.
By:
/s/ GARY MEYERS
Gary Meyers
President and Chief Executive Officer
By:
/s/ DOUGLAS S. MILLER
Douglas S. Miller
Senior Vice President of Finance and Chief Financial Officer
Date: March 3, 2005
POWER OF ATTORNEY
KNOW ALL PERSONS BY THESE PRESENTS, that each person whose signature appears below constitutes and appoints Gary Meyers and Douglas S. Miller, his or her true and lawful attorney-in-fact and agent, with full power of substitution and resubstitution, to sign any and all amendments (including post-effective amendments) to this Annual Report on Form 10-K and to file the same, with all exhibits thereto and other documents in connection therewith, with the Securities and Exchange Commission, granting unto said attorney-in-fact and agent, full power and authority to do and perform each and every act and thing requisite and necessary to be done in connection therewith, as fully to all intents and purposes as he or she might or could do in person, hereby ratifying and confirming all that said attorney-in-fact and agent, or his or her substitute or substitutes, or any of them, shall do or cause to be done by virtue hereof.
Pursuant to the requirements of the Securities Exchange Act of 1934, as amended, this Report has been signed below by the following persons on behalf of the Registrant and in the capacities and on the dates indicated:
SCHEDULE II
VALUATION AND QUALIFYING ACCOUNTS AND RESERVES
(in thousands)
INDEX TO EXHIBITS
(1) Portions of the exhibit have been omitted pursuant to a request for confidential treatment and the omitted portions have been separately filed with the Commission.
(2) Filed as an exhibit to the Company’s Registration Statement on Form S-1 (File No. 333-42146) as declared effective by the Securities and Exchange Commission on October 12, 2000.
(3) Filed as an exhibit to the Company’s Annual Report on Form 10-K for the fiscal year ended December 31, 2000.
(4) Filed as an exhibit to the Company’s Annual Report on Form 10-K for the fiscal year ended December 31, 2001.
(5) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended September 30, 2002.
(6) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended March 31, 2003.
(7) Filed as an exhibit to the Company’s Annual Report on From 10-K for the fiscal year ended December 31, 2003.
(8) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended March 31, 2004.
(9) Filed as an exhibit to the Company’s Quarterly Report on Form 10-Q for the quarter ended June 30, 2004.
(10) Filed as an exhibit to the Company’s 8-K filed September 22, 2004.
(11) Filed as an exhibit to the Company’s 8-K filed October 4, 2004.
(12) Indicates a management contract or compensatory plan or arrangement.