Meh.  You realize that the capacity limit is just a limitation in the logical sector specification in the protocol, right?  The NVMe protocol uses a 64-bit field for the LBA... it's actually considerably more than 128TB, but if the marketing folks specified the full 16Exabytes allowed by the field then people wouldn't be fooled.  So... try to avoid being fooled next time.  1 GByte/sec sounds like a 1 or 2 lanes of PCIe... so its nice that they are improving the interface for the formfactor, but there's nothing special about it other than they finally improved the interface for the form factor (a few years late in my view).<br><br>This is more of a 'gee, they finally update the interface beyond 30+ year-old IDE/ATA protocols.  It only took them 30 years!<br><br>-Matt,(reply>), It's actually more.  It's 2^64 sectors @ 512 bytes each, so 16EB * 512 = 8192EB.  However, both firmware and operating systems usually convert back and forth between byte offsets and sectors and still use 64-bits, so the practical limit is 2^64 bytes rather than 2^64 sectors.  And some OS's use the 2s complement negative space for other purposes, so it's actually 0 ... 2^63-512 bytes... around 8 Exabytes.<br><br>In the old days (30+ years ago), every byte in the protocol mattered so the protocols simply did not use wide fields to store sector numbers.   IDE was horribly brain-damaged... there are half a dozen 'READ' and 'WRITE' commands each supporting a different width for the sector number as storage sizes continued to race ahead of what the protocols could accommodate.  SCSI had the same problem.   AHCI (chipset used to talk to SATA) stupidly inherited all the IDE protocol crap, even though by then everyone (except Intel) knew better.  But Intel was more interested in intentionally brain-damaging AHCI/SATA in order to differentiate it from the SAS protocol so they perpetuated some horrible hacks.   AHCI/SATA is braindamaged in so many ways it isn't even funny.<br><br>The NVMe chipset and protocol is a clean from-scratch implementation done by someone with some intelligence.  Even so, most of the NVMe controllers only use a small fraction of the protocol's capabilities.  For example, the protocol specs MSI-X and  up to 16384 queues, meaning that one can trivially create multiple queues and separate out reads, writes, and priority and give each one its own cpu and interrupt vector.  But Intel and most other NVMe chipsets usually only implement support for no more than 32 queues and 32 vectors.  One of those has to be reserved for administrative commands, so  the remaining odd numbers (31) doesn't even allow assigning a per-cpu queue cleanly on a 32-thread system.  A lot of chipsets only support 8.  Really annoying that they are penny pinching in this day and age.<br><br>NVMe is gobs better than AHCI/SATA, though.  By several orders of magnitude.  AHCI had only a single queue and really horrible chipset sequences and locking requirements that made is a sludgepile on multi-core systems.  NVMe is far better.<br><br>-Matt,(reply>), How the fuck do they know it's 16 Exabytes if there's limitation? <br><br>And Holy fuck that's a lot of gigabytes! lol