re decoupling caps onboard i ve used on chip capacitors to reduce ground bounce noise on a small systolic array chip that had pf loads on the clock lines design was in micron n well cmos using the mosis scalable design rules here are some thoughts on the bypass capacitors they don t help much with simultaneous output switching there is still a large inductance between the bypass capacitor and the load capacitor on both the signal line and the ground return so you still get ground and power line bounce they do help a lot with on chip loads as i had with the high load on the clock lines the transients you are trying to suppress are really high frequency so forget about large areas of poly thin oxide diff capacitors since the rc time constant is too large what i did is to make a metal metal poly diff sandwich but put a lot of holes in the poly layer allowing frequent diff metal contacts i forget exactly how wide the poly lines were if i were doing this design again i d probably omit the diff altogether and use a solid poly sheet instead using just m m and poly and substrate but that has such a high resistance it can be ignored at these speeds you are probably better off trying to tune your circuit to run with slightly slower edges and lower voltage swings especially for output signalling than spending chip area on capacitors i had spare space on the die since the circuit was too big for a mosis tiny chip and the next size up was twice as big as i needed kevin karplus kevin karplus karplus ce ucsc edu due to budgetary constraints the light at the end of the tunnel is being turned off
