re help mc a real time clock standby mode in article r b inn ct flash pax tpa com au mgregory flash pax tpa com au martin john gregory writes i am having trouble obtaining the specified standby current drain from a mc a real time clock lowest current drain i can acheive at v vcc is ua this is three times the specified maximum made sure that reset is asserted for trlh after powerup and as is low during this time made sure that there is a cycle on as after the negation of rd or wr during which stby was asserted are any of the inputs to the chip coming from ttl standby drain specs for cmos chips typically apply only if inputs are pulled all the way down to zero or all the way up to vcc ttl isn t good at doing the former and it won t do the latter at all without help from pullup resistors this sort of thing can easily multiply power consumption by a considerable factor because the cmos transistors that are supposed to be off aren t all the way hard off all work is one man s work henry spencer u of toronto zoology kipling henry zoo toronto edu utzoo henry
