re uart needed really break detect in article alan alan apple com alan mimms writes actually detecting a break is done by watching for a character containing all zero bits with the framing error resulting from its receipt this true enough but means that the line stayed in the zero bit state even past the stop bit time slot which basically indicates a break there is no special way to detect break that i have found other than this there s no magic signal generated by uarts etc zilog scc rr break detect this is a very popular part but it has a number of quirks especially in hdlc mode signetics duscc rsr break start detect rsr break end detect two of the bits in the receiver status register you can enable an interrupt on either of these bits going high too also only one null will be put in the fifo per break detected this is simply the best serial chip i ve ever worked with many less quirks than the scc which is imho second best death to devices ii cccccc jim cathey ii sssscc isc bunker ramo ii cc taf c spokane wa iissss cc uucp uunet isc br jimc jimc isc br isc br com ii cccccc one design to rule them all one design to find them one design to bring them all and in the darkness bind them in the land of mediocrity where the pc s lie
