In 3D thin-film batteries (3D-TFBs) and in trenched capacitors, the surface area is increased by forming holes in a substrate such as a silicon wafer. In this paper we define area gain (AG) as a ratio of the total new surface area (including the surface areas of all the holes) to the original surface area of the substrate (“footprint”). We analyze the AG for different configurations of convex polygonal holes within the substrate. In most cases, the AG can be computed based on the P/S ratio, where P is the sum of all hole perimeters and S is the surface area of one side of the substrate. Assuming that the diameter of each hole is not less than D and that the distance between any two holes is not less than s, the P/S ratio never exceeds 4/(D +2s). Tesselation of the surface into a regular grid of polygonal cells of diameter D + s with regular polygonal holes of the same form (of diameter D) results in P/S =4D/(D + s)2. We propose two alternative tessellations (one with regular square holes and another with regular triangular holes) which have P/S ratios slightly better than 4D/(D + s)2 and which satisfy the assumptions of the hole diameter and the wall width. It is found that a smoothed triangular tessellation provides the largest AG.