Energy saving power amplifier design methodologies are gaining increasing momentum in the exponential growth of wireless communications due to the demand of high data rates. The demand in high data rates bottlenecks linear transmission specifications for the power amplifier, thus mandates the device to drain more battery energy. In other words, the efficiency of the PA degrades significantly. The improvement in PA׳s overall efficiency is possible with the innovation of various circuit topology, which has paved the path to reduce the overall battery energy consumption. In this paper, these techniques are reviewed, explicitly. Also reviewed are recent reported works which attempts low voltage headroom implementation in complementing the reduction of battery energy consumption and design cost through the use of Complementary Metal Oxide Semiconductor (CMOS) process.