Publisher Summary This chapter provides an overview of techniques for designing communication architectures for high-performance, energy-efficient systems-on-chips. It describes the techniques for fast and accurate system-level performance/power analysis to drive communication architecture design, and automatic techniques for customizing the communication architecture to the characteristics of an application's communication traffic, through both static customization and dynamic customization. It also describes a system power management methodology called communication-based power management (CBPM) that utilizes new, battery-aware on-chip communication protocols to enhance the overall battery efficiency of a system. The growing importance of on-chip communication adds a new facet to the process of system design. Under the traditional notion of system design, a system's functional requirements are refined and mapped onto a well-optimized set of computational resources and storage elements. Today, system designers pay more attention to the relatively less understood process of mapping a system's communication requirements onto a well-optimized on-chip communication architecture.