Motion estimation (ME) is crucial to the performance of a video codec as it recognizes and mitigates temporal redundancies between consecutive frames of a video sequence. It is one of the most computationally intensive blocks in the video encoder. Block matching algorithm (BMA) is considered as one of the best approaches for performing ME due to its ease of implementation and efficiency. Several ME algorithms are based on fixed search patterns while the others are adaptive in nature and exploit the correlation present between neighboring macroblocks of a video frame. This paper introduces an efficient ME algorithm named Hexagon Based Compressed Diamond Algorithm (HCDA) that tries to reduce the complexity of ME by lowering the number of search points in the process. The algorithm uses an early termination technique and an adaptive search pattern that can uniformly deal with slow and fast motion content in a video. The proposed HCDA uses dual threshold technique based on the available spatial information. This further helps in terms of clock cycles or hardware resources during VLSI implementation. Moreover, VLSI design for HCDA can explore the adaptive nature of the algorithm and the adopted search methodology is handled by interleaved memory organization that enhances the operational speed. Supportive data re-use scheme with effective block for SAD computation contributes to a fair trade-off between speed and on-chip area. The designs can work at a maximum frequency of 262 MHz to process 76 HD (1280 × 720) frames per second. The corresponding gate count comes out to be 35.8 K gate equivalent. The encouraging experimental results obtained under various defined metrics indicate suitability of the proposed hardware architecture for its inclusions in portable battery powered consumer video devices.