Publisher Summary This chapter presents a discussion on physical network layer. The chapter describes physical design issues for networks on chips (NoCs). A major design problem in NoCs is the interconnect realization that requires modeling and performance metrics—such as the signal integrity and noise immunity. High-speed signaling—such as current-mode signaling and wave-pipelining—and low-power interconnection designs—such as low-swing signaling and transition-reducing coding—are widely used within the NoC physical layer. The chapter analyzes the clock and data synchronizing methods as well as the physical design issues of NoC building blocks such as switches, buffeting memories, and SERDES. Although a new design approach such as NoC is required to get a more process independent interconnection architecture, still more emphasis is put on the physical design of interconnection and more detail understanding of the physics in the interconnect of deep submicron (DSM) technology is required than before. Four factors are referred to cause new challenges in DSM: (1) increase of the operation frequency so that the inductance characteristics are more conspicuous than before, (2) signal reflection and transmission because of impedance mismatch, (3) increase of fringe capacitance because of increased aspect ratio of the interconnection wire, and (4) increase of resistance with sheet resistance because of skin effect of high frequency and contact resistance.