Title: RISC-V&#x27;s compressed instruction (RVC) extension is intended as an add-on to the regular, 32-bit instruction set, not a replacement or competitor. Its designers intended RVC instructions to be expanded into regular 32-bit RV32I equivalents via a pre-decoder.<p>What happens if we explicitly architect a RISC-V CPU to execute RVC instructions, and &quot;mop up&quot; any RV32I instructions that aren&#x27;t convenient via a microcode layer? What architectural optimizations are unlocked as a result?<p>&quot;Minimax&quot; is an experimental RISC-V implementation intended to establish if an RVC-optimized CPU is, in practice, any simpler than an ordinary RV32I core with pre-decoder. While it passes a modest test suite, you should not use it without caution. (There are a large number of excellent, open source, &quot;little&quot; RISC-V implementations you should probably use reach for first.)
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