This week's book giveaway is in the General Computing forum.
We're giving away four copies of Arduino in Action and have
Martin Evans, Joshua Noble, and Jordan Hochenbaum on-line! See
this thread for details. Two processors, M-5 and M-7, implement
the same instruction set. Processor M-5 uses a 5-stage pipeline
and a clock cycle of 10 nanoseconds. Processor M-7 uses a
7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of
the following is (are) true? I. M-7�s pipeline has better
maximum throughput than M-5�s pipeline. II. The latency of a
single instruction is shorter on M-7�s pipeline than on M-5�s
pipeline. III. Programs executing on M-7 will always run faster
than programs executing on M-5. (A) I only (B) II only (C) I and
III only (D) II and III only (E) I, II, and III Originally
posted by Pat Farrell: (..snip..)I don't see how to answer the
other two, it depends on how many stalls you get. Yep, it's L-2
misses and so on. Great deal of cut and try here. If this is an
exam question, then I am not w