Cart is empty Highly Energy-efficient CMOS Logic Systems
Developments in low power, high performance CMOS logic
technology are vital to the future of microprocessors and
system-on-Chip (SoC) devices for personal computers, servers,
and mobile/smart phones. Much of the processing in these
computing systems is carried out using a volatile hierarchical
memory system in which bistable circuits such as static random
access memory (SRAM) and flip-flop (FF) play an essential role
for fast data-access. However, the power to these bistable
circuits cannot be switched off without losing their data. This
inability to turn off power is a fundamental problem for energy
consumption in CMOS logic systems. The method for saving energy
in CMOS logic systems, called power-gating, uses architecture to
cut the supply voltage to idle circuit domains, effectively
putting them to power shut-off state to avoid leakage and
thereby save static energy. Satoshi Sugahara and his team at the
Tokyo Institute of Technology have proposed a n