In this lecture we will describe a different implementation
style. We will use the term bus-based implementation. We will
first describe the datapath and then provide RTL (register
transfer language) for some of the control states. This is a
multi-cycle implementation. The key difference is that we do not
design a datapath with point-to-point connections amongst the
various units. Instead we assume a common bus and connect all
inputs and outputs of all units to that bus. We are going to use
the same building blocks (e.g., Register File and ALU). The
following figure shows for example how the PC will be connected
to the common bus: As you see in the figure, the PC input is
directly connected to the common bus and the PC’s output is also
connected to the common bus via a tri-state buffer. The PCout
signal controls the tri-state buffer. If PCout is 0, the PC does
not place a value on the bus. If PCout is 1, the PC places its
value on the bus. All outputs will be connected in this manner
with the common bus. At a