Power is a daunting challenge for modern system-on-chip (SoC)
designs, from both the power consumption and power integrity
perspectives. Achieving low-power, from mobile and wireless
designs to consumer devices to high-performance networking and
computing applications that face power supply and cooling
limitations, is now critical to design success. At the same
time, rising complexity and chip-level power management
techniques make power integrity analysis from chip-to-package-
to-system essential. Designing for low-power and power integrity
is not automatic – there is no “low-power” button. This article
describes a holistic design for power methodology that spans
from architectural decisions through front-end design to
physical implementation and sign-off. Power is a key challenge
in modern IC designs for various applications. The power
challenge is comprised of two fundamental aspects: power
consumption and power integrity. From mobile and wireless
designs where extending battery life is essential to product