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Overstress (EOS) and Electrostatic Discharge (ESD) account for
most of the electrical failures of devices that occur in
factories and in the field. The effects of ESD on integrated
circuits have received much attention in technical literature,
standards bodies and educational workshops and tutorials. The
problem has been approached in a systematic manner which has
resulted in relatively successful practices for design of robust
devices and control procedures for the factory. However, the
same cannot be said for the effects of the broader categories of
electrical stresses generally referred to as electrical
overstress (EOS). This disparity is reflected in the typical
Pareto analysis of failures in electrical assembly where EOS is
often the most commonly assigned cause of failure and may exceed
the incidence of ESD by 10 ti