The challenge of controlling signal integrity is ever present in
designs that operate at speeds over 30-40 MHz. The signal
integrity design process includes technology characterization up
front, which is necessary to develop noise budgets, layout rules
and circuit models. After the board is routed it must be
verified to ensure that all nets are free of excessive noise.
Identifying problem nets is only a part of the engineering
problem. These problems must be fixed in the design before a
board is built to prevent the design from being riddled with
intermittent failures. The following problems are related to
signal integrity: * Logic Hazards - occur when an input
transition causes a glitch at the output of a combinational
logic circuit. In general, circuits feeding pulse sensitive
inputs (clock, enables, resets, and clears) should be designed
to be free of logic hazard. * Timing Violations - a setup time
(the time data must stabilize before clock) or hold time (the
time data must remain after clock) violation o