US 6874077 B2 In a computer system, a parallel, distributed
function lookaside buffer (TLB) includes a small, fast TLB and a
second larger, but slower TLB. The two TLBs operate in parallel,
with the small TLB receiving integer load data and the large TLB
receiving other virtual address information. By distributing
functions, such as load and store instructions, and integer and
floating point instructions, between the two TLBs, the small TLB
can operate with a low latency and avoid thrashing and similar
problems while the larger TLB provides high bandwidth for memory
intensive operations. This mechanism also provides a parallel
store update and invalidation mechanism which is particularly
useful for prevalidated cache tag designs. 1. A method for
translating virtual address information in a computer system,
comprising: accessing a first translation lookaside buffer (TLB)
by a first memory port and a second memory port; accessing a
second TLD by the first and the second memory ports, and by a
third memory port