Tuesday May 11, 2004 Hamerschlag Hall D-210 With each technology
generation, we are experiencing an increased rate of cosmically-
induced soft errors in our chips. In the past, the impact of
such errors could be minimized through protection of large
memory structures. Unfortunately, such techniques alone are
becoming insufficient to maintain adequately low error rates.
Although, to a very rough approximation, the fault rate per
transistor is not changing much, the increasing number of
transistors is resulting in an ever increasing raw rate of bit
upsets. Thus, we are starting to see a dark side to Moore's Law
in which the increased functionality we get with our
exponentially increasing number of transistors is being
countered with a exponentially increasing soft error rate. This
will take increasing effort and cost to cope with. In this talk
I will describe the severity of the soft error problem as well
as techniques to estimate a processor's soft error rate. These
estimates should help designers choose approp