|United States Patent||4,766,566| |Chuang||August 23, 1988|
Performance of a VLSI processor of the reduced instruction set
computer (RISC) type is enhanced by executing two instructions
simultaneously in the two execution units of the processor.
There is very little increase in the cost of hardware. Three
embodiments are presented with different cost and performance
capabilities. The first embodiment has an instruction input to
an instruction buffer (10) and two sets of control ROSs (40 and
42) and control registers (64 and 65). The control ROS and
control register which is chosen depends on which instruction
execution unit is to execute the instruction. Data inputs to the
execution units is from a register file (48) which has an
additional pair of outputs (51) and (53) that provide the data
paths for simultaneous execution of instructions by the
execution units. Execution unit I has an arithmetic and logic
unit (ALU) (24), while execution unit II has a rotate (26) and
mask generator (31). Load balancing betw