Process Lots (or corner lots) are special-modified-wafers that
help verifying chip design robustness to accommodate process
variations that statistically occur in wafer production over the
years. One of the products that semiconductor foundries offer is
process lots (also called: corner lots, split lots or skewed
lots). Corner lots wafers are a group of wafers which have been
skewed by the fab to different corners. The purpose of process
lots is to help you find out whether your design will be immune
to process variations in the future. A successful corner lot
exercise includes production of process lots in all different
corners. Thereafter these wafers need to pass the electrical
test (by the ATE) at all corners. The industry is using two-
letter designation to describe the different corners, where the
first letter refers to the NMOS device, and the second refers to
the PMOS device. There are 5 classic corners: - FF (fast fast) -
SF (slow fast) - SS (slow slow) - FS (fast slow) - TT (typical
typical) The FF c