Clock gating is one of the most frequently used techniques in
RTL to reduce dynamic power consumption without affecting the
functionality of the design. One method involves inserting
gating conditions in the RTL, which the synthesis tool
translates to clock gating cells in the clock-path of a register
bank. This helps to reduce the switching activity on the clock
network, thereby reducing dynamic power consumption in the
design. Since the translation done by the synthesis tool is
purely combinational, it is referred to as combinational clock
gating. This transformation does not alter the behavior of the
register being gated. In the example shown in Figure 1, the
netlist generated by the RTL synthesis tool from the Verilog
code snippet is shown at the top right. Register Q loads new
data when the EN signal is HIGH; otherwise, it holds the data.
Opportunities to insert combinational clock gating can be found
by looking for conditional assignments in the code. Clock gating
logic is substituted when code like if