The need to move cache management to hardware In the old days,
cache coherency management was largely done in software,
invalidating large parts of the cache to ensure no stale data
could get accessed, and forcing the cache to gradually be
reloaded from main memory. There are several reasons why this is
no longer appropriate. Caches have got very large and the
penalty for off-chip access back to main memory is enormous. A
large amount of data flowing through a slow interface is bad
news for system performance, and off chip memory accesses have a
big negative impact on power. Caches now require more
intelligence. Instead of invalidating lots of data that might
turn out to be stale, the cache controllers need to invalidate
on a line-by-line basis in order to ensure that anybody reading
an address gets the latest value written. This even needs to be
extended to devices that don't even have caches since a DMA
device cannot simply go to the main memory due to delayed write-
back. Verifying the AMBA4 protocol with J