Pipelining is a technique you can use to increase the throughput
of the FPGA VI. In a pipelined design, you take advantage of the
parallel processing capabilities of the FPGA to increase the
efficiency of sequential code. To implement a pipeline, you must
divide code into discrete steps and wire the inputs and outputs
of each step to Feedback Nodes or shift registers in a loop. In
the following block diagram, subVIs A, B, and C execute in
sequence within a single-cycle Timed Loop. As a result, the
clock rate of the single-cycle Timed Loop must be set to
accommodate the sum of the running times of all three running
subVIs. When you wire the inputs and outputs of the subVIs to
Feedback Nodes, as shown in the following block diagram, LabVIEW
pipelines the subVIs. Now, the subVIs execute in parallel, all
within a single cycle, and the maximum clock rate is limited
only by the subVI with the longest combinatorial path. By
implementing a pipelined design, you might be able to increase
the clock rate of the single-c