| Deep submicron technology enabled the design of the industry's
first very large chips. The magnitude of the design effort
involved in creating these chips led to the adoption of reuse
methodologies and system-on-chip (SoC) design, in which various
intellectual property (IP) components were created and reused to
produce even larger, more complex chips. This led to the
emergence of design flows and methods for handling IP protection
and hierarchy, and ultimately SoC test. | To enable SoC test,
two technologies emerged: As the industry matures in the usage
of these technologies, hierarchical SoC test flows have begun to
emerge, and the benefits of having an SoC test methodology are
being recognized. - Wrapper technology, in which a wrapper
isolates the core from the embedded environment during test,
such that the core can be tested independently from the logic in
which it is embedded. - Core Test Language (CTL), which
communicates test information for the core and allows for the
successful creation of a comple