The contentious issue of gate-first or gate-last in front-end of
line (FEOL) chip manufacturing is raising its ugly head again;
but this time in with regard to the fully-depleted silicon on
insulator (FDSOI) process. Some readers may remember that gate-
first high-k metal gate technology was developed and touted by
IBM's circle of chip manufacturing partners for the 32/28-nm
bulk CMOS node. This was a contrast to the gate-last position
taken by Intel, which of course went on to introduce the FinFET
or tri-gate transistor at nominal 28-nm and 22-nm nodes. But
IBM's bulk CMOS technology partners revealed that having gone
gate-first at 28-nm they would move to gate-last at the 20-nm
node. Professor Asen Asenov, of Glasgow University and CEO of
TCAD company Gold Standard Simulations Ltd. (GSS), has used its
TCAD simulator to investigate the statistical variability in
32/28-nm FDSOI in comparison to equivalent bulk MOSFETs and
studied the difference between metal-gate-first and metal-gate-
last flavors of the techno