Low power is a central concern of digital design, especially for
handheld and wireless devices, but also for servers and other
computation intensive applications where the cost of cooling and
packaging can be quite high. As a consequence, power
optimization is an essential factor in meeting and improving
quality of results as well as for optimizing performance and
area. Thus far, power optimization efforts have centered on RTL
models and gate-level netlists, which are not sufficient for
achieving optimal power savings. Optimizing for power should
occur at all levels of design—from architecture to board. It is
at the architecture, or electronic system level (ESL), where the
potential for power savings are the greatest. Indeed, the
opportunities for optimizing low power are significantly higher
at the architectural level of abstraction—with as much as a 10X
improvement over gate level optimizations. Yet, ironically, this
is where low power methodologies and tools are the weakest. This
deficiency drives the need