All procedures in the Verilog HDL are specified within one of
the following four statements: -- initial construct -- always
construct The initial and always constructs are enabled at the
beginning of a simulation. The initial construct shall execute
only once and its activity shall cease when the statement has
finished. In contrast, the always construct shall execute
repeatedly. Its activity shall cease only when the simulation is
terminated. There shall be no implied order of execution between
initial and always constructs. The initial constructs need not
be scheduled and executed before the always constructs. There
shall be no limit to the number of initial and always constructs
that can be defined in a module An initial block consists of a
statement or a group of statements enclosed in begin... end or a
signle statement , which will be executed only once at
simulation time 0. If there is more than one block they execute
concurrently and independently. The initial block is normally
used for initialisation,