An Energy Aware Bit Serial Streaming Deep Convolutional Neural Network Accelerator
Over the past decade, deep convolutional neural networks (CNN) have been widely embraced in various visual recognition applications owing to their extraordinary accuracy. However, their high computational complexity and excessive data storage present two challenges when designing CNN hardware. We propose an energy aware bit serial streaming deep CNN accelerator to tackle these challenges. With several optimization methods and the proposed ring streaming dataflow, the computational performance is improved and the external memory access is reduced. We evaluate our design with the roofline model by exploring the design space to find the best performance and computation and communication (CTC) ratio solution. We can reach 1.36x speed up and reduce energy consumption by 41% for external memory access compared with the design in [1] The hardware implementation for our PE Array architecture design can reach the operating frequency of 119 MHz and consumes 68 k gates with a power consumption of 10.08mW using TSMC 90 nm technology.
2019 IEEE International Conference on Image Processing (ICIP)