VLSI Implementation of a Digitally Tunable Gm C Filter with Double CMOS Pair
This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of Gm C filters The advantage of this scheme is that, instead of varying the power supply, the bias voltages at high impedance nodes are varied for frequency (F) tuning. A current steering DAC is proposed for controlling these bias voltages. Another major contribution of this paper is the use of switchable transconductance cell for Q tuning. This dispenses with the need for two separate biasing circuits (for F and Q tuning) To study the performance of proposed schemes, a bandpass filter is implemented on TSMC 0.18 mum CMOS process using Gm/Id design methodology. The simulation results show a good centre frequency (10 MHz 120 MHz) and pass band (10MH 80MHz) tuning. The proposed approach guarantees the upper bound on THD to be 40 dB for 1 Vw signal swing. The use of inverters with double CMOS pair results in 21 dB higher PSRR compared to those using push pull inverter.
21st International Conference on VLSI Design (VLSID 2008)