GraphS: A Graph Processing Accelerator Leveraging SOT MRAM
In this work, we present GraphS architecture, which transforms current Spin Orbit Torque Magnetic Random Access Memory (SOT MRAM) to massively parallel computational units capable of accelerating graph processing applications. GraphS can be leveraged to greatly reduce energy consumption dealing with underlying adjacency matrix computations, eliminating unnecessary off chip accesses and providing ultra high internal bandwidth. The device to architecture co simulation for three social network data sets indicate roughly 3.6x higher energy efficiency and 5.3x speed up over recent ReRAM crossbar. It achieves ~4x higher energy efficiency and 5.1x speed up over recent processing in DRAM acceleration methods.
2019 Design, Automation Test in Europe Conference Exhibition (DATE)