Design and failure analysis of logic compatible multilevel gain cell based dram for fault tolerant VLSI systems
This paper considers the problem of increasing the storage density in fault tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area efficient and fully logic compatible gain cell based dynamic memories. A memory macro in 90 nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within die process variations by means of Monte Carlo simulations.
GLSVLSI '11