DesignCon 2009 Performance Calibration of High Speed Serial Links
We present an empirical method of evaluating high speed serial link systems. Test cards implementing several hundred variations of the channel types expected in the real system are built; these channels are excited by the SerDes transceivers under consideration or an earlier version of the same. Performance is measured in terms of an available metric that is sufficiently dependent on the measure of interest; the available metric is empirically correlated with the measure of interest using calibration data. Link performance is parameterized against all variables of interest, and statistical analyses of performance and transceiver state matrices versus these variables are used to evaluate the solution at the system level. Author(s) Biography Bilal Ahmad obtained his Bachelors degree from the University of Engineering Technology Lahore in 1991, and his Masters and Doctorate degrees from Stanford University California in 1993 and 1999, respectively. During his professional career he has worked as software engineer for the Jet Propulsion Laboratories, as research associate for Stanford University, as visiting faculty for the Center for Advanced Studies in Engineering Islamabad, and as founder and entrepreneur in a privately funded effort to develop EDA tools for high speed serial interfaces. At present he works as signal integrity lead for Cisco Systems Canada Co. a company he has worked for over 7years. Jayanthi Natarajan obtained her B.E. from Bharathiyar University, India, in 1996, majoring in Electronics and Communication Engineering. At present, she works for Cisco Systems, Inc. in San Jose. Current responsibilities include performing signal integrity and power integrity analyses for Catalyst products. Eric Tran received both his B.S.E.E. and M.S.E.E. from the University of Washington, Seattle, Washington in 2005 and 2007, respectively. He majored in Analog Devices as an undergraduate and transitioned to Microwave for graduate school. Eric is currently working for Cisco Systems, Inc. in San Jose where he is tasked with providing signal integrity evaluation and analyses for high speed links used on communication systems. Before joining Cisco he worked for Sensors, Energy, and Automation Laboratory to investigate use of electrostatic discharge to propel, filter, sanitize, and dehumidify air. Introduction A general framework for modeling and analysis of high speed serial links was presented by Ahmad and Cain [2001] which was later extended by Casper et al. [2002] and Ahmad [2003] utilizing an accurate statistical determination of proportional interference. Accurate modeling of SerDes communication links at 5Gbps and above remains a considerable challenge, however, because of the complexity of the problem and because of the level of accuracy desired. When a system is being designed anew or an existing system is being upgraded signal integrity engineers responsible for long reach SerDes links operating across multiple boards and connectors usually rely on industry specifications to ensure that the channels and the transceivers both meet their part of the specifications. This approach can be problematic for several reasons: (1) The specifications may not be complete, that is, the components put together will not necessarily operate as desired even if they are individually compliant to their parts of the specifications; (2) the channels of a particular chassis or system may not comply with the specifications; (3) certain procedures involved in compliance testing are complicated and are not fully appreciated which makes this task often difficult to complete; (4) accurate transceiver models are not available; etc. In this paper we present an empirical method which is accurate and effective for evaluation of high speed serial links at the system level. The experimental setup consists of test boards that implement several hundred variations of the channel types expected in the real system. These channels are excited by the actual transceivers under consideration, or an earlier version of the same. Controlled distortion is used to induce errors at the receiver side, and this provides an estimate of the noise margin. Additionally, or alternatively, one may use other measures of performance that are now commonly available from transceivers of this class, such as the eye margin. Using trends, averages, and spreads this performance metric is correlated with physical attributes of the channel design, such as channel length, routing layer, connector row, etc. The measured performance metric such as the one obtained from controlled distortion must eventually be related to the performance measure of interest, which is usually the probability of achieving a certain bit error rate (BER) The data that describes this relationship are called calibration data. Such data may be parameterized, for example, by certain broad measure of the quality of channels comprising the system (e.g. FR4 or Megtron6 dielectric) or by the class of equalization employed by the transceivers (e.g. decision feedback or linear equalization) or by the environmental conditions (e.g. low or high temperature corner) etc. A joint assessment of the performance and calibration data allows one to evaluate and compare different transceivers, various system design choices, and the effects of manufacturing and environmental variations. Furthermore, an assessment of the space spanned by the transceiver state parameters when operating across the set of channels comprising the system under consideration may allow one to project for performance in another system whose channels are qualitatively and quantitatively different. Figure 1: Components of a serial link channel: transmitter chip foot print vias, first transmission line segment (TLS1) transmitter card connector foot print vias, connector connecting TLS1 and TLS2, backplane connector foot print vias, second transmission line segment (TLS2) backplane connector footprint vias, connector connecting TLS2 and TLS3, receiver card connector footprint vias, third transmission line segment (TLS3) dc blocking capacitor vias, dc blocking capacitor macro including pads, short microstrip transmission line segments and the capacitors, dc blocking capacitor vias, fourth transmission line segment (TLS4) receiver chip foot print vias It is not uncommon for a modern modular router or switch to have on the order of a thousand high speed serial link channels traversing the back plane. These channels differ from one another considerably in their ability to support communication at a certain rate; these differences stem from the various design choices of connectors, via pad stacks, transmission line geometries, lengths of various transmission line segments, etc. A given transceiver will perform with varying degrees of success on each of these channels which may also exhibit significant manufacturing and environmental variations. The total number of channel models characterizing fully the design, manufacturing, and environmental variations can easily run into the tens of thousands. Furthermore, if we are to combine channel variations with PVT variations in the transceivers, the problem size becomes truly daunting, and it is not feasible to evaluate system level performance using link level simulations on such a large scale. Symbol Description Environment 1 l length of TLS1 transmitter card 2 l length of TLS2 back plane 3 l length of TLS3 receiver card 4 l length of TLS4 receiver card 1 l routing layer for TLS1 transmitter card 2 l routing layer for TLS2 back plane 3 l routing layer for TLS3 receiver card 4 l routing layer for TLS4 receiver card 12 x connector row connecting TLS1 TLS2 connector 23 x connector row connecting TLS2 TLS3 connector Table 1: List of channel design parameters corresponding to the topology of Figure 1. Using the modeling framework of Ahmad and Cain [2001] and Ahmad [2003] along with accurate transceiver models we are able to perform link level simulations to predict performance. But link performance is dependent on channel and transceiver parameters in a complex and correlated manner, therefore, it is not advisable to select 10 or 20 channels from a system, perform link level simulations on each, and consider this set of simulations to encompass all variations expected across the system. Such a strategy might work when margins are substantial, but for forward looking designs this is rarely the case. One approach towards solving this problem is to generate parameterized channel models where design, manufacturing, and environmental variations can be captured. We have used this approach a few times for certain types of problems, and although it is a powerful method it presents two main difficulties: (1) Generating parameterized models that are a reasonable match to the actual channels is a challenging task that requires significant time and effort; and (2) since link level simulations utilizing actual transceiver models are compute intensive only canonical simulations utilizing reference transceiver models can be performed. Example Let us consider the set of high speed serial link channels that traverse the back plane of a modular networking chassis. These links have a common topology illustrated in Figure 1. The dc blocking capacitors are always placed on the top layer and in a consistent manner using a macro model, therefore this part of the link geometry is not a design variation. Via pad stacks and counter boring are controlled consistently so that specification of the routing layer for the adjoining transmission line segment constrains also the via design. Table 1 lists the channel design parameters for this example. Symbol Description Environment Control 0 a FIR center tap transmitter tunable 1 a FIR pre cursor tap transmitter tunable 1 a FIR post cursor tap transmitter tunable 1 b 1 st DFE tap receiver adaptive 2 b 2 nd DFE tap receiver adaptive 3 b 3 rd DFE tap receiver adaptive 4 b 4