HCI reliability control in HV PMOS transistors: Conventional EDMOS vs. Dielectric RESURF and lateral field plates
This paper demonstrates that degradation mechanisms can be controlled by electric field tuning with Dielectric RESURF (STI Shallow Trench Isolation interleaves in the drain extension) and lateral field plates (gate fingers on top of the STI regions) Transistors, rated for max. Vds=5.5 and 20 V, show on resistance (Ron) of 6.5 and 40 mmm2 respectively (comparable with optimized devices [1, 2] and 10 years Hot Carrier Injection (HCI) lifetime in 65 nm CMOS technology.
2009 21st International Symposium on Power Semiconductor Devices IC's