The Optimization Scheme Of The Leakage Current Reduction Technique For SRAM Design
An optimization scheme of the leakage current reduction (LCR) for SRAM design has been proposed in this letter. By choosing the enabling signals for the LCR circuits intentionally, it can be deduced theoretically that there exists an optimal design option for the LCR technique application under the premise of SRAM performance re quirement. Assuming that the reliably of SA sense requires 100mV differential voltage of bitlines, and the number of bitcells attached to one bitline is 2048, the simulate results shows that the discharging rate under the value of 256 of k is the fastest which is conform to the theoretical calculation, which means the most significant reduction of leakage current. Keywords component; SRAM; Leakage current reduction (LCR) Optimization