Increasing feasibility of the field programmable gate array implementation of an iterative image registration using a kernel warping algorithm
Abstract. Image registration is a fundamental image processing technique. It is used to spatially align two or more images that have been captured at different times, from different sensors, or from different viewpoints. There have been many algorithms proposed for this task. The most common of these being the well known Lucas Kanade (LK) and Horn Schunck approaches. However, the main limitation of these approaches is the computational complexity required to implement the large number of iterations necessary for successful alignment of the images. Previously, a multi pass image interpolation algorithm (MP I2A) was developed to considerably reduce the number of iterations required for successful registration compared with the LK algorithm. This paper develops a kernel warping algorithm (KWA) a modified version of the MP I2A, which requires fewer iterations to successfully register two images and less memory space for the field programmable gate array (FPGA) implementation than the MP I2A. These reductions increase feasibility of the implementation of the proposed algorithm on FPGAs with very limited memory space and other hardware resources. A two FPGA system rather than single FPGA system is successfully developed to implement the KWA in order to compensate insufficiency of hardware resources supported by one FPGA, and increase parallel processing ability and scalability of the system.
J. Electronic Imaging