Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment
Neural networks utilizing non volatile random access memory (NVM) exhibit excellent power reduction over traditional CMOS implementations. RRAM (resistive random access memory) is one such emerging memory technology offering low energy, good endurance, and a large analog conductance window. When implemented in a crossbar architecture, these networks are able to bypass the von Neumann bottleneck by performing compute in memory. This architecture works well for inference; however, training the network is far more challenging. Networks built using RRAM can be trained on chip with gradient descent or off chip where weights are transferred. Backpropagation, while effective in training von Neumann architectures, is inefficient when memory and compute are partitioned together. Commonly referred to as the weight transport problem, each neuron's dependence on the weights and errors located deeper in the network requires reading the weights in each layer before computing and applying the error. This presents a key challenge in performing efficient on chip training for non von Neumann architectures. In this work we demonstrate an alternative to backpropagation called sparse direct feedback alignment which bypasses the weight transport problem. We simulate crossbars of HfOx RRAM based on experimental data to explore the performance, area, and energy trade offs of using bio plausible algorithms on the MNIST and EMNIST datasets.
2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)