Low Power Process Variation Tolerant Schmitt Trigger Based SRAM
Aggressive scaling of transistor dimensions with each technology generation has resulted in increased integration density and improved device performance at the expense of increased leakage current. Supply voltage scaling is an effective way of reducing dynamic as well as leakage power consumption. However the sensitivity of the circuit parameters increases with reduction of the supply voltage. SRAM bitcells utilizing minimum sized transistors are susceptible to various random process variations. Hence reducing the memory operating supply voltage, while maintaining the yield is becoming extremely challenging in nano scale technologies. This paper presents solution for high power dissipation of SRAM by reducing the leakage current and increasing the Stability compared with Basic 6T SRAM. In this paper the Schmitt Trigger (ST) based SRAM is proposed to reduce the power consumption. The Schmitt Trigger based SRAM bit cell, feedback is provided by separate control signal where in feedback is provided by the internal nodes.