Design and Implementation of a Low Power, Embedded CNN Accelerator on a Low end FPGA
in this paper, an optimized hardware for Convolutional Neural Networks with the purpose of implementation on embedded vision systems is presented. This design method is meant to be implemented with minimum resource consumption on a low end hardware platform. We propose an architecture on a Z turn evaluation board featuring a Xilinx Zynq 7000 system on chip (SoC) All computations in this architecture are optimized as 8 bit. Also, the accelerator has a frequency of 160 MHz and power consumption of 1.77 watts which leads to a performance of 40.96GOP/s, using only 134 computing units and 601 KB of internal memory. So we can claim that the acceptable speed and low power and low area consumption of this architecture make it an ideal choice for portable and embedded CNN applications.
2019 22nd Euromicro Conference on Digital System Design (DSD)