CMOS Devices Advanced Device Structures
This session contains six papers that describe the recent advanced device structures beyond 32 nm node including Si/SiGe nanowire, PD SOI for low power, and the future insulating technique. The first paper by Tezuka from MIRAI ASET proposes a novel anisotropic etching technique for multi nanowire channels. Mobility enhancement by hydrogen treatment is shown in this paper. The next paper by Suk from Samsung presents a detailed study of the electrical characteristics on gate all around Twin Silicon Nanowire MOSFET. The next paper by Tian from Peking University proposes a new method to fabricate self alinged silicon nanowire transistors on bulk silicon substrate. Excellent immunity of short channel effects and high Ion/Joff ration is demonstrated. The next paper on silicon nanowire transistor by Li from Samsung describes the impact of device performance on embedded SiGe source /drain technique. The effect of uniaxial compressive stress on different silicon nanowire orientation is evaluated. Park from Samsung fabricated a novel array device with a special partially insulated STI. Well isolation characteristic is improved remarkably due to increase of effective isolation path. Low power SOI technology for 65 nm node is given through detailed device design and junction engineering to decrease off current by Cai from IBM in the last presentation.
2007 IEEE International Electron Devices Meeting