Design of Digital FIR Filters Using CSE Algorithm
Many efficient algorithms and architectures have been introduced for the design of low complexity bitparallel Multiple Constant Multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit serial MCM design that offers alternative low complexity MCM operations. In this paper, we address the problem of optimizing the gate level area and delay in digit serial MCM designs, for that purpose we introduce high level CSE and GB algorithms. Experimental results show the efficiency of the proposed optimization algorithms and of the digit serial MCM architectures in the design of digit serial MCM operations and finite impulse response filters.