Proposal for Capacitance Matching in Negative Capacitance Field Effect Transistors
Negative capacitance transistors use ferroelectric (FE) material in the gate stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance <inline formula> <tex math notation="LaTeX"{C}_{\textsf {fe} /tex math>/inline formula> and the underlying MOS transistor <inline formula> <tex math notation="LaTeX"{C}_{\textsf {MOS} /tex math>/inline formula> Since both <inline formula> <tex math notation="LaTeX"{C}_{\textsf {MOS} /tex math>/inline formula> and <inline formula> <tex math notation="LaTeX"{C}_{\textsf {fe} /tex math>/inline formula> have strong non linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi layer FE to engineer the shape of <inline formula> <tex math notation="LaTeX"{C}_{\textsf {fe} /tex math>/inline formula> The proposed method is validated using the TCAD simulation of negative capacitance FDSOI transistor, and the results show that it leads to better sub threshold swing as well as lower power supply <inline formula> <tex math notation="LaTeX"{V}_{\textsf {dd} /tex math>/inline formula> compared with a prototype single layer negative capacitance field effect transistor.
IEEE Electron Device Letters