High Efficiency Class F Power Amplifier Design
Due to the high increase in and demand for a wide assortment of applications that require low cost, high efficiency, and compact systems, RF power amplifiers are considered the most critical design blocks and power consuming components in wireless communication, TV transmission, radar, and RF heating. Therefore, much research has been carried out in order to improve the performance of power amplifiers. Classes A, B, C, D, E and F are the main techniques for realizing power amplifiers. An implementation of high efficiency class F power amplifier with Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) was realized in this paper. The simulation and optimization of the class F power amplifier circuit model was undertaken using Agilent's Advanced Design system (ADS) The circuit was designed using lumped elements. Keywords Power Amplifier (PA) Gallium Nitride (GaN) Agilent's Advanced Design system (ADS) and lumped elements. I. SIMULATION METHODOLOGY CLASS F PA DESIGN AND CHOOSING OF OPERATION FREQUENCY O configure and design class F PA, a non linear model, EGN030MK GaN HEMT by Modelithics was used. This model is prepared for use to operate from 0.1 to 4.0 GHz with low current, wide band and high power design [5] Hence, 1.7GHz was chosen as an operation frequency in this paper. A. Choice of Bias Point From Figs. 1 (a) (c) gate to source voltage (Vgs) was chosen 0.6V when drain to source voltage, Vds was chosen 35V. Fig. 1 (a) Schematic of Transistor Biasing Abdalla Mohamed Eblabla is with the University of Glasgow. Department of Electronics and Electrical Engineering, Supervisor of Dr. Edward Wisage (e mail: aeblabla@yahoo.com) Fig. 1 (b) Ids vs. Vgs Characteristics for Vds=35 V Fig. 1 (c) Ids vs. Vds Characteristics for Different Vgs Values B. DC Bias Circuit Design In lumped elements configuration, DC block acts as an ideal capacitor used to oppose varieties in voltage while DCfeed acts as an ideal inductor used to oppose varieties in current. Therefore, preventing DC current from affecting the input and output lines is done by DC block while the AC current is allowed to pass throw. DC current is allowed by DC feed in order to bias the transistor while the AC current is blocked from passing throw [1] [2] C. Output Matching Network In Fig. 2, output network was done using lumped elements. The first tank was tuned at 5.1GHz which is the 3rd harmonic frequency (3f0) The assumed value of C is 33pF and calculated value of L is 0.0295nH. RL can be measured at chosen bias point as following [3] RL V I VDD I VDD I RL (8 35) (p 1.257) 22.57O P_1Tone PORT1 Freq=1.7 GHz P=dbmtow (20) Z=50 Ohm Num=1 Options Options1 MaxWarnings=10 GiveAllWarnings=yes I_AbsTol=1e 8 A I_RelTol=1e 3 V_AbsTol=1e 4 V V_RelTol=1e 3 Tnom=25 Temp=25 OPTIONS VAR VAR1 VGS=0 VDS=0 Eqn Var DC DC1 DC ParamSw eep Sw eep1 Step=5 Stop=40 Start=0 SimInstanceName[6] SimInstanceName[5] SimInstanceName[4] SimInstanceName[3] SimInstanceName[2] SimInstanceName[1]"DC1" Sw eepVar="VDS" PARAMETER SWEEP V_DC SRC1 Vdc=VGS V_DC SRC2 Vdc=VDS DC_Feed DC_Feed1 Term Term2 Z=50 Ohm Num=2 DC_Feed DC_Feed2