Highly linear Sampling Receivers in Silicon and BiCMOS Processes for Multi GS/s Optically and Electrically Sampled Systems
In this dissertation, high linearity sampling circuits are presented for wideband (multi GS/s) electrical and optical sampling, millimeter wave circuits are discussed for wideband communication, and injection locking is presented for nonlinear sampling and spectrum analysis. A 2GS/s sampling receiver with 4.5 measured effective number of bits is presented for spectrally efficient optical communication in a 45nm SOI CMOS process. Next, jitter limitations for broadband sampling circuits are discussed as sampling rates and input bandwidths are increased. An integrate and dump optical receiver is introduced for high dynamic range photonic analog to digital conversion at a sample rate of 2GS/s. Next, a novel rate scalable photonic analog to digital converter is described that enables very low jitter, high linearity, and low noise photonic sampling and subsequent analog to digital conversion of wideband signals up to 10GHz and beyond. A special emphasis is placed on achieving high system linearity. Integrate and sample receivers will be discussed within this context, as they bring both signal to noise ratio benefits due their approximation of a matched filter, and because they reduce the subsequent electronic analog to digital converter bandwidth, linearity, and jitter requirements. In addition, an alternative complementary photonic sampling architecture is presented for novel emph{pseudo differential} photonic analog to digital conversion, and measurement results will be provided for the photonic sub sampling front end and the integrate and sample receiver with input frequencies up to 50GHz at a 2GS/s rate. The jitter benefits of optical sampling are demonstrated with a measurement of 36.4dB of SNR with a 49.8GHz input at a 2GS/s rate. Following this discussion of high linearity receivers for photonic analog to digital conversion, electronic sampling circuits in SiGe BiCMOS and InP BiCMOS are described for sampling with high dynamic range. First, the design and measurement results for a track and hold 120nm SiGe BiCMOS are provided with 9 bit linearity at 2GS/s with an electrical input of 1Vpp. Next, very high speed track and hold and time interleaved sampling architectures are described in an InP BiCMOS technology for sampling at 40GS/s and beyond. In the second part of this dissertation, traveling wave techniques for millimeter wave wide band communication circuits and nonlinear techniques for spectrum analysis are discussed. A Ka band high pass distributed amplifier is implemented in a 120nm SiGe BiCMOS process with a gain of 8.5 dB, sharp rejection below the low frequency cutoff, a bandwidth of 21.5GHz, and a power consumption of 28mW from a 1.7V supply. Following, a constructive wave deterministic quadrature oscillator and N push modulator in 120nm SiGe BiCMOS is presented for operation at 92GHz in W band. Operating at 32mW from a 2V supply, the oscillator contains an integrated quadrature modulator suitable for BPSK and QPSK modulation and a measured phase noise of 78.6dBc/Hz at an offset of 1MHz. Both of these millimeter wave designs support wideband communication and could be used in receiver designs in conjunction with multi GS/s analog to digital converters. Injection locking as a means of spectral sampling is presented for chip scale, low power spectrum analysis suitable for cognitive radio and adaptive radio architectures. In comparison to state of the art optical and electrical sampling techniques described in the first part of the dissertation, this all analog injection locked sampling technique has significant advantages in terms of power dissipation and integration on chip. Two architectures will be presented for injection locked spectrum analysis. First, an injection locked oscillator array with measurement results from two injection locked oscillators is implemented in 120nm SiGe BiCMOS with oscillation frequencies close to 5.5GHz. Second, an improved architecture is presented with balanced injection locked phase locked loops in which detection of the input signal's frequency and power is orthogonal