10 nm CPI Study for Fine Pitch Flip Chip Attach Process and Substrate by
The rapid growth rate of advance technology developments in the semiconductor industry is driving the evolution in emerging markets to satisfy the increasing requirements of higher performance, higher bandwidth and lower power consumption as well as multiple functions in portable and mobile devices. Electronic devices have evolved from a simple communication device to a complicated and highly integrated system with multiple functions required. Moving forward with this trend, packaging semiconductor devices for mobile electronics is more challenging than ever before, pushing smaller form factor package designs and developments in emerging markets. To meet these demands, developments in advanced silicon (Si) nodes, finer bump pitch attach processes as well as finer line width and spacing (LW/LS) substrate manufacturing has become a hot topic in the industry. For example, look at the Si node development status. While 20/16/14nm technology is widely utilized today in mobile applications to pursue the die size reduction, efficiency enhancement and lower power consumption, 10nm technology is receiving increasing attention. Based on the requirements and evolution of mobile applications, package types have migrated from wire bond packaging to flip chip chip scale package (fcCSP) to deliver cleaner power to the device, provide higher input/output (I/O) to accommodate the volume of high speed consumer devices and still satisfy all other requirements without compromising reliability and/or cost. In order to achieve high I/O solutions, finer flip chip bump pitch as well as finer line width and spacing are becoming the attractive solution to meet this target. Flip chip interconnect with copper (Cu) pillar bond on lead (BOL) and enhanced processes (fcCuBE (r) can deliver a high performance packaging solution with a cost effective mass reflow (MR) manufacturing process. The robust flip chip bump process with copper pillar technology in fcCuBE (r) has been widely adopted to achieve bump pitch reduction, performance improvement and Si node reduction. In order to realize the chip package interaction (CPI) in a fcCSP with 10nm backend process daisychain die and Cu pillar BOL architecture, the cost effective solution of mass reflow flip chip attach process with 90mm and 60mm bump pitch and a 2 layer embedded trace substrate (ETS) is evaluated. The quick temperature cycling (QTC) test is performed to realize the 10nm extremely low k (ELK) performance in a fcCSP. Through these results, the significant factors to impact ELK performance can be delivered to enhance the yield in the chip attach process. It is believed that this successful data can help guarantee the 10nm flip chip assembly yield without ELK damage issues in the future.