LSFQ: A Low Precision Full Integer Quantization for High Performance FPGA Based CNN Acceleration
Neural network quantization has become an important research area. Deep networks run with low precision operations at inference time offer power and space advantages over high precision alternatives, and can maintain high accuracy. However, few quantization can demonstrate this advantage on hardware platform, because the design of quantization algorithm lacks the consideration of actual hardware implementation. In this paper, we propose an efficient quantization method for hardware implementation, a learnable parameter soft clipping fully integer quantization (LSFQ) which includes weight quantization and activation quantization with learnable clipping parameter method. The quantization parameters are optimized automatically by back propagation to minimize the loss, then the BatchNorm layer and convolutional layer are fused, and the bias and quantization step size are further quantized. In this way, LSFQ accomplishes integer only arithmetic. We evaluate the quantization algorithm on a variety of models including VGG7, mobile net v2 in CIFAR10 and CIFAR100. The results show that when the quantization reaches 3 bit or 4 bit, the accuracy loss of our method is less than 1 compared with the full precision network. In addition, we design an accelerator for the quantization algorithm and deploy it to the FPGA platform to verify the hardware awareness of our method.
2021 IEEE Symposium in Low Power and High Speed Chips (COOL CHIPS)