A 2.3 ps RMS Resolution Time to Digital Converter Implemented in a Low Cost Cyclone V FPGA
We present a nonuniform multiphase (NUMP) method to construct a high resolution time to digital converter (TDC) for low cost field programmable gate array (FPGA) devices. The NUMP method involves a system clock being passed through a series of delay elements to generate multiple clocks with different phase shifts. The phases of the rising and falling edges of all the clocks are sorted in order and the states of all the clocks are latched when a hit signal arrives. The sizes of the time bins (and precision) of the NUMP method are not limited by the uniformity and minimum value of the time delays of the delay lines. In theory, any delay sources with small jitters in an FPGA, not just very fine carry chains, can be used in the NUMP method to delay and randomize the clocks. Thus, the NUMP method can achieve excellent TDC timing resolutions in low cost FPGAs without very fine delay lines. We implemented four NUMP TDC channels in a low cost FPGA device (an Altera Cyclone V 5CEBA4F23C7N) The performance of the four NUMP TDCs was evaluated using both internal and external pulses. The root mean square (rms) for the timing resolution measured using the internal and the external pulses with short time intervals (less than 1 ns) was 2.3 and 5.2 ps, respectively. A 14.1 ps rms timing resolution was measured at a time interval of 517 ns. The NUMP method is suitable for applications that require a number of high performance TDC channels in a low cost FPGA.
IEEE Transactions on Instrumentation and Measurement