An Integrated Framework for Multi Core Architectures with 3D Stacked Memory
As the number of processor cores on a chip increases, researches on three dimensional integration receives growing attention. Stacking last level cache memory on processor cores is a promising way to solve the well known 'memory wall' problem which limits performance of multi processor [1] Chip temperature is a major performance bottleneck of 3D ICs, because stacking multiple dies leads to higher power density than 2D IC. Therefore, the hybrid design considering performance, power, and temperature is crucial in the multi processor architecture with 3Dstacked cache memory. Conventional simulation tools, however, do not provide required environment for the hybrid design. Moreover, these tools are not able to examine processor management schemes such as dynamic power management, task scheduling, and dynamic cache partitioning. In this paper, we propose an integrated framework for dynamic processor management considering performance, power and temperature on multi core architectures with 3D stacked memory. The experimental results show the importance of our framework to improve performance of the multi processor.