Fast Quantum Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive or Gate and Full Adder
Quantum dot Cellular automata is a promising area to implement digital systems at nano scale level. Adders and subtractors are widely used in almost every digital information processing system. This work targets to design an efficient 8 bit adder/subtractor that can perform addition as well as subtraction by using a novel control signal distribution scheme. To perform controlled inversion of inputs a novel exclusive or gate with fewer cells is proposed. During Quantum dot Cellular automata circuit fabrication, missing cell defects have the potential to affect the performance of a circuit. The proposed designs have higher fault resistance to missing cell defects compared to the existing state of the art designs. Results demonstrate that the proposed design has (N 2) less clock phases compared to the existing state of the art designs. The proposed design can be extended to implement any N bit adder/subtractor. All the designs are designed and verified using coherence vector simulation engine in QCADesigner.
International Journal of Theoretical Physics