Memristor crossbar based multicore neuromorphic processors
This paper describes memristor based neuromorphic circuits for non linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed based on this neuron circuit. By applying neural network learning algorithms to these circuits, we demonstrate the learning of both linearly and non linearly separable logic functions. The simulations are carried out in SPICE using a detailed memristor model so that the crossbar is simulated as accurately as possible. We also examine the system level performance of multicore memristor crossbar based neuromorphic processors. We consider the impact on on chip routing, calculate the chip areas, and evaluate the timing of the systems in the study. The results indicate that such architectures can enable over 300,000 times energy efficiencies over traditional high performance computing architectures when processing large neural networks.
2014 27th IEEE International System on Chip Conference (SOCC)