Transactional memory analysis using CSB+ trees
Enterprise applications using in memory databases prefer to run on scale up systems where the amount of memory and CPUs available are increasing with each generation. In addition to the cores/socket, the number of hardware threads per core has also increased. Increasing cores/socket and HW threads per core provides opportunities for more parallelism from application's perspective. But the applications fail to achieve the expected linear scaling due to various reasons. One of the key reason being the application having to serialize access to certain resources. Hardware transactional memory provides a way for the application to execute concurrently without serializing them using locks. We let the CPUs execute enter transactional mode concurrently and let them execute until a transaction failure is detected which primarily is due to cache line collision. Else, we let all of them succeed. Hardware transactional memory is available in Haswell processors from Intel and also in Power8 processors from IBM. The most important data structure where enabling parallel access becomes critical is a tree update or modify. Without this we will have to serialize the threads using a global lock which prevents the application from using all the available CPUs. In this paper, we will use an sample program of cache sensitive B+ tree (CSB+ tree) which is used in file system meta data indexing and in key value database systems where the data access performance is very critical and compare the performance advantages of using a transactional memory and its scalability. Also, we will provide ways to improve or tune the performance.