A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS
This paper describes a single cycle throughput lighting accelerator fabricated in 1.05 V, 32 nm CMOS for on die acceleration of 3D graphics vertex and pixel shading in high performance processors and mobile systems on chip. Log domain parallel computation of ambient, diffuse, and specular lighting using high accuracy 32b log and anti log units that convert computation from floating point (FP) to fixed point domain, 32b sparse tree fixed point adders and a 32 x 32b signed fixed point multiplier with truncated partial product reduction tree enable 2.05 GVertices/s throughput measured at 1.05 V, 25degC in an area of 0.064 mm2 while achieving: (i) 47% reduction in critical path logic stages compared to previously published work, (ii) 0.56% mean vertex lighting error compared to single precision FP computation, (iii) 354 mW active leakage power measured at 1.05 V, 25 degC, (iv) scalable performance up to 2.22 GHz, 232 mW measured at 1.2 V, (v) peak energy efficiency of 56 GVertices/s/W, measured at 560 mV, 25 degC, and (vi) 119.6 dB PSNR for a 2 M pixel high resolution 3D image.
IEEE Journal of Solid State Circuits