Delta Sigma Modulator based Discrete Data Multiplier with Digital Output
In the proposed multiplier configuration, a new technique is proposed for multiplication of two sampled analog signals and the output is in digital form. One analog signal is fed to the input of first delta sigma modulator (DSM1) after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of second DSM(DSM2).The resulting bit stream at the output of DSM2 is the digital representation of the product of the sampled data of the two analog signals. I. INRODUCTION The second order, single stage, discrete, single bit quantizer and unity feedback gain Delta Sigma Modulator (DSM) [1][2] is shown in Fig. (1) and is a typical DSM where xanalog is the analog input signal. The Sample and Hold (S/H) circuit over samples the input signal at a sampling period (update period) TU. The DSM circuit is operated by the clock with period TC (TC TU) x(i) is the sampled analog input signal to the DSM circuit during the i sampling period. x1(i,j x2(i,j) z(i,j and e(i,j) represents the first integrator output, second integrator output, quantizer output and quantizer error signal in i sampling period and during j clock period. The average values of the outputs of the first integrator, second integrator, quantizer and error signal during i update period are denoted as x1(i) x2(i) z(i) and e(i) respectively. The block D is the delay unit of one clock period. The normalized input signal during the i update period, xnor(i) is the ratio of x(i) to the feedback gain. Fig. 1. Schematic diagram of typical second order DSM. For a typical DSM with unity feedback gain, z(i) is equal to x(i)during the i update period. The subscript i is dropped in the figures and in further discussion. If the quantizer output is VS then the range of xanalog is 0.7VS xanalog< +0.7VS. Input signal dependant feedback gain and input signal dependant operating period is used in DSM, to make the DSM more stable for extended range of input and suitable for industrial applications [3] In the patents [4] and [5] and in the papers [6] and [9] the accuracy of, analog multipliers which use different techniques, is limited by the tolerance of the analog components. In [4] an analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters is presented for very low supply voltage with less distortion at the output of multiplier. In [5] is discussed an analog multiplier which has MOS input stage which provides good linearity range for the multiplier. In [6] is proposed a four quadrant CMOS multiplier in which the output voltage swings with linearity of less than 1% The dynamic ranges of the two input signals are 72% and 48% of supply voltage, 2.5V. In [7] are compared eight categories of transconductance multipliers. The best linearity out of the eight categories of multipliers is about 0.5% The low cost precision multiplier which is supplied by Analog Devices has maximum four quadrant accuracy of 2% of full scale [8] K.Diwakar et al. International Journal of Engineering and Technology (IJET) ISSN 0975 4024 Vol 7 No 1 Feb Mar 2015 117 The analog multiplier which is proposed in [9] is used for power and energy measurement and the power is measured with an accuracy of 0.25% In [10] is proposed cmos four quadrant analog multiplier which gives better bandwidth and less power dissipation but accuracy is not improved. In [11] is proposed analog multiplier using operational amplifiers and the linearity error in the multiplier is 0.09% Zhangcai Huang et. al. proposed a four quadrant CMOS multiplier in which the output voltage swings with linearity less than 1% The dynamic ranges of the two input signals are 72% and 48% of supply voltage [12] Dei M. et. al. proposed Gilbert like CMOS multiplier based on linear current divider in which the distortion is less than 1% [13] Han G. et. al. proposed eight categories of trans conductance multipliers and compared. The best linearity out of the eight categories of multipliers is about 0.5% [14] In the case of proposed DSM based multiplier, two DSMs working with same clock frequency multiply the two analog input signals and the result is in digital form. The tolerance requirements of analog components in the DSMs are relaxed. The cost paid for high accuracy is faster operation and is feasible as on chip VLSI implementation technology advances. The proposed multiplier is DSM based four quadrant multiplier with new technique. It has maximum accuracy of 0.0344% of FS for low frequency signals when the sampling period of analog signals is 0.01sec and the DSMs operating clock period is 0.1msec. The maximum value of the input signal can be increased to 70% of feedback gain. The proposed multiplier has better accuracy and wider input range compared to the conventional CMOS multipliers. The major advantage is that it multiplies two low frequency analog signals and provides digital output directly which is useful for power electronics applications like motor control using SCs. In this paper, the proposed low cost four quadrant multiplier uses a new technique using basically two typical DSMs, a switch and a NOT circuit. The standard available CMOS operational amplifiers' specification with DC gain (Aod) 100V/mV, bandwidth 10MHz, input offset voltage 20mV and supply voltage 2.5V is considered for op amps in this proposal. With considered specification of the CMOS op amp. the proposed multiplier has maximum overall accuracy of 0.46% of FS (full scale of supply voltage) for low frequency signals. The maximum value of the input voltages can be 70% of the supply voltage because only dc signals are fed to DSMs. The input voltages of DSMs are restricted to 70% due to stability reasons. If 2.5V is the supply voltage of the operational amplifiers used in the circuit then the input signals can range from 1.75V to +1.75V with feedback gain constant equal to 2.5. The proposed multiplier has better accuracy and wider input range compared to the conventional CMOS multipliers. II. PROPOSED MULTIPLIER CONFIGURATION The details of proposed multiplier including the block diagram, relation between inputs and output, accuracy of inverting amplifier, implementation of non ideality factors and the advantages are presented in this section inverter circuit and the specification of op amp which is used in the circuits. A. Block Diagram of Proposed Multiplier In this multiplier configuration a new technique is proposed for multiplication of two sampled discrete analog signals and the output is in digital form. One analog signal is fed to the input of first DSM (DSM1) after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of second DSM (DSM2) The resulting bit stream at the output of second DSM is the digital representation of the product of the two analog signals. The block diagram of the proposed multiplier is shown in Fig.2. The sample and hold circuit S/H1 samples the input signal xanalog at a sampling period TU. The sampled analog input signal x is fed to the input of DSM1. The DSM1circuit is operating with the clock of period TC (TU TC) The SR flip flop is reset (phase Foff) during each positive transition of the clock signal. The output of the single bit quantizer, Q1 is in 1 state or in 0 state. When the quantizer output is in 1 state, SR flip flop is set (phase Phon) The S/H2 circuit samples the input signal yanalog at a sampling period TU. The DSM2 circuit is also operating with the clock of period TC. The sampled analog input signal y is fed to the input of DSM2 during phase Phon. The variable y is negated and fed to DSM2 during phase Foff. K.Diwakar et al. International Journal of Engineering and Technology (IJET) ISSN 0975 4024 Vol 7 No 1 Feb Mar 2015 118 Fig. 2. Proposed Multiplier of Configuration During each sampling period, the bit stream at the output of quantizer Q2, gives the digital representation of the product of sampled input signals. The average value of the bit stream at the output during each sampling period (z) gives the analog value of the product of normalized samples of input signals n y n x Therefore, the normalized value of z (nz) is equal to the normalized product of input signals n xy The resolution of DSM output Dz is given by, n T T z U C D However, Dz is limited by the realization of inverter circuit and the specification of op amp which is used in the circuits. B. Relation between Inputs and Output Let x,y be the samples fed to DSM1 and DSM2 respectively in i sampling period. If b1, b2..bn are the stream of outputs of DSM1 during i sampling period, then the average analog input to DSM2 during TU is