The major drawback with NMOS (and most other logic families) is that a DC current must flow through a logic gate even when the output is in a steady state (low in the case of NMOS). This means static power dissipation, i.e. power drain even when the circuit is not switching. A similar situation arises in modern high speed, high density CMOS circuits (microprocessors, etc.) which also has significant static current draw, although this is due to leakage, not bias.