264 KB SRAM in six independent banks No internal flash or EEPROM memory (after reset, the boot-loader loads firmware from either external flash memory or USB bus into internal SRAM) QSPI bus controller, supporting up to 16 MB of external flash memory DMA controller AHB crossbar, fully-connected On-chip programmable low-dropout regulator (LDO) to generate core voltage 2 on-chip PLLs to generate USB and core clocks 30 GPIO pins, of which 4 can optionally be used as analog inputs Peripherals: 2 UARTs 2 SPI controllers 2 I²C controllers 16 PWM channels USB 1.1 controller and PHY, with host and device support 8 programmed input–output (PIO) state machines