For instance, for PMOS memories this technology delivered three to five times the speed in half the chip area.[9] The polysilicon gate material not only made the self-aligned gate possible, it also resulted in a reduced threshold voltage and consequently in a lower minimum power supply voltage (e.g. -16 V[10]: 1-13 ), reducing the power consumption. Because of the lower power supply voltage, silicon gate PMOS logic is often referred to as low-voltage PMOS in contrast to the older, metal-gate PMOS as high-voltage PMOS.[3]: 89