Design and Implementation of a Low-Power Low-Noise Biopotential Amplifier in 28 nm CMOS Technology with a Compact Die-Area of 2500 $\mu$m$^2$
<|reference_start|>Design and Implementation of a Low-Power Low-Noise Biopotential Amplifier in 28 nm CMOS Technology with a Compact Die-Area of 2500 $\mu$m$^2$: This paper presents a compact low-power, low-noise bioamplifier for multi-channel electrode arrays, aimed at recording action potentials. The design we put forth attains a notable decrease in both size and power consumption. This is achieved by incorporating an active lowpass filter that doesn't rely on bulky DC-blocking capacitors, and by utilizing the TSMC 28 nm HPC CMOS technology. This paper presents extensive simulation results of noise and results from measured performance. With a mid-band gain of 58 dB, a -3 dB bandwidth of 7 kHz (from 150 Hz to 7.1 kHz), and an input-referred noise of 15.8 $\mu$V$_{\rm rms}$ corresponding to a NEF of 12. The implemented design achieves a favourable trade-off between noise, area, and power consumption, surpassing previous findings in terms of size and power. The amplifier occupies the smallest area of 2500 $\mu$m$^2$ and consumes only 3.4 $\mu$W from a 1.2 V power supply corresponding to a power efficiency factor of 175 and an area efficiency factor of 0.43, respectively.<|reference_end|>
@article{koleibi2024design,
    title={Design and Implementation of a Low-Power Low-Noise Biopotential
  Amplifier in 28 nm CMOS Technology with a Compact Die-Area of 2500 $\mu$m$^2$},
    author={Esmaeil Ranjbar Koleibi, Konin Koua, William Lemaire, Maher Benhouria,
  Marwan Besrour, Takwa Omrani, J'er'emy M'enard, Louis-Philippe Gauthier,
  Montassar Dridi, Mahziar Serri Mazandarani, Benoit Gosselin, S'ebastien
  Royand R'ejean Fontaine},
    journal={arXiv preprint arXiv:2406.17779},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.17779},
    primaryClass={q-bio.NC cs.SY eess.SP eess.SY physics.bio-ph}
}