Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
<|reference_start|>Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS: Open-source hardware (OSHW) is rapidly gaining traction in academia and industry. The availability of open RTL descriptions, EDA tools, and even PDKs enables a fully auditable supply chain for end-to-end (RTL to layout) open-source silicon, significantly strengthening security and transparency. Despite promising developments, existing OSHW efforts have so far fallen short of producing end-to-end open-source SoCs at the complexity and performance level needed to run a general-purpose OS. We present Basilisk, the first end-to-end open-source, Linux-capable RISC-V SoC taped out in IHP's open 130 nm technology. Basilisk features a 64-bit RISC-V core, a fully digital HyperRAM DRAM controller, and a rich set of IO peripherals including USB 1.1 and VGA. To tape out Basilisk, we create a reusable tool pipeline to convert its industry-grade SystemVerilog description to Verilog. We optimized logic synthesis in the open source Yosys synthesis tool, obtaining an increase in Basilisk's peak clock speed by 2.3x to 77 MHz and reducing its cell area by 1.6x to 1.1 MGE while also reducing synthesis runtime and RAM usage. We further optimized place and route in OpenROAD, enabling convergence to zero DRC violations while increasing core area utilization by 10% and reducing die area by 12%.<|reference_end|>
@article{scheffler2024basilisk:,
    title={Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm
  CMOS},
    author={Paul Scheffler, Philippe Sauter, Thomas Benz, Frank K. G"urkaynak,
  Luca Benini},
    journal={arXiv preprint arXiv:2406.15107},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.15107},
    primaryClass={cs.AR}
}