Modeling State in Software Debugging of VHDL-RTL Designs -- A Model-Based Diagnosis Approach
<|reference_start|>Modeling State in Software Debugging of VHDL-RTL Designs -- A Model-Based Diagnosis Approach: In this paper we outline an approach of applying model-based diagnosis to the field of automatic software debugging of hardware designs. We present our value-level model for debugging VHDL-RTL designs and show how to localize the erroneous component responsible for an observed misbehavior. Furthermore, we discuss an extension of our model that supports the debugging of sequential circuits, not only at a given point in time, but also allows for considering the temporal behavior of VHDL-RTL designs. The introduced model is capable of handling state inherently present in every sequential circuit. The principal applicability of the new model is outlined briefly and we use industrial-sized real world examples from the ISCAS'85 benchmark suite to discuss the scalability of our approach.<|reference_end|>
@article{peischl2003modeling,
    title={Modeling State in Software Debugging of VHDL-RTL Designs -- A
  Model-Based Diagnosis Approach},
    author={Bernhard Peischl, Franz Wotawa},
    journal={arXiv preprint arXiv:cs/0311001},
    year={2003},
    archivePrefix={arXiv},
    eprint={cs/0311001},
    primaryClass={cs.AI cs.SE}
}