Demonstration of 3 V Programmable Josephson Junction Arrays Using Non-Integer-Multiple Logic
<|reference_start|>Demonstration of 3 V Programmable Josephson Junction Arrays Using Non-Integer-Multiple Logic: This article demonstrates a new kind of programmable logic for the representation of an integer that can be used for the programmable Josephson voltage standard. It can enable the numbers of junctions in most bits to be variable integer values, which is different from normal binary logic or ternary logic. Consequently, missing junctions due to superconducting short circuits can be tolerated under this logic. This logic can also have nearly the same segmentation efficiency as ternary logic. The completeness of the sequences using this logic is proven by the recursive method in mathematics in this paper. After that, a new algorithm for the representation of integers is presented according to the proven process, and an analysis of the number of fault-tolerant junctions for each bit is provided. Although the first and second bits are not tolerant to missing junctions, bits beyond these can tolerate one to hundreds of missing junctions. Due to the non-fixed multiples between the bits of the sequence, this logic is called non-integer-multiple logic. Finally, the design and fabrication of a 3 V programmable Josephson junction array using this logic are described, and the measurements and analysis of the characteristic parameters are presented.<|reference_end|>
@article{cao2024demonstration,
    title={Demonstration of 3 V Programmable Josephson Junction Arrays Using
  Non-Integer-Multiple Logic},
    author={Wenhui Cao, Erkun Yang, Jinjin Li, Guanhua She, Yuan Zhong, Qing
  Zhong, Da Xu, Xueshen Wang, Xiaolong Xu, Shijian Wang and Jian Chen},
    journal={arXiv preprint arXiv:2402.16072},
    year={2024},
    archivePrefix={arXiv},
    eprint={2402.16072},
    primaryClass={cs.ET quant-ph}
}