SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results
<|reference_start|>SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results: Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -- the word-line voltage margin (VWLVM) -- and the measured circuit alpha-SER. Additional experiments show that no other memory cell electrical robustness-related parameters exhibit such correlation. The technique proposed is based on correlating the VWLVM to the SER measured on a small number of circuit samples to determine the correlation parameters. Then, the remaining non-irradiated circuits SER is determined from electrical measurements (VWLVM) without the need of additional radiation experiments. This method represents a significant improvement in time and cost, while simplifying the SER-determination methods since most of the circuits do not require irradiation. The technique involves a minor memory design modification that does not degrade circuit performance, while circuit area increase is negligible.<|reference_end|>
@article{torrens2024sram,
    title={SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements:
  Design Architecture and Experimental Results},
    author={Gabriel Torrens (1), Ivan de Paul (1), Bartomeu Alorda (1), Sebastia
  Bota (1) and Jaume Segura (1) ((1) University of the Balearic Islands)},
    journal={IEEE Transactions on Nuclear Science, vol. 61, no. 4, pp.
  1849-1855, Aug. 2014},
    year={2024},
    doi={10.1109/TNS.2014.2311697},
    archivePrefix={arXiv},
    eprint={2402.10917},
    primaryClass={cs.AR}
}