Hypervisor Extension for a RISC-V Processor
<|reference_start|>Hypervisor Extension for a RISC-V Processor: This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.<|reference_end|>
@article{gauchola2024hypervisor,
    title={Hypervisor Extension for a RISC-V Processor},
    author={Jaume Gauchola, JuanJos'e Costa, Enric Morancho, Ramon Canal, Xavier
  Carril, Max Doblas, Beatriz Otero, Alex Pajuelo, Eva Rodr'iguez, Javier
  Salamero, Javier Verd'u},
    journal={arXiv preprint arXiv:2406.17796},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.17796},
    primaryClass={cs.AR}
}