Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC
<|reference_start|>Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC: We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteeing a device cross-section lower than $5.36 \times 10^{-12}$ cm$^2$.<|reference_end|>
@article{rogenmoser2024design,
    title={Design and Experimental Investigation of Trikarenos: A Fault-Tolerant
  28nm RISC-V-based SoC},
    author={Michael Rogenmoser, Philip Wiese, Bruno Endres Forlin, Frank K.
  G"urkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini},
    journal={arXiv preprint arXiv:2407.05938},
    year={2024},
    archivePrefix={arXiv},
    eprint={2407.05938},
    primaryClass={physics.ins-det cs.AR hep-ex}
}