Analog Spiking Neuron in CMOS 28 nm Towards Large-Scale Neuromorphic Processors
<|reference_start|>Analog Spiking Neuron in CMOS 28 nm Towards Large-Scale Neuromorphic Processors: The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms.   In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC's 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 $\mu m^{2}$, leading to a maximum spiking frequency of 300 kHz at 250 mV power supply.   These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit post-training quantization stands at 82.5\%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications.<|reference_end|>
@article{besrour2024analog,
    title={Analog Spiking Neuron in CMOS 28 nm Towards Large-Scale Neuromorphic
  Processors},
    author={Marwan Besrour, Jacob Lavoie, Takwa Omrani, Gabriel Martin-Hardy,
  Esmaeil Ranjbar Koleibi, Jeremy Menard, Konin Koua, Philippe Marcoux, Mounir
  Boukadoum, Rejean Fontaine},
    journal={arXiv preprint arXiv:2408.07734},
    year={2024},
    archivePrefix={arXiv},
    eprint={2408.07734},
    primaryClass={cs.NE eess.SP}
}