Synth\`ese Comportementale Sous Contraintes de Communication et de Placement M\'emoire pour les composants du TDSI
<|reference_start|>Synth\`ese Comportementale Sous Contraintes de Communication et de Placement M\'emoire pour les composants du TDSI: The design of complex Digital Signal Processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. Unfortunately, the traditional Matlab/ Simulink design flows gather not very flexible hardware blocs. In this paper, we present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, our tool GAUT helps the designer in finding a reasonable trade-off between the circuit's performance and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm.<|reference_end|>
@article{corre2006synth\`{e}se,
    title={Synth\`{e}se Comportementale Sous Contraintes de Communication et de
  Placement M\'{e}moire pour les composants du TDSI},
    author={Gwenol'e Corre (LESTER), Philippe Coussy (LESTER), Pierre Bomel
  (LESTER), Eric Senn (LESTER), Eric Martin (LESTER)},
    journal={GRETSI'05 (Colloque sur le Traitement du Signal et de l'Image),
  Belgique (2005) 779-782},
    year={2006},
    archivePrefix={arXiv},
    eprint={cs/0605146},
    primaryClass={cs.AR}
}