Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML
<|reference_start|>Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML: The emergence of Deep Neural Network (DNN) and machine learning-based applications paved the way for a new generation of hybrid hardware platforms. Hybrid platforms embed several cores and accelerators in a small package. However, in order to satisfy the Size, Weight and Power (SWaP) constraints, limited and shared resources are integrated. This paper presents an overview of the standards applicable to the certification of hybrid platforms and an early mapping of their objectives to said platforms. In particular, we consider how the classification of AMC20-152A for airborne electronic hardware applies to hybrid platforms. We also consider AMC20-193 for multi-core platforms, and how this standard fits different types of accelerators.<|reference_end|>
@article{lesage2024towards,
    title={Towards the Certification of Hybrid Architectures: Analysing
  Interference on Hardware Accelerators through PML},
    author={Benjamin Lesage, Fr'ed'eric Boniol, Kevin Delmas, Adrien Gauffriau,
  Alfonso Mascarenas Gonzalez, Claire Pagetti},
    journal={arXiv preprint arXiv:2406.12346},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.12346},
    primaryClass={cs.AR}
}