FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning
<|reference_start|>FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning: This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning (RL) with the goal of minimizing wirelength. In addition to our preliminary learning results, we also evaluated a novel decomposition to address the nature of large search space when placing many blocks on a chipboard. Empirical experiments evaluate the effectiveness of the learning and decomposition paradigms on FPGA placement tasks.<|reference_end|>
@article{wang2024fpga,
    title={FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning},
    author={Shang Wang, Deepak Ranganatha Sastry Mamillapalli, Tianpei Yang,
  Matthew E. Taylor},
    journal={arXiv preprint arXiv:2404.13061},
    year={2024},
    archivePrefix={arXiv},
    eprint={2404.13061},
    primaryClass={cs.AR cs.AI cs.LG}
}