A 35 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping
<|reference_start|>A 35 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping: In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop configuration. A key enabler of the high-bandwidth MASH VCO ADC is the use of a multi-bit estimated error signal. With an OSR of 16, an SNDR of 67 dB and DR of 68 dB are achieved in 109.375 MHz bandwidth. The full-custom pseudo-analog circuits consume 9 mW, while the automatically generated digital circuits consume another 24 mW. A $\mathbf{FoM_{DR} = 163}$ dB and core area of $\mathbf{0.017\,\mathbf{mm}^2}$ are obtained.<|reference_end|>
@article{saux2024a,
    title={A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping},
    author={Brendan Saux, Jonas Borgmans, Johan Raman and Pieter Rombouts},
    journal={arXiv preprint arXiv:2409.15066},
    year={2024},
    doi={10.1109/TCSI.2024.3450570},
    archivePrefix={arXiv},
    eprint={2409.15066},
    primaryClass={eess.SY cs.SY}
}