Silicon Photonic 25D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
<|reference_start|>Silicon Photonic 25D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators: Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energy-efficient and high throughput 2.5D ML accelerator architectures.<|reference_end|>
@article{sunny2024silicon,
    title={Silicon Photonic 2.5D Interposer Networks for Overcoming Communication
  Bottlenecks in Scale-out Machine Learning Hardware Accelerators},
    author={Febin Sunny, Ebadollah Taheri, Mahdi Nikdast, Sudeep Pasricha},
    journal={arXiv preprint arXiv:2403.04189},
    year={2024},
    archivePrefix={arXiv},
    eprint={2403.04189},
    primaryClass={cs.AR cs.LG eess.SP}
}