Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock
<|reference_start|>Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock: This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D (i.e., nFETs and pFETs are stacked in 3D). Thus, signal/power routing layers have fine-grained, all-sided access to the FET active regions maximizing 3D standard cell design flexibility. This is in sharp contrast to approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and stacked FETs. Importantly, the routing flexibility of Omni 3D is enabled by double-side routing and an interleaved metal (IM) layer for inter- and intra-cell routing, respectively. In this work, we explore Omni 3D variants (e.g., both with and without the IM layer) and optimize these variants using a virtual-source BEOL-FET compact model. We establish a physical design flow that efficiently utilizes the double-side routing in Omni 3D and perform a thorough design-technology-co-optimization (DTCO) of Omni 3D device architecture on several design points. From our design flow, we project 2.0x improvement in the energy-delay product and 1.5x reduction in area compared to the state-of-the-art CFETs with BSPDNs.<|reference_end|>
@article{choi2024omni,
    title={Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and
  Clock},
    author={Suhyeong Choi, Carlo Gilardi, Paul Gutwin, Robert M. Radway, Tathagata
  Srimani, Subhasish Mitra},
    journal={arXiv preprint arXiv:2409.16608},
    year={2024},
    archivePrefix={arXiv},
    eprint={2409.16608},
    primaryClass={cs.ET cs.AR}
}