SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
<|reference_start|>SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers: Stencil codes are performance-critical in many compute-intensive applications, but suffer from significant address calculation and irregular memory access overheads. This work presents SARIS, a general and highly flexible methodology for stencil acceleration using register-mapped indirect streams. We demonstrate SARIS for various stencil codes on an eight-core RISC-V compute cluster with indirect stream registers, achieving significant speedups of 2.72x, near-ideal FPU utilizations of 81%, and energy efficiency improvements of 1.58x over an RV32G baseline on average. Scaling out to a 256-core manycore system, we estimate an average FPU utilization of 64%, an average speedup of 2.14x, and up to 15% higher fractions of peak compute than a leading GPU code generator.<|reference_end|>
@article{scheffler2024saris:,
    title={SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V
  Compute Clusters with Indirect Stream Registers},
    author={Paul Scheffler, Luca Colagrande, Luca Benini},
    journal={arXiv preprint arXiv:2404.05303},
    year={2024},
    archivePrefix={arXiv},
    eprint={2404.05303},
    primaryClass={cs.MS cs.AR}
}