High-level synthesis under I/O Timing and Memory constraints
<|reference_start|>High-level synthesis under I/O Timing and Memory constraints: The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.<|reference_end|>
@article{coussy2006high-level,
    title={High-level synthesis under I/O Timing and Memory constraints},
    author={Philippe Coussy (LESTER), Gwenol'e Corre (LESTER), Pierre Bomel
  (LESTER), Eric Senn (LESTER), Eric Martin (LESTER)},
    journal={International Symposium on Circuits And Systems (2005) 680-683},
    year={2006},
    archivePrefix={arXiv},
    eprint={cs/0605143},
    primaryClass={cs.AR}
}