vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
<|reference_start|>vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems: The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands of modern autonomous systems require advanced heterogeneous embedded architectures. Such architectures must support high-performance and reliable execution of parallel tasks with different levels of criticality. Hardware-assisted virtualization is crucial for isolating applications concurrently executing these tasks under real-time constraints, but interrupt virtualization poses challenges in ensuring transparency to virtual guests while maintaining real-time system features, such as interrupt vectoring, nesting, and tail-chaining. Despite its rapid advancement to address virtualization needs for mixed-criticality systems, the RISC-V ecosystem still lacks interrupt controllers with integrated virtualization and real-time features, currently relying on non-deterministic, bus-mediated message-signaled interrupts (MSIs) for virtualization. To overcome this limitation, we present the design, implementation, and in-system assessment of vCLIC, a virtualization extension to the RISC-V CLIC fast interrupt controller. Our approach achieves 20x interrupt latency speed-up over the software emulation required for handling non-virtualization-aware systems, reduces response latency by 15% compared to existing MSI-based approaches, and is free from interference from the system bus, at an area cost of just 8kGE when synthesized in an advanced 16nm FinFet technology.<|reference_end|>
@article{zelioli2024vclic:,
    title={vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V
  Mixed-criticality Systems},
    author={Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff,
  Angelo Garofalo, Luca Benini},
    journal={arXiv preprint arXiv:2410.07798},
    year={2024},
    archivePrefix={arXiv},
    eprint={2410.07798},
    primaryClass={cs.AR}
}