A polynomial-time heuristic for Circuit-SAT
<|reference_start|>A polynomial-time heuristic for Circuit-SAT: In this paper is presented an heuristic that, in polynomial time and space in the input dimension, determines if a circuit describes a tautology or a contradiction. If the circuit is neither a tautology nor a contradiction, then the heuristic finds an assignment to the circuit inputs such that the circuit is satisfied.<|reference_end|>
@article{capasso2005a,
    title={A polynomial-time heuristic for Circuit-SAT},
    author={Francesco Capasso},
    journal={arXiv preprint arXiv:cs/0511071},
    year={2005},
    archivePrefix={arXiv},
    eprint={cs/0511071},
    primaryClass={cs.CC cs.DS}
}