Power-Area Efficient Serial IMPLY-based 4:2 Compressor Applied in Data-Intensive Applications
<|reference_start|>Power-Area Efficient Serial IMPLY-based 4:2 Compressor Applied in Data-Intensive Applications: The data transfer between a processor and memory has become a design bottleneck in data-intensive applications. Processing-In-Memory (PIM) is a practical approach to overcome the memory wall bottleneck. The 4:2 compressor is suitable for implementing the processor's crucial arithmetic circuits, including multiplier. Some area-efficient memristive structures, like Material Implication (IMPLY) in serial architecture, are compatible with the crossbar array. This paper proposes a serial memristive IMPLY-based 4:2 compressor, which is applied to present new 4-bit and 8-bit multipliers. The proposed circuits are evaluated regarding latency, area, and energy consumption. Compared to the existing serial compressor, the proposed 4:2 compressor's algorithm improves the area, energy consumption, and speed by 36%, 17%, and 15%, respectively. The proposed 4-bit and 8-bit multipliers are improved by 7.3% and 10%, respectively, regarding the latency, and reduced energy consumption by up to 12%, compared to the serial multiplier based on a 4:2 compressor with XOR/MUX design.<|reference_end|>
@article{bagheralmoosavi2024power-area,
    title={Power-Area Efficient Serial IMPLY-based 4:2 Compressor Applied in
  Data-Intensive Applications},
    author={Bahareh Bagheralmoosavi, Seyed Erfan Fatemieh, Mohammad Reza
  Reshadinezhad, Antonio Rubio},
    journal={arXiv preprint arXiv:2407.09980},
    year={2024},
    archivePrefix={arXiv},
    eprint={2407.09980},
    primaryClass={cs.ET cs.AR}
}