A Jammer-Mitigating 267 Mb/s 378 mm$^2$ 583 mW 32$\times$8 Multi-User MIMO Receiver in 22FDX
<|reference_start|>A Jammer-Mitigating 267 Mb/s 378 mm$^2$ 583 mW 32$\times$8 Multi-User MIMO Receiver in 22FDX: We present the first multi-user (MU) multiple-input multiple-output (MIMO) receiver ASIC that mitigates jamming attacks. The ASIC implements a recent nonlinear algorithm that performs joint jammer mitigation (via spatial filtering) and data detection (using a box prior on the data symbols). Our design supports 8 user equipments (UEs) and 32 basestation (BS) antennas, QPSK and 16-QAM with soft-outputs, and enables the mitigation of single-antenna barrage jammers and smart jammers. The fabricated 22 nm FD-SOI ASIC includes preprocessing, has a core area of 3.78 mm$^2$, achieves a throughput of 267 Mb/s while consuming 583 mW, and is the only existing design that enables reliable data detection under jamming attacks.<|reference_end|>
@article{bucheli2024a,
    title={A Jammer-Mitigating 267 Mb/s 3.78 mm$^2$ 583 mW 32$\times$8 Multi-User
  MIMO Receiver in 22FDX},
    author={Florian Bucheli and Oscar Casta~neda and Gian Marti and Christoph
  Studer},
    journal={arXiv preprint arXiv:2406.18149},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.18149},
    primaryClass={cs.AR eess.SP}
}