DFabric: Scaling Out Data Parallel Applications with CXL-Ethernet Hybrid Interconnects
<|reference_start|>DFabric: Scaling Out Data Parallel Applications with CXL-Ethernet Hybrid Interconnects: Emerging interconnects, such as CXL and NVLink, have been integrated into the intra-host topology to scale more accelerators and facilitate efficient communication between them, such as GPUs. To keep pace with the accelerator's growing computing throughput, the interconnect has seen substantial enhancement in link bandwidth, e.g., 256GBps for CXL 3.0 links, which surpasses Ethernet and InfiniBand network links by an order of magnitude or more. Consequently, when data-intensive jobs, such as LLM training, scale across multiple hosts beyond the reach limit of the interconnect, the performance is significantly hindered by the limiting bandwidth of the network infrastructure. We address the problem by proposing DFabric, a two-tier interconnect architecture. We address the problem by proposing DFabric, a two-tier interconnect architecture. First, DFabric disaggregates rack's computing units with an interconnect fabric, i.e., CXL fabric, which scales at rack-level, so that they can enjoy intra-rack efficient interconnecting. Second, DFabric disaggregates NICs from hosts, and consolidates them to form a NIC pool with CXL fabric. By providing sufficient aggregated capacity comparable to interconnect bandwidth, the NIC pool bridges efficient communication across racks or beyond the reach limit of interconnect fabric. However, the local memory accessing becomes the bottleneck when enabling each host to utilize the NIC pool efficiently. To the end, DFabric builds a memory pool with sufficient bandwidth by disaggregating host local memory and adding more memory devices. We have implemented a prototype of DFabric that can run applications transparently. We validated its performance gain by running various microbenchmarks and compute-intensive applications such as DNN and graph.<|reference_end|>
@article{zhang2024dfabric:,
    title={DFabric: Scaling Out Data Parallel Applications with CXL-Ethernet Hybrid
  Interconnects},
    author={Xu Zhang, Ke Liu, Yisong Chang, Ke Zhang, Mingyu Chen},
    journal={arXiv preprint arXiv:2409.05404},
    year={2024},
    archivePrefix={arXiv},
    eprint={2409.05404},
    primaryClass={cs.DC cs.AR cs.ET}
}