Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness
<|reference_start|>Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness: In safety-critical systems, timing accuracy is the key to achieving precise I/O control. To meet such strict timing requirements, dedicated hardware assistance has recently been investigated and developed. However, these solutions are often fragile, due to unforeseen timing defects. In this paper, we propose a robust and timing-accurate I/O co-processor, which manages I/O tasks using Execution Time Servers (ETSs) and a two-level scheduler. The ETSs limit the impact of timing defects between tasks, and the scheduler prioritises ETSs based on their importance, offering a robust and configurable scheduling infrastructure. Based on the hardware design, we present an ETS-based timing-accurate I/O schedule, with the ETS parameters configured to further enhance robustness against timing defects. Experiments show the proposed I/O control method outperforms the state-of-the-art method in terms of timing accuracy and robustness without introducing significant overhead.<|reference_end|>
@article{jiang2024hardware/algorithm,
    title={Hardware/Algorithm Co-design for Real-Time I/O Control with Improved
  Timing Accuracy and Robustness},
    author={Zhe Jiang, Shuai Zhao, Ran Wei, Xin Si, Gang Chen and Nan Guan},
    journal={arXiv preprint arXiv:2409.14779},
    year={2024},
    archivePrefix={arXiv},
    eprint={2409.14779},
    primaryClass={cs.AR}
}