Enabling full-speed random access to the entire memory on the A100 GPU
<|reference_start|>Enabling full-speed random access to the entire memory on the A100 GPU: We describe some features of the A100 memory architecture. In particular, we give a technique to reverse-engineer some hardware layout information. Using this information, we show how to avoid TLB issues to obtain full-speed random HBM access to the entire memory, as long as we constrain any particular thread to a reduced access window of less than 64GB.<|reference_end|>
@article{walker2024enabling,
    title={Enabling full-speed random access to the entire memory on the A100 GPU},
    author={Alden Walker},
    journal={arXiv preprint arXiv:2405.11425},
    year={2024},
    archivePrefix={arXiv},
    eprint={2405.11425},
    primaryClass={cs.PF cs.AR}
}