MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning
<|reference_start|>MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning: Technology mapping involves mapping logical circuits to a library of cells. Traditionally, the full technology library is used, leading to a large search space and potential overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune framework that addresses this challenge by utilizing reinforcement learning to make design-specific choices during cell selection. By learning from the environment, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality.   The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries and technology mappers. The experimental results demonstrate that MapTune achieves higher mapping accuracy and reducing delay/area across diverse circuit designs, technology libraries and mappers. The paper also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area trade-off. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0 and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 22.54\% among all different exploration settings in MapTune. The improvements are consistently remained for four different technologies (7nm, 45nm, 130nm, and 180 nm) and two different mappers.<|reference_end|>
@article{liu2024maptune:,
    title={MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning
  Guided Library Tuning},
    author={Mingju Liu, Daniel Robinson, Yingjie Li, Cunxi Yu},
    journal={arXiv preprint arXiv:2407.18110},
    year={2024},
    archivePrefix={arXiv},
    eprint={2407.18110},
    primaryClass={cs.AR cs.AI}
}