SAMIPS: A Synthesised Asynchronous Processor
<|reference_start|>SAMIPS: A Synthesised Asynchronous Processor: Miniaturisation and ever increasing clock speeds pose significant challenges to synchronous VLSI design with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Asynchronous logic promises to alleviate these challenges however its development and adoption has been hindered by the lack of mature design tools. Balsa is a response to this gap, encompassing a CSP-based asynchronous hardware description language and a framework for automatically synnthesising asynchronous circuits. This paper discusses SAMIPS, an asynchronous implementation of the MIPS microprocessor and the first full scale asynchronous microprocessor to be synthesised in Balsa. The objectives of the paper are twofold: first to provide a holistic description of SAMIPS and its components, the approach that it has been followed for the asynchronisation of MIPS and the innovative solutions that have been developed to address hazard challenges and a quantitative performance analysis of the system; secondly, to provide insights about the effectiveness of Balsa as a hardware description language and synthesis system.<|reference_end|>
@article{zhang2024samips:,
    title={SAMIPS: A Synthesised Asynchronous Processor},
    author={Qianyi Zhang and Georgios Theodoropoulos},
    journal={arXiv preprint arXiv:2409.20388},
    year={2024},
    archivePrefix={arXiv},
    eprint={2409.20388},
    primaryClass={cs.AR}
}