A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR
<|reference_start|>A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR: We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ultra-low latency interconnect (7-11 cycles), a modular Direct Memory Access engine provides an efficient link to a high bandwidth memory, such as HBM2E (98% peak bandwidth at 910GBps). The system achieves leading-edge energy efficiency at sub-ms latency in key 6G baseband processing kernels: Fast Fourier Transform (93 GOPS/W), Beamforming (125 GOPS/W), Channel Estimation (96 GOPS/W), and Linear System Inversion (61 GOPS/W), with only 9% data movement overhead.<|reference_end|>
@article{zhang2024a,
    title={A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for
  Low-Latency 6G-SDR},
    author={Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro
  Vanelli-Coralli, Luca Benini},
    journal={arXiv preprint arXiv:2408.08882},
    year={2024},
    archivePrefix={arXiv},
    eprint={2408.08882},
    primaryClass={cs.DC}
}