An Open-Source Fast Parallel Routing Approach for Commercial FPGAs
<|reference_start|>An Open-Source Fast Parallel Routing Approach for Commercial FPGAs: In the face of escalating complexity and size of contemporary FPGAs and circuits, routing emerges as a pivotal and time-intensive phase in FPGA compilation flows. In response to this challenge, we present an open-source parallel routing methodology designed to expedite routing procedures for commercial FPGAs. Our approach introduces a novel recursive partitioning ternary tree to augment the parallelism of multi-net routing. Additionally, we propose a hybrid updating strategy for congestion coefficients within the routing cost function to accelerate congestion resolution in negotiation-based routing algorithms. Evaluation on public benchmarks from the FPGA24 routing contest demonstrates the efficacy of our parallel router. It achieves a 2x speedup compared to the academic serial router RWRoute. Furthermore, when compared to the industry-standard tool Vivado, our approach not only delivers a 2x acceleration but also yields a notable 31% enhancement in critical-path wirelength.<|reference_end|>
@article{zang2024an,
    title={An Open-Source Fast Parallel Routing Approach for Commercial FPGAs},
    author={Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F.Y. Young},
    journal={arXiv preprint arXiv:2407.00009},
    year={2024},
    archivePrefix={arXiv},
    eprint={2407.00009},
    primaryClass={cs.DC cs.NI}
}