PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC
<|reference_start|>PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC: This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board.<|reference_end|>
@article{ribeiro2024pefsl:,
    title={PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA
  SoC},
    author={Lucas Grativol Ribeiro, Lubin Gauthier, Mathieu Leonardon, J'er'emy
  Morlier, Antoine Lavrard-Meyer, Guillaume Muller, Virginie Fresse, Matthieu
  Arzel},
    journal={ISCAS 2024 : IEEE International Symposium on Circuits and Systems,
  May 2024, Singapore, Singapore},
    year={2024},
    archivePrefix={arXiv},
    eprint={2404.19354},
    primaryClass={cs.AR cs.LG}
}