Energy efficiency optimization of task-parallel codes on asymmetric architectures
<|reference_start|>Energy efficiency optimization of task-parallel codes on asymmetric architectures: We present a family of policies that, integrated within a runtime task scheduler (Nanox), pursue the goal of improving the energy efficiency of task-parallel executions with no intervention from the programmer. The proposed policies tackle the problem by modifying the core operating frequency via DVFS mechanisms, or by enabling/disabling the mapping of tasks to specific cores at selected execution points, depending on the internal status of the scheduler. Experimental results on an asymmetric SoC (Exynos 5422) and for a specific operation (Cholesky factorization) reveal gains up to 29% in terms of energy efficiency and considerable reductions in average power.<|reference_end|>
@article{costero2024energy,
    title={Energy efficiency optimization of task-parallel codes on asymmetric
  architectures},
    author={Luis Costero, Francisco D. Igual, Katzalin Olcoz, Francisco Tirado},
    journal={arXiv preprint arXiv:2402.06319},
    year={2024},
    doi={10.1109/HPCS.2017.67},
    archivePrefix={arXiv},
    eprint={2402.06319},
    primaryClass={cs.DC}
}