Occamy: A 432-Core 281 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
<|reference_start|>Occamy: A 432-Core 281 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET: We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit) SIMD FP data. Occamy features 48 clusters of RISC-V cores with custom extensions, two 64-bit host cores, and a latency-tolerant multi-chiplet interconnect and memory system with 32 GiB of HBM2E. It achieves leading-edge utilization on stencils (83 %), sparse-dense (42 %), and sparse-sparse (49 %) matrix multiply.<|reference_end|>
@article{paulin2024occamy:,
    title={Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet,
  Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra
  Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET},
    author={Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus Cavalcante, Tim
  Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca
  Colagrande, Gianmarco Ottavi, Frank K. G"urkaynak, Davide Rossi, Luca Benini},
    journal={arXiv preprint arXiv:2406.15068},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.15068},
    primaryClass={cs.AR}
}