Efficient Fault Detection Architectures for Modular Exponentiation Targeting Cryptographic Applications Benchmarked on FPGAs
<|reference_start|>Efficient Fault Detection Architectures for Modular Exponentiation Targeting Cryptographic Applications Benchmarked on FPGAs: Whether stemming from malicious intent or natural occurrences, faults and errors can significantly undermine the reliability of any architecture. In response to this challenge, fault detection assumes a pivotal role in ensuring the secure deployment of cryptosystems. Even when a cryptosystem boasts mathematical security, its practical implementation may remain susceptible to exploitation through side-channel attacks. In this paper, we propose a lightweight fault detection architecture tailored for modular exponentiation, a building block of numerous cryptographic applications spanning from classical cryptography to post quantum cryptography. Based on our simulation and implementation results on ARM Cortex-A72 processor, and AMD/Xilinx Zynq Ultrascale+, and Artix-7 FPGAs, our approach achieves an error detection rate close to 100%, all while introducing a modest computational overhead of approximately 7% and area overhead of less than 1% compared to the unprotected architecture. To the best of our knowledge, such an approach benchmarked on ARM processor and FPGA has not been proposed and assessed to date.<|reference_end|>
@article{aghapour2024efficient,
    title={Efficient Fault Detection Architectures for Modular Exponentiation
  Targeting Cryptographic Applications Benchmarked on FPGAs},
    author={Saeed Aghapour, Kasra Ahmadi, Mehran Mozaffari Kermani, Reza
  Azarderakhsh},
    journal={arXiv preprint arXiv:2402.18033},
    year={2024},
    archivePrefix={arXiv},
    eprint={2402.18033},
    primaryClass={cs.CR}
}