Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers
<|reference_start|>Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers: This paper presents a comprehensive study and implementations onto FPGA device of an Expectation Propagation (EP)-based receiver for QPSK, 8-PSK, and 16-QAM. To the best of our knowledge, this is the first for this kind of receiver. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture.<|reference_end|>
@article{schilling2024hardware,
    title={Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based
  Receivers},
    author={Ian Fischer Schilling (IMS), Serdar Sahin, Camille Leroux (IMS),
  Antonio Maria Cipriano, Christophe Jego (IMS)},
    journal={arXiv preprint arXiv:2406.07934},
    year={2024},
    archivePrefix={arXiv},
    eprint={2406.07934},
    primaryClass={cs.AR eess.SP}
}