Safety Verification and Navigation for Autonomous Vehicles based on Signal Temporal Logic Constraints
<|reference_start|>Safety Verification and Navigation for Autonomous Vehicles based on Signal Temporal Logic Constraints: The software architecture behind modern autonomous vehicles (AV) is becoming more complex steadily. Safety verification is now an imminent task prior to the large-scale deployment of such convoluted models. For safety-critical tasks in navigation, it becomes imperative to perform a verification procedure on the trajectories proposed by the planning algorithm prior to deployment. Signal Temporal Logic (STL) constraints can dictate the safety requirements for an AV. A combination of STL constraints is called a specification. A key difference between STL and other logic constraints is that STL allows us to work on continuous signals. We verify the satisfaction of the STL specifications by calculating the robustness value for each signal within the specification. Higher robustness values indicate a safer system. Model Predictive Control (MPC) is one of the most widely used methods to control the navigation of an AV, with an underlying set of state and input constraints. Our research aims to formulate and test an MPC controller, with STL specifications as constraints, that can safely navigate an AV. The primary goal of the cost function is to minimize the control inputs. STL constraints will act as an additional layer of constraints that would change based on the scenario and task on hand. We propose using sTaliro, a MATLAB-based robustness calculator for STL specifications, formulated in a receding horizon control fashion for an AV navigation task. It inputs a simplified AV state space model and a set of STL specifications, for which it constructs a closed-loop controller. We test out our controller for different test cases/scenarios and verify the safe navigation of our AV model.<|reference_end|>
@article{parameshwaran2024safety,
    title={Safety Verification and Navigation for Autonomous Vehicles based on
  Signal Temporal Logic Constraints},
    author={Aditya Parameshwaran and Yue Wang},
    journal={arXiv preprint arXiv:2409.10689},
    year={2024},
    archivePrefix={arXiv},
    eprint={2409.10689},
    primaryClass={eess.SY cs.RO cs.SY}
}