Using a Performance Model to Implement a Superscalar CVA6
<|reference_start|>Using a Performance Model to Implement a Superscalar CVA6: A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40% on CoreMark.<|reference_end|>
@article{allart2024using,
    title={Using a Performance Model to Implement a Superscalar CVA6},
    author={C^ome Allart, Jean-Roch Coulon, Andr'e Sintzoff, Olivier Potin,
  Jean-Baptiste Rigaud},
    journal={arXiv preprint arXiv:2410.01442},
    year={2024},
    archivePrefix={arXiv},
    eprint={2410.01442},
    primaryClass={cs.AR}
}