A Memory Aware High Level Synthesis Too
<|reference_start|>A Memory Aware High Level Synthesis Too: We introduce a new approach to take into account the memory architecture and the memory mapping in High- Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.<|reference_end|>
@article{corre2006a,
    title={A Memory Aware High Level Synthesis Too},
    author={Gwenol'e Corre (LESTER), Nathalie Julien (LESTER), Eric Senn
  (LESTER), Eric Martin (LESTER)},
    journal={International Symposium on VLSI (2004) 279-280},
    year={2006},
    archivePrefix={arXiv},
    eprint={cs/0605144},
    primaryClass={cs.AR}
}