LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
<|reference_start|>LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust: Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous potential, the community must also carefully consider the related security risks and the need for building trust into using LxMs for chip design. First, we review the recent surge of using LxMs for chip design in general. We cover state-of-the-art works for the automation of hardware description language code generation and for scripting and guidance of essential but cumbersome tasks for electronic design automation tools, e.g., design-space exploration, tuning, or designer training. Second, we raise and provide initial answers to novel research questions on critical issues for security and trustworthiness of LxM-powered chip design from both the attack and defense perspectives.<|reference_end|>
@article{wang2024llms,
    title={LLMs and the Future of Chip Design: Unveiling Security Risks and
  Building Trust},
    author={Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur
  Sinanoglu},
    journal={arXiv preprint arXiv:2405.07061},
    year={2024},
    archivePrefix={arXiv},
    eprint={2405.07061},
    primaryClass={cs.LG cs.AR cs.CR}
}