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Copying register value in Verilog behavioral modelling
I'm working to design encryption module in Verilog using behavioral modelling approach, but i'm stuck in passing register value to Data_out port. I'm making little mistake to copy register p value in Data_out port. Testbench is also attached. expected output of the module should be Data_out = (Data_in + Key) MOD 26. but we can't use % operator because of systhesis issue.
Your answer will be valuable for me.
module encription(Start,Clk,Reset,Data_In, Key,Data_out,Done);

parameter M='d26;
parameter S0=0, S1=1, S2= 2;
input Clk,Reset,Start;
input [4:0] Data_In,Key;
output reg [4:0] Data_out;
output reg Done;
 reg [1:0] state;
 reg [4:0] p,q,r,s;
 
 always @ (posedge Clk)
 begin
 r <= Data_In;
 s <= Key;
 end
 
 
 always @ (posedge Clk )
    begin
      if(Reset=='b0)
        begin
            Done <= 1'b0;
            p <= M;
        end
        else if (Reset == 'b1)
        case (state)
         S0: 
         if (Start) begin
         q <= r + s;
         
         state <= S1;
         end
         S1: 
         if (p >= q) begin
         p <= p - q;
         state <= S2;
         end
         S2:
         begin
               Data_out <= p;
               Done <= 1'b1;
               Done <= 1'b0;
               end
               default:
               state <= S0;
endcase

end
endmodule



module Encryption_tb();

reg Clk,Reset,Start;
reg [4:0] Data_In,Key;
wire [4:0] Data_out;
wire [4:0] q;
wire Done;

  encription DUT(Start,Clk,Reset,Data_In, Key,Data_out,Done);
initial
    begin
    Clk = 0;
    forever #5 Clk=~Clk;
    end
    
    initial
    begin
        #10 Start = 'b1;  Data_In = 'b000111; Key = 'b01110;
    #10 Start = 'b1;  Data_In = 'b000101; Key = 'b01100;
    #10 Start = 'b1;  Data_In = 'b000001; Key = 'b00110;
    #10 Reset = 'b1; Start = 'b1;
    //#10 Reset = 'b0;
    #10 Start = 'b1;  Data_In = 'b000111; Key = 'b01110;
    #10 Start = 'b1;  Data_In = 'b000101; Key = 'b01100;
    #10 Start = 'b1;  Data_In = 'b000001; Key = 'b00110;
    #10 $finish;
    end
endmodule


I want to implement vingere cipher encryption algorithm and equation looks like that, Data_out = (Data_In + Key) MOD 26.

actually, what exactly is your question? you did not ask one.

The question seems to be: "Why does this (Data_in + Key)MOD 26 with registered output module not produce (Data_in + Key) MOD 26"? Please confirm.

This does not need a state machine just some flops.
RTL:
module encription(Start,Clk,Reset,Data_In, Key,Data_out,Done);

parameter M='d26;
parameter S0=0, S1=1, S2= 2;
input Clk,Reset,Start;
input [4:0] Data_In,Key;
output reg [4:0] Data_out;
output reg Done;
  
  reg [6:0] sum;

assign sum = Data_In + Key;
 
 always @ (posedge Clk )
    begin
      if(Reset=='b1)
        begin
            Data_out <= 0;
            Done <= 0;         
        end
        else
          begin
          if(sum < M)
            Data_out <= sum;
            else
              if(sum < 2*M)
                Data_out <= sum - M;
               else
                 Data_out <= sum - 2*M ;
            
            Done <= Start;
          end
    end

endmodule    

Testbench with meaningful vectors:
    module Encryption_tb();

reg Clk,Reset,Start;
reg [4:0] Data_In,Key;
wire [4:0] Data_out;
wire [4:0] q;
wire Done;

  encription DUT(Start,Clk,Reset,Data_In, Key,Data_out,Done);
  
  
initial
    begin 
    Clk = 0;
    forever #5 Clk=~Clk;
    end
    
    initial
    begin :initial_block
      
      $monitor("Data_In = %d,Key = %d, Data_out = %d",Data_In,Key,Data_out);
      
    Reset = 1;
    #20 Reset = 0;
      
    #10;
      
    #1;
    Start = 1;
      for(int i = 0; i < 30; i++)
        begin
          @ (posedge Clk);
          #1;
          Key = i;
          Data_In = i;
        end

    #10 $finish;
    end :initial_block
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars;
    end
  
endmodule    

Some of the outputs (note the answer is delayed by 1 clk because of the flops)
Data_In =  0,Key =  0, Data_out =  0
Data_In =  1,Key =  1, Data_out =  0
Data_In =  1,Key =  1, Data_out =  2
Data_In =  2,Key =  2, Data_out =  2
Data_In =  2,Key =  2, Data_out =  4
Data_In =  3,Key =  3, Data_out =  4
Data_In =  3,Key =  3, Data_out =  6
Data_In =  4,Key =  4, Data_out =  6
Data_In =  4,Key =  4, Data_out =  8
Data_In =  5,Key =  5, Data_out =  8
Data_In =  5,Key =  5, Data_out = 10
Data_In =  6,Key =  6, Data_out = 10
Data_In =  6,Key =  6, Data_out = 12
Data_In =  7,Key =  7, Data_out = 12
Data_In =  7,Key =  7, Data_out = 14
Data_In =  8,Key =  8, Data_out = 14
Data_In =  8,Key =  8, Data_out = 16
Data_In =  9,Key =  9, Data_out = 16
Data_In =  9,Key =  9, Data_out = 18
Data_In = 10,Key = 10, Data_out = 18
Data_In = 10,Key = 10, Data_out = 20
Data_In = 11,Key = 11, Data_out = 20
Data_In = 11,Key = 11, Data_out = 22
Data_In = 12,Key = 12, Data_out = 22
Data_In = 12,Key = 12, Data_out = 24
Data_In = 13,Key = 13, Data_out = 24
Data_In = 13,Key = 13, Data_out =  0
Data_In = 14,Key = 14, Data_out =  0
Data_In = 14,Key = 14, Data_out =  2
Data_In = 15,Key = 15, Data_out =  2
Data_In = 15,Key = 15, Data_out =  4
Data_In = 16,Key = 16, Data_out =  4
Data_In = 16,Key = 16, Data_out =  6
Data_In = 17,Key = 17, Data_out =  6
Data_In = 17,Key = 17, Data_out =  8
Data_In = 18,Key = 18, Data_out =  8


I see a couple issues.

The only way to get out of S1 in your state machine is if "if (p >= q)". If p is already less than Q, you are stuck in that state forever.

In your testbench, you are giving time between starts for your state
machine to run.


A few suggestions:
Better indentation make it easier to see what is inside a code block: Ex:
        S1: 
          if (p >= q) begin
             p <= p - q;
             state <= S2;
          end

In your testbench, instead of using #10 to define the sequence of stimulus, use  @(posedge Clk), that way if your clock frequency changes or some other length delay is used in the TB, things will still line up with the clock.
Use @(Done) to wait for results.
I'm also curious, what synthesis tool you are using that doesn't support %?
