Stack Exchange
Adder subtractor VHDL issue
I currently have this code, but it is not properly working; I'll put the example in the next image. IT has to be an adder subtractor 4 bits support, and it should use complement of 2.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity soma4 is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           CIN : in STD_LOGIC;
           S : out STD_LOGIC_VECTOR (3 downto 0);
           COUT : out STD_LOGIC);
end soma4;

architecture Behavioral of soma4 is

component sum1 is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           s : out STD_LOGIC;
           cout : out STD_LOGIC);
end component;

signal c0, c1, c2, c3: STD_LOGIC;
signal TMPP: STD_LOGIC_VECTOR(3 downto 0);

component twocomplement is
    Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
           Y : out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin

process(CIN)
begin
if(CIN = '1') then
TMPP <= std_logic_vector(unsigned(not B) + 1);   
else   
TMPP <= B;                    
end if;
end process;

soma1: sum1 port map (a=>A(0), b=>TMPP(0), cin=>CIN, s=>S(0), cout =>c0);
soma2: sum1 port map (a=>A(1), b=>TMPP(1), cin=>c0, s=>S(1), cout =>c1);
soma3: sum1 port map (a=>A(2), b=>TMPP(2), cin=>c1, s=>S(2), cout =>c2);
soma4: sum1 port map (a=>A(3), b=>TMPP(3), cin=>c2, s=>S(3), cout =>c3);
COUT <= CIN XOR c3;
end Behavioral;

sum1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sum1 is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           s : out STD_LOGIC;
           cout : out STD_LOGIC);
end sum1;

architecture Behavioral of sum1 is

begin
    s <= a xor b xor cin;
    cout <= (a and b) or (b and cin) or (a and cin);
end Behavioral;

and finally, the test table
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_soma4 is
--  Port ( );
end tb_soma4;

architecture Behavioral of tb_soma4 is

component soma4 is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           CIN : in STD_LOGIC;
           S : out STD_LOGIC_VECTOR (3 downto 0);
           COUT : out std_logic);
end component;

signal s_A, s_B, s_S, T: STD_LOGIC_VECTOR(3 downto 0);
signal subtracao, overflow: STD_LOGIC;

begin

uuu: soma4 port map(A=> s_A,
 B=> s_B, cin => subtracao, 
 s=>s_S, cout=> overflow);

stimulus: process
begin
s_A<="0011"; s_B<="0010"; subtracao<='1';
wait for 10ns;

end process;

end Behavioral;

subtracao means subtract, and for some reason, the result should be 1, right? That's where the problem is. The result should be 1, but it's giving me two for some reason.  Here is the table run:

Ignore T. I was trying to use it as a DEBUG way, but the complement of two seems to be correct.  I don't know what's wrong.

Consider how you are adding the two's complement of b to subtract it from a. TMPP <= std_logic_vector(unsigned(not B) + 1); That looks like the way to provide a two's complement of b, but the invert and increment is the size of the rest of the soma4 component and you already using the soma1 cin input to increment. Only incrementing once gives you the right answer and eliminates the need for a numeric_std unsigned "+". How would you increment with a separate cin and subtracao allowing you to gang soma4 instances? Component twocomplement isn't used.

As this appears to be a homework problem (and one very similar to a lab I used to teach) I don't want to get into too much detail...
However, I note that you've declared a component called twoscomplement inside your soma4 entity. Where is the associated entity for twoscomplement? How many do you need? And how have you mapped its ports?
(As a side note, I'd question any structural implementation of a VHDL adder that uses the + operator, or for that matter, the process keyword at all, and I'd strongly recommend you look very carefully at what your process is actually doing...)

I currently live in Brasil and study in UnB, I am sure it was not the lab you teach to, as well as my teacher tried to help but he don't seem to care that much to be honest, since he looked at it said everything was right and did not find what's wrong with the code.

As of about the twocomplement, it's just waste of lines there, I was using it to keep the two complement method outside of this vhd file, so the two complement is now generated by:
TMPP <= std_logic_vector(unsigned(not B) + 1);   

As of the process, I am using it that way becasue I cannot have an IF statement if not using the process, or at least it gives me syntax errors every where..

You should definitely not need an if statement in an adder-subtractor. What signal does your adder-subtractor use to determine if it is supposed to add or subtract? What hardware circuit uses such a binary signal to select between two options?

You may have also been taught about a logic operation that selectively inverts a signal. When the 'invert' signal is high, the input switches, and when it's low, the input stays the same. Much easier to put your B vector through a set of such "selective-inverters" rather than having an if statement...

Hey, its the CIN, i don't know, its a simple thing using a basys3 board

What does CIN stand for?

It's just random variable naming. like foreachs with i or k, CIN is the subtract or add.

Are you sure about that? Where is CIN being used in your design?

... peculiar random downvote on a weeks-old answer. Hope it was worth it (?)
