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Near text "process"; expecting "if" VHDL
Here is my code for paralel in serial out shif register. I get error Near text "process"; expecting "if" and i cant fix this.
Here is my code
library ieee;
use ieee.std_logic_1164.all;

entity shiftreg is
port(
sl:in std_logic;
clk:in std_logic;
data:in std_logic_vector(3 downto 0);
q:out std_logic
);
end shiftreg;

architecture myarch of shiftreg is
signal q1:std_logic_vector(3 downto 0);
begin
process(sl,clk,data)
begin
    if(sl='0') then
        q1<=data;
    else if(sl='1' and rising_edge(clk)) then
        q<=q1(3);
        q1(3)<=q1(2);
        q1(2)<=q1(1);
        q1(1)<=q1(0);
        q1(0)<="0";
    end if;
end process;
end myarch;


elsif . if after else is another branch. so you need to use end if after the statements. Saying that, you really need to read about the synchronous process, clocks, resets etc. if else

Thank you! I have VHDL this semester and i just started learning it. I couldnt figure this out. Im really tired xD

Basic VHDL is great

Thank you so much!
