A heterogeneous processor architecture for integrating a convolutional neural network (CNN) and a recurrent neural network (RNN) into a single high-performance, low-power chip in a neural network processor architecture, the heterogeneous processor architecture includes: an on-chip integrated circuit including a CNN operator for processing the CNN, an RNN operator for processing the RNN, an operation controller for performing control, a memory for storing data which is to be used by the operators, an interface for externally exchanging data, and a data bus through which data moves between constituent elements, wherein a fully-connected layer constituting the CNN performs data processing by sharing the RNN operator.
Heterogeneous processor architecture for integrating CNN and RNN into single high-performance, low-power chip