A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding binary and duo-binary code. The reconfigurable MAP calculation circuit comprises M memory banks for storing N input data samples. Each input data sample comprises systematic data, non-interleaved parity data and interleaved parity data. The N input data samples are divided into M logical blocks and input data samples from each logical block are stored in each of the M memory banks. The reconfigurable MAP calculation circuit comprises M processing units. Each processing unit processes one of the M logical blocks. The reconfigurable MAP calculation circuit comprises a communication switch for coupling the M processing units to the M memory banks such that the M processing units simultaneously access input data samples from each of the M logical blocks in each of the M memory banks without collision.
Apparatus and method for a collision-free parallel turbo decoder in a software-defined radio system