PURPOSE: To constitute a hardware architecture by a smaller neuron network by combining a digital multiplier, a digital adder and a register, etc., to a neuron. CONSTITUTION: The input terminals of many neuron units in the same constitution constituted of the plural neurons are connected through respective input registers REGE to network input terminals EN. The output terminals are connectable through multiplexers MUX and output registers REGA to network output terminals AN at the different points of time. Also, the weight value of neuron connection and threshold value O signals for the evaluation of input signals are supplied to an auxiliary input terminal. Thus, this network architecture for enabling the use of the small neuron unit formable by a present technique is obtained.
ARTIFICIAL NEURON CIRCUIT NETWORK ARCHITECTURE