The circuit comprises a first and a second circuit part (CZ, SZ) which include an evaluation circuit (M1, M2, M3, M4, M7; M1', M2', M3', M4', M7') and elements (M5, M5', M6, M6') for an addition of weighted input sizes, respectively. A partial sum is formed in the first circuit part (CZ), and the partial sum is supplied to at least one of the adding elements of the second circuit part. The partial sum signal controls the channels of at least two neuron MOS transistors (M6, M6') in at least two circuit parts simultaneously over a common polysilicon area.
Threshold logic circuits with limited area