A compute-in-memory architecture for p learning uses a combination of neural circuits in complementary metal-oxide semiconductor (CMOS) technology, and synaptic conductance crossbar arrays in resistive nonvolatile random-access memory (RRAM) technology. The crossbar memory structures store the weight parameters of the deep neural network in the conductances of the RRAM synapse elements, which make interconnects between lines of neurons of consecutive layers in the network at the crossbar intersection points.
COMPUTE-IN-MEMORY ARCHITECTURE FOR NEURAL NETWORKS