A neural network computation circuit that outputs output data (y) according to a result of a multiply-accumulate operation between input data (x<sub>0</sub>to x<sub>n</sub>) and connection weight coefficients (w<sub>0</sub>to w<sub>n</sub>), the neural network computation circuit includes computation units (PU0 to PUn) in each of which a non-volatile semiconductor memory element (RP) and a cell transistor (T0) are connected in series between data lines (BL0, SL0), a non-volatile semiconductor memory element (RN) and a cell transistor (T1) are connected in series between data lines (BL1, SL1), and gates of the transistors (T0, T1) are connected to word lines (WL0 to WLn). The connection weight coefficients (w<sub>0</sub>to w<sub>n</sub>) are stored into the non-volatile semiconductor memory elements (RP, RN). A word line selection circuit (30) places the word lines (WL0 to WLn) in a selection state or a non-selection state according to the input data (x<sub>0</sub>to x<sub>n</sub>). A determination circuit (50) determines current values flowing in data lines (BL0, BL1) to output output data (y).
NEURAL NETWORK ARITHMETIC CIRCUIT USING NON-VOLATILE SEMICONDUCTOR MEMORY ELEMENT