Embodiments are directed towards a system on chip (SoC, 110) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus (166), a plurality of addressable memory arrays coupled to the system bus (166), at least one applications processor core (128) coupled to the system bus (166), and a configurable accelerator framework (400) coupled to the system bus. The configurable accelerator framework (400) is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus (166), wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework (400) to execute the DCNN.
DEEP CONVOLUTIONAL NETWORK HETEROGENEOUS ARCHITECTURE SYSTEM AND DEVICE