A synaptic integration circuit for a neuromorphic chip comprising a resistive memory synapse which has an activation terminal to receive a presynaptic action signal and a propagation terminal intended to be connected to the circuit for transmitting a synaptic output signal which depends on the resistance of the memory. The circuit comprises an accumulator of the synaptic output signal, a comparator configured to emit a postsynaptic spike in case of the crossing of a threshold (Vm) by the accumulated output signal. It further comprises a control unit configured, when a presynaptic action signal is applied on the activation terminal, to impose a conductance modification voltage on the synapse by controlling the application of a postsynaptic action signal (VBLset, VBLreset) on the propagation terminal.
CIRCUIT NEURONAL APTE À METTRE EN OEUVRE UN APPRENTISSAGE SYNAPTIQUE