A neuromorphic computing circuit based on a multi-bit parallel binary synaptic array, comprising a neural axon module, a multi-bit parallel binary RRAM synaptic array, a time division multiplexer, a plurality of integrators, and one shared successive approximation register analog-to-digital converter. The neural axon module comprises two basic units, namely a timing scheduler and an adder; the timing scheduler is used for arranging the timing of a signal, so that an input signal is sequentially input into the multi-bit parallel binary RRAM synaptic array by means of a dendritic priority strategy; the adder is used for expanding the array scale, and when a configured neural network input layer is greater than the input of one RRAM array, the adder is used for adding the computing results of the plurality of arrays to obtain the output of the network layer. Compared with a current system, the circuit has the advantages of high precision and low power consumption, can be configured into most deep neural network applications, and is particularly suitable for being deployed in edge computing devices with high energy consumption requirements.
NEUROMORPHIC COMPUTING CIRCUIT BASED ON MULTI-BIT PARALLEL BINARY SYNAPTIC ARRAY