PURPOSE: To make all of given words addressable to improve the compactness of integrated circuit and alignment speed by activating all the related switches for each bit of the words by using single lines which carry single-mode selective signals. CONSTITUTION: Array 10 supplies four synaptic coefficients C11 -C14 to the bus of the array 10 for neuron 1, and in this case these synaptic coefficients reach both the neuron states V1 -V4 accumulated in a shift register 121 constituting a neuron state memory and multipliers 501 -504 , respectively. These multipliers are connected to a multiplier tree 51 which reports the result S to neuron 1. This array reports the synaptic coefficients supplied through another different array to a neuron 2. Before executing the calculation of disassembly step, the shift register 121 circulates the neuron states for correct assignment of each neuron state in the synaptic coefficients. With this, an array which can collect neuron states at high speed and compactly is realized.
DATA CELL ARRAY AND NERVE NETWORK SYSTEM USING THE SAME