AMD has its own announcements about power consumption for the International Solid-State Circuits Conference this week. A few days ago we reported on Intel's success integrating Wi-Fi transceivers into the CPU to reduce power consumption. Cyclos Semiconductor discussed their resonant clock mesh (RCM) technology which reduces waste energy dissipated when keeping the chip synchronized. AMD announced that this technology would be introduced in their upcoming Piledriver APUs and Opteron processors.
Excuse me, good sir. Do you have the time?
Tom's Hardware put up an article to discuss the announcement with a small explanation of what is going on.
Inductive-capacitive oscillators are leveraged in mesh-based high-performance clock distribution networks to deliver "high-precision timing while dissipating almost no power." In effect, RCM promises to recycle clock power to enable lower power consumption or higher clock speeds.
For a more specific explanation, I turned to Josh Walrath. Chips are timed by a clock signal -- any overclocker will attest to that. Over time chips became larger and more complex which of course requires a larger and more complex system to propagate the clock signal through. Slowly but surely those circuits became large enough that the energy they dissipate simply by being powered becomes less and less negligible.
What Cyclos contributes is cleverly using inductor-capacitor circuits to keep the energy stored in the clock circuit mesh. With more of the energy stored in the mesh it just requires a small energy shove to trigger the signal after the initial charge. Also, less energy lost also means less heat dissipation which helps your battery as well as your heatsink.
Cyclos Semiconductor states that power savings are between 5 to 30 percent dependent on the chip design. In AMD's case, they expect approximately 5 to 10 percent power savings in their Piledriver implementation. While AMD is the first implementation of Cyclos' technology, it is not known what Intel currently has done or will potentially do to solve the problem.
While this is great news to hear as to increase APU efficiency and decrease energy loss/dissipation. Will this be implemented on the Piledrive APU chip or will it be included on the Piledrive CPU as well? I apologize for my stupid question. Is there still going to be a Piledrive CPU on the AM3+ socket? or was Bulldozer the last?
I would expect it to be implemented on the AM3+ Piledriver core. And yes, there should be Piledriver for AM3+ sometime in Q3.