The Complete Verilog Book
Vivek Sagdeo
Kluwer Academic Publishers
The Verilog hardware description language provides the ability  to describe digital and analog systems for design concepts and  implementation. It was developed originally at Gateway Design and  implemented there. Now it is an open standard of IEEE and Open Verilog  International and is supported by many tools and processes. The  Complete Verilog Book introduces the language and describes it  in a comprehensive manner.   In The Complete Verilog Book, each feature of the language is  described using semantic introduction, syntax and examples. A chapter  on semantics explains the basic concepts and algorithms that form the  basis of every evaluation and every sequence of evaluations that  ultimately provides the meaning or full semantics of the language.    The Complete Verilog Book takes the approach that Verilog is not  only a simulation language or a synthesis language or a formal method  of describing design, but is a totality of all these and covers many  aspects not covered before but which are essential parts of any design  process using Verilog. The Complete Verilog Book starts with a  tutorial introduction. It explains the data types in Verilog HDL, as  the object-oriented world knows that the language-constructs and data  types are equally important parts of a language. The Complete  Verilog Book explains the three views, behavioral, RTL and  structural and then describes features in each of these views.   The Complete Verilog Book keeps the reader abreast of current  developments in the Verilog world such as Verilog-A, cycle simulation,  SD, and DCL, and uses IEEE 1364 syntax.   The Complete Verilog Book will be useful to all those who want  to learn Verilog HDL and to explore its various facets.