The VLSI Handbook
Wai-Kai Chen
CRC/Taylor & Francis
Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and other resources-such as software, databases, standards, and seminars-points toward more in-depth information.<br>Section I VLSI Technology<br>Bipolar Technology<br>CMOS/BiCMOS Technology<br>Silicon-on-Insulator Technology<br>SiGe HBT Technology<br>Silicon Carbide Technology<br>Passive Components<br>Power IC Technologies<br>Microelectronics Packaging<br>Multichip Module Technologies<br>Section II Devices and Their Models<br>Bipolar Junction Transistor Circuits<br>RF Passive IC Components<br>CMOS Fabrication<br>Analog Circuit Simulation<br>Interconnect Modeling and Simulation<br>Section III Low Power Electronics and Design<br>System-Level Power Management: An Overview<br>Communication-Based Design for Nanoscale SoCs<br>Power-Aware Architectural Synthesis<br>Dynamic Voltage Scaling for Low-Power Hard Real-Time Systems<br>Low-Power Microarchitecture Techniques and Compiler Design Techniques<br>Architecture and Design Flow Optimizations for Power-Aware FPGAs<br>Technology Scaling and Low-Power Circuit Design<br>Section IV Amplifiers<br>CMOS Amplifier Design<br>Bipolar Junction Transistor Amplifiers<br>High-Frequency Amplifiers<br>Operational Transconductance Amplifiers<br>Section V Logic Circuits<br>Expressions of Logic Functions<br>Basic Theory of Logic Functions<br>Simplification of Logic Expressions<br>Binary Decision Diagrams<br>Logic Synthesis with AND and OR Gates in Two Levels<br>Sequential Networks 32 Logic Synthesis with AND and OR Gates in Multi-Levels<br>Logic Properties of Transistor Circuits<br>Logic Synthesis with NAND (or NOR) Gates in Multi-Levels<br>Logic Synthesis with a Minimum Number of Negative Gates<br>Logic Synthesizer with Optimizations in Two Phases<br>Logic Synthesizer by the Transduction Method<br>Emitter-Coupled Logic<br>CMOS<br>Pass Transistors<br>Adders<br>Multipliers<br>Dividers<br>Full-Custom and Semi-Custom Design<br>Programmable Logic Devices<br>Gate Arrays<br>Field-Programmable Gate Arrays<br>Cell-Library Design Approach<br>Comparison of Different Design Approaches<br>Section VI Memory, Registers and System Timing<br>System Timing<br>ROM/PROM/EPROM 52 SRAM<br>Embedded Memory<br>Flash Memories<br>Dynamic Random Access Memory<br>Content-Addressable Memory<br>Low-Power Memory Circuits<br>Section VII Analog Circuits<br>Nyquist-Rate ADC and DAC<br>Oversampled Analog-to-Digital and Digital-to-Analog Converters<br>RF Communication Circuits<br>PLL Circuits<br>Switched-Capacitor Filters<br>Section VIII Microprocessor and ASIC<br>Timing and Signal Integrity Analysis<br>Microprocessor Design Verification<br>Microprocessor Layout Method<br>Architecture<br>Logic Synthesis for Field Programmable Gate Array (FPGA) Technology<br>Section IX Testing of Digital Systems<br>Design for Testability and Test Architectures<br>Automatic Test Pattern Generation 70 Built-In Self-Test<br>Section X Compound Semiconductor Integrated Circuit Technology<br>Compound Semiconductor Materials<br>Compound Semiconductor Devices for Analog and Digital Circuits<br>Compound Semiconductor RF Circuits<br>High-Speed Circuit Design Principles<br>Section XI Design Automation<br>Internet-Based Micro-Electronic Design Automation (IMEDA) Framework<br>System-Level Design<br>Performance Modeling and Analysis Using VHDL and SystemC<br>Embedded Computing Systems and Hardware/Software<br>Design Automation Technology Roadmap<br>Section XII VLSI Signal Processing<br>Computer Arithmetic for VLSI Signal Processing<br>VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges<br>VLSI Architectures for Forward Error-Control Decoders<br>An Exploration of Hardware Architectures for Face Detection<br>Multidimensional Logarithmic Number System<br>Section XIII Design Languages<br>Languages for Design and Implementation of Hardware<br>System Level Design Languages<br>RT Level Hardware Description with VHDL<br>Register Transfer Level Hardware Description with Verilog<br>Register-Transfer Level Hardware Description with SystemC<br>System Verilog<br>VHDL-AMS Hardware Description Language<br>Verification Languages<br>ASIC and Custom IC Cell Information Representation<br>Test Languages<br>Timing Description Languages<br>HDL-Based Tools and Environments