title: Bellmac 32
text: # Bellmac 32
  
  The Bellmac 32 is a microprocessor developed by Bell Labs' processor division in 1980, implemented using CMOS technology and was the first microprocessor that could move 32 bits in one clock cycle. The microprocessor contains 150,000 transistors and improved on the speed of CMOS design by using "domino circuits". It was designed with the C programming language in mind. After its creation, an improved version was produced called the Bellmac 32A, then cancelled along with its successor, the "Hobbit" C-language Reduced Instruction Set Processor (CRISP).
  
  ## History
  
  The Bellmac 32 processor was developed by AT&T engineers in three different Bell Labs locations: Indian Hill, Holmdel and Murray Hill.
  
  As the designers did not have automation tools, every chip designer had to use colored pencils for the completion of the initial design. Later, Steve Law developed a computer program that aided in the digitization of the initial designs.
  
  The development of the Bellmac 32 produced a novel circuit design technique called domino logic, deemed a breakthrough for the production of the microprocessor. Tests performed during manufacture indicated that a clock frequency even higher than the 4 MHz target speed was possible. Implementing the control logic, however, proved unexpectedly complicated. These complications limited the final speed, when the entire chip was finished and tested, to 2 MHz. The team considered it as progress, but not as successful, as it could not meet the initial AT&T design goals.
  
  Followup design meetings resulted in the Bellmac 32A project, as a second generation of the Bellmac microprocessor. The project once again selected CMOS technology and fixed the target clock frequency at 6.2 MHz. Adjustments to maximize the size of transistors and resistors and minimizing interconnections were fundamental in meeting the specifications. The engineers placed a 20-foot-by-20-foot engineering drawing of the chip layout on the floor of a large room. Testing of chips produced from the completed circuit exceeded the design speed, and reached clock frequencies of 7, 8, and even 9 MHz.
  
  After the breakup of AT&T, Bell Labs became a component of Western Electric. With this change, the Bellmac 32 was renamed to WE 32000. Updated versions of the chip included the WE 32100, announced in June 1984, and the WE 32200.
  
  ## Architecture
  
  The Bellmac 32 has a pipelined architecture with an instruction fetch unit that serves to control access to main memory, and an execution unit which serves to monitor the process and manipulate data.
  
  The instruction queue is filled with the instructions fetched from the memory. The address arithmetic unit serves for address calculations.
  
  ### Programming language support
  
  The Bellmac 32 architecture provides a variety of conveniences for programming language implementers. Procedure invocation involves the manipulation of four registers – the program counter, stack pointer, frame pointer and argument pointer – to transfer control between program procedures, along with use of the program stack to preserve register contents and communicate arguments and return values. Four instructions are offered to support such "procedure linkage": call saves the return address and argument pointer to the stack, save preserves selected registers in the range from R3 to R8 inclusive, restore restores any previously saved registers, and return obtains the stack frame prior to invocation and returns control to the saved return address. Addressing modes are provided that offer stack access relative to the argument pointer and frame pointer.
  
  ### Process management
  
  The architecture supports a particular model of process management, where a process employs a single execution stack, and where a Process Control Block (PCB) retains the execution context of each process, holding copies of the process's register values along with "block move" data describing a process's virtual memory configuration. As a convenience for operating system implementers, architectural support for process switching includes two dedicated instructions analogous to the traditional jump-to-subroutine and return-from-subroutine instructions. The call-process instruction saves user and control registers to a given process's PCB via the privileged Process Control Block Pointer (PCBP) register, thus capturing the execution state of the current process and allowing it to be suspended, followed by the loading of such registers from another process's PCB, thus restoring the execution state of a given process. Meanwhile, the return-to-process instruction merely loads process state from a given PCB. By performing "block moves", the process switching instructions are able to automatically reconfigure the active virtual memory layout without further intervention by the operating system, and combining this reconfiguration with updates to the processor registers, these instructions permit the execution environment of process to be conveniently restored.
  
  ### Interrupt handling
  
  Alongside the PCBP register, the Interrupt Stack Pointer (ISP) register is used to refer to a position on a common interrupt stack, used to record PCB pointers referencing the stored state of interrupted processes. When an interrupt is delivered, the dedicated call-process instruction is employed to suspend the running process, whose PCB address is stored on the interrupt stack, and to switch to an interrupt handler selected from a table. Interrupts behave like separate processes and are therefore provided with their own distinct execution stack. After interrupt handling is completed, the return-to-process instruction is then used to resume the suspended process. The selection of a suitable interrupt handler involves a table of PCB pointers in a fixed virtual memory location.
  
  ### Privileges, system calls and exception handling
  
  Four privilege levels are supported by the Bellmac 32 architecture. To switch between privilege levels, the "controlled transfer" mechanism is provided, relying on a two-level table hierarchy to define the privilege level using the Processor Status Word (PSW) register and the location of each procedure or handler to be invoked by a "controlled call", thus providing a system call mechanism. Exception handling employs this controlled call mechanism to direct execution to an appropriate handler, which for a "normal" exception is found via a particular second-level table whose entries each correspond to a particular Internal State Code (ISC), defined in the PSW register. For the exception-related features of the Bellmac 32 to function, an operating system kernel is also expected to reside in each process's virtual address space since an exception, relying on a controlled transfer, will not change the virtual memory configuration.
  
  ### Instructions supporting the C language
  
  Although various operations provided by the Bellmac 32 architecture support high-level languages generally, specific instructions are provided that support C language conventions, notably the string copy and string end instructions which rely on the C language representation of terminating character strings with a zero byte. A general block copy operation is also provided that utilises an explicit block length parameter to define the amount of data to be copied between locations.
  
  ## Registers
  
  Bellmac 32 has sixteen 32-bit registers. Three of these (ISP, PCBP, PSW) are privileged, used to support the operating system and can be written only when the microprocessor is in kernel mode. There are three other registers (SP, AP, FP) that are used by some instructions as stack pointers. Execution level, set in the Processor Status Word, can be one of four states: Kernel, Executive, Supervisor, User.
  
  There are an additional sixteen registers in the WE 32200, these being divided into two groups of eight registers: R16 to R23 being user registers, readable and writable in any processor mode, being intended for global variable and temporary storage; R24 to R31 being kernel, or privileged, registers that are only writable in kernel mode, being readable in any other mode. These additional registers were introduced to allow high-level language compilers to generate code that could use them to store frequently used data, thus improving the execution performance of such languages.
  
  ## Processor status word
  
  The Process Status Word is part of the register file and is aliased as R11.
  
  | Bits | Meaning |
  | - | - |
  | 31:26 | Unused |
  | 25 | Cache Flush Disable |
  | 24 | Quick-Interrupt Enable |
  | 23 | Cache Disable |
  | 22 | Enable Overflow Trap |
  | 21 | Negative |
  | 20 | Zero |
  | 19 | Overflow |
  | 18 | Carry |
  | 17 | Trace Enable |
  | 16:13 | Interrupt Priority Level |
  | 12:11 | Current Execution Level |
  | 10:9 | Previous Execution Level |
  | 8:7 | Register-Initial Context |
  | 6:3 | Internal State Code |
  | 2 | Trace Mask |
  | 1:0 | Exception Type |
  
  ## Instructions
  
  This microprocessor has 169 instructions, which are optimized for executing programs written in the C programming language. Accordingly, the format of character strings is adapted to C language specifications, for example.
  
  The instructions may have up to three operands. The processor has no floating-point or decimal arithmetic instructions, which were later provided by coprocessors WE 32106 and WE 32206.
  
  ## Memory
  
  The Bellmac 32 implements multiple types of memory addressing, such as linear, immediate 8, 16 or 32 bits, registration, register indirect, short shift, absolute and indirect displacement of 8, 16 or 32 bits.
  
  ## Usage
  
  The WE 32x00 processors were used in the AT&T Computer Systems' 3B series computers, being unveiled as commercially available products in the form of the 3B2, 3B5 and 3B20 ranges at the spring 1984 Comdex show. In mid-1985, AT&T started to offer the WE 32100 and associated chipset, along with "board-level" evaluation systems, to other manufacturers.
  
  ## Supporting chips
  
  AT&T had a lineup of WE 32x00 supporting chips and peripherals, including:
  
  * WE 32101 / 32201 Memory Management Unit
  * WE 32102 Clock (10, 14, 18, or 24 MHz)
  * WE 32103 DRAM Controller
  * WE 32104 / 32204 DMA Controller
  * WE 32106 / 32206 Math Acceleration Unit
  * WE 321SB VMEbus Single Board Computer
  * WE 321EB Evaluation Board
  