title: DEC Firefly
text: # DEC Firefly
  
  The Firefly was a shared memory asymmetric multiprocessor workstation, developed by the Systems Research Center, a research organization within Digital Equipment Corporation. The first version built contained up to seven MicroVAX 78032 microprocessors. The cache from each of the microprocessors kept a consistent view of the same main memory using a cache coherency algorithm, the Firefly protocol. The second version of the Firefly used faster CVAX 78034 microprocessors. It was later introduced as a product by DEC as the VAXstation 3520/3540 codenamed Firefox.
  
  ## Hardware description
  
  The Firefly was an asymmetric multiprocessor specialized racked computer as only one of the microprocessors had access to a Q-Bus interface that implemented the I/O subsystem.
  
  ### Processors
  
  The Firefly contained a primary processor board and zero, one, two or three secondary processor boards. These processor boards were 8 by 10 inches large. The primary processor board contained a microprocessor, its floating-point coprocessor and cache, and the Q-Bus control logic. The secondary processor boards each contained two microprocessors, their floating-point coprocessors and caches. The original Firefly processor boards used the MicroVAX 78032 microprocessor and MicroVAX 78132 floating-point coprocessor, but later Firefly systems used the faster CVAX 78034 microprocessors, CVAX Floating Point Chips (floating-point coprocessors). The processor boards communicated with each other and the memory via the MBus. The components used in the processor boards of the original Firefly were the same as those originally designed for the MicroVAX II system. Originally, the system was designed to use Motorola 68010 processors within this general architecture.
  
  The caches in the Firefly were direct-mapped for simplicity and to support multiprocessing; they used the Firefly protocol to ensure cache coherency. The caches on the MicroVAX processor boards had a capacity of 16 KB (4,096 4-byte lines) and were implemented with eleven 2 KB (4-bit by 4,096-word) SRAMs and twenty transistor–transistor logic (TTL) devices. The cache control logic was implemented with fifteen devices, mostly consisting of programmable array logic (PAL) devices. The caches on CVAX processor boards differed only in the capacity: 64 KB (16,384 4-byte lines) and were implemented with 8 KB (4-bit by 16,384-word) SRAMs.
  
  ### Memory
  
  Processors in the Firefly communicated with the main memory through their individual caches and over the MBus. Memory was implemented by one to four memory modules that connect to the MBus. The original Firefly had a master memory module with a capacity of 4 MB and up to three slave memory modules of the same capacity for a memory capacity of 4 to 16 MB. Later Firefly systems used a memory module with a capacity of 32 MB, for a memory capacity of 32 to 128 MB. The memory access time in the original MicroVAX-based Firefly was 400 ns, while the CVAX version had a memory access time of 200 ns.
  
  ### I/O
  
  I/O devices were connected to the system via the Q-Bus, whose 22-bit address space was mapped onto the 24-bit memory address space of the Firefly by using mapping registers controlled by the master processor. The devices used direct memory access (DMA) to access the memory though the cache of the main processor. The Firefly's I/O devices were: a monochrome display controller (MDC), a buffered controller for magnetic disk drives, the RQDX3 and an DEQNA Ethernet controller.
  
  While DEC used existing components for most of the I/O system, the display controller was designed specifically for the Firefly by the project's engineers who felt that no existing product met their performance requirements. There were two displayer controllers, one providing color graphics, and the other monochrome graphics. These controllers operated by checking a work queue set up in the memory using DMA, providing fully symmetric access to the display hardware by all processors.
  
  The monochrome display controller (MDC) was contained on a board half as large as the processor boards and was capable of achieving a resolution of 1024 by 768 pixels. It contained a 16-bit Am29116 microprocessor clocked at 10 MHz with a 10 KB memory containing 2,048 40-bit words of microinstruction memory. A 1024 by 1024-pixel frame buffer was implemented with VRAMs, with three quarters used to hold the display bitmap with the rest available for the display manager or used to cache fonts.
  
  The 29116 microprocessor periodically checked a work queue set up in the memory using DMA and executed commands from that queue. The commands performed BitBlt operations within the frame buffer, between the system memory and frame buffer and were also used to paint characters from the font cache.
  
  The display hardware also provided an interface for a keyboard and mouse. Sixty times per second, the MDC wrote to the memory the position of the mouse and an unencoded bitmap representing the state of the keyboard. As a result of implementing the MDC as an I/O device, the Firefly supported multiple display controllers in one system connected to multiple monitors.
  
  ## Software
  
  Two of the variants of the Firefly used system software called Topaz, which consisted of multiple components such as the Taos operating system that used a microkernel named the Nub and the Trestle window system. One of the features of Taos was that it supported the Ultrix binary calling interface, allowed existing Ultrix binaries compiled for the MicroVAX run unmodified image on the Firefly. In contrast to Ultrix, Topaz supported processes with multiple threads which could span multiple processors, and the Taos system could run both Ultrix and Topaz applications at the same time. Modula-2+, (a Modula-2 extended language) was used to program both Topaz and its applications.
  
  The Stanford V (operating system) also supported Firefly in a configuration with one CVAX and four Microvax-II CPUs in a BA123 chassis and QVSS?VCB01 graphics.
  
  