title: Raytheon 704
text: # Raytheon 704
  
  The Raytheon 704 is a 16-bit minicomputer introduced by Raytheon in 1970. The basic machine contained 4 kwords (8 kB) of memory and a simple arithmetic logic unit (ALU) running at 1 MHz. It was normally operated with a Teletype Model 33 acting as a computer terminal. It sold for "less than $10,000" (equivalent to $80,000 in 2022).
  
  A key feature of the design was the ability to expand the central processing unit (CPU) using plug-in cards. Options included a hardware multiply/divide unit, an 8-level vectored interrupt controller, a DMA controller, among others. Memory could also be added using the same cards, allowing up to 32 kW in total. Memory was based on an 18-bit word, not 16-bit, with the extra bits for use with an optional parity check card.
  
  Another unique feature was that general input/output expansion was external, using a daisy chained cable system known as DIO. This allowed devices like lab equipment and low-speed storage like tape drives to be added without requiring an internal card to support it; the device was added simply by connecting it to the nearest free DIO port on the computer or any other DIO device.
  
  The 704 does not appear to have seen widespread use, although passing mentions can be found in many documents and it had a presence in scientific circles. One example is displaying weather radar data for the United States Air Force. It is historically notable as the first computer to be used to run play-by-mail games, when Flying Buffalo Inc purchased one in 1970.
  
  ## History
  
  When it was launched, the 704 was a competitive machine compared to recently-released systems. The PDP-8/I, of 1968, cost $12,800 for a similar 4 kWord machine, but used smaller 12-bit words and thus had 6 kB of memory compared to the 704's 16-bit words where the same 4 kWord memory was 8 kB. The 704 was also faster, running at 1 MHz rather than the PDP-8's 600 kHz. Another machine aimed more squarely at the 704's instrumentation market was the HP 2116A, another 16-bit design that listed at $22,000.
  
  In spite of these advantages, the 704 faced stiff competition from other newly-introduced machines like the Data General Nova, which had a similar feature set but was less expensive, with a similar configuration costing $7,999. The Nova was slower than the 704, but this was addressed in the SuperNOVA, released in 1970 for $11,700. This sandwiched the 704 between lower-cost, lower-performance solutions, and higher-performance solutions that were only slightly more expensive.
  
  The 704 was used as an onsite seismic processing system by Petty-Ray Geophysical, named the Com*MAND 1, in the early 1970s, equipped with 1/2" tape drives, card reader, Teletype 33 console, and Gould 11" electrostatic plotter. Without an ATP, Vibroseis correlation of a full tape of seismic data would take several hours.
  
  The successor to the 704 was the RDS 500 which was extensively used by seismic acquisition companies such as Petty-Ray Geophysical, named the Com*MAND 2, CGG (company), Seismograph Survey Company (SSC) and Seismograph Survey Ltd (SSL), as well as several national oil companies.
  
  The compact size and relatively low environmental needs as compared to traditional mainframe systems meant it could be installed in 'frontier' areas in offices and trailers, processing seismic data for fast turnaround behind seismic data acquisition crews operating in areas such as North Africa, the Middle East and the Far East and various active exploration areas in the 1970s.
  
  ## Description
  
  ### Hardware design
  
  Like most minicomputers of the late 1960s, the 704 was designed to be mounted in a rack mount case, with the CPU being 9U (15.75 in, 40 cm) tall.
  
  The central processing unit (CPU) used 16-bit words, although it also included instructions that worked on 8-bit data, useful for working with ASCII text. Math was performed in parallel and used two's complement number format. Memory addresses were only 15-bits, allowing a maximum of 32 kilowords (64 kbytes) of directly addressable main memory.
  
  A showcase feature was the external input/output system, handled using a separate 16-bit wide "data input/output bus", or DIO, with up to 16 devices on two physical ports. These were connected together with custom DIO cables, daisy chained up to 50 feet (15 m) in total. By using both ports on separate 50-foot chains and placing the CPU in the center, the total distance could be up to 100 feet (30 m). The end of every DIO bus had to have an electrical terminator, even if it was unused.
  
  The basic unit included 4 kilowords of 18-bit memory, and a DIO controller for an ASCII terminal, normally the Teletype Model 33 or 35. This left four free card slots, and at launch, Raytheon offered a variety of plug-in expansions. These included 4 kilowords core memory modules, with enough room in the case for a total of four modules for a total of 16 kilowords.
  
  The purpose of the 18-bit memory was to allow the use of an optional parity check module, which offloaded this task from the CPU. Two bits were used to store separate parity bits for the two bytes of data in each word. In the event an error was found, the processor was halted and a lamp illuminated on the front panel.
  
  The hardware multiply/divide card reduced the time for a 16-bit multiply from 105 µsec to only 8, and a divide from 193 to 10.
  
  The DIO normally had a single level of interrupt, which is fine for simple uses but not in realtime computing and similar roles where rapid hardware handling of data is a major concern. For these roles, the Priority Interrupt Expansion added an eight-level interrupt system, and a second card could be used to expand this to 16 levels. Installing this option also activated the front-panel interrupt button, which was normally inactive as the only interrupt, level 00, was assigned to the terminal.
  
  The direct memory access (DMA) card connected up to six devices to memory, although only one device was active at a time, using a separate dedicated bus that bypassed the CPU and DIO. This was normally used for hard disk and magnetic tape support. The DMA bus also used custom cables, limited in this case to 24 feet (7.3 m) in length with only a single bus. Like DIO, the bus had to be terminated.
  
  Finally, a Power Failsafe Option was available that was intended to stop the processor in a known-good state if it noticed the voltage from the power supply dropping, indicating an imminent power failure. An Automatic Bootstrap Module is mentioned but was not available at launch time. Sales documents from the era also mention a real-time clock and an analog-to-digital converter.
  
  ### CPU model
  
  The CPU ran lock-step with the core memory, which was a typical design of the era. This limited the machine to a basic 1 µsec cycle time, or 1 MHz in common modern terms. The clock was a 20 MHz crystal oscillator that was divided down for the various components.
  
  There were 72 basic instructions, plus the MPY and DIV instructions if the multiply/divide unit was installed. Instructions were generally one word long, in strong contrast to typical designs of the era which used variable length instructions depending on the addressing mode. Most instructions used the single user-visible 16-bit accumulator ACR and a 16-bit memory buffer register (MBR) used to temporarily hold operands for two-operand instructions (the other being ACR). 15-bit registers were used for the program counter (PCR) and memory address register (MAR), the later of which was used while fetching data from memory. Addresses could also be offset using the 16-bit index register IXR. Two other registers, the 5-bit EXR and 8-bit INR served special purposes.
  
  Opcodes were generally 4-bits in length, in bits 0 through 3. The purpose of the 15-bit addresses in a 16-bit machine was to set aside one bit in the instruction format to indicate that the address was relative, normally bit 4. This left bits 5 through 15 for use as an address or constant. When used as an address, this meant it was only 11 bits long, and an additional four bits from the 5-bit EXR were added to the front to make a complete 15-bit address. This meant the memory was logically organized as a set of 2 k pages, and working with data in another page required instructions to change the EXR. All five bits of EXR were used when using byte addressing, or only four when addressing words. On top of both, the index register would be added if the index bit was turned on in the instruction.
  
  Math instructions, ADD and SUB, always worked on 16-bit values, as did logical operations – AND, ORI ("inclusive" OR) and ORE (exclusive OR). Interesting additions were INV to invert the value and CMP to perform the two's complement. Shift and rotate instructions were available in 16 and 32-bit forms.
  
  There were three primary comparison operators, CMW to compare words and CMB to compare bytes, and CLB to compare a byte in the accumulator with a literal byte (constant) in the address section of the instruction word. The only other support for literals was LLB which loaded a constant byte value into the accumulator. These sorts of literal (or constant) instructions are generally much more common in most processors as it avoids a memory accesses for these frequently used instructions.
  
  Conditional branching was not supported directly, instead, there were a series of "skip" instructions that could be performed after a comparison. For instance, SAZ would skip the next instruction if the value in the accumulator was zero. To perform branches, the next instruction would normally be a jump, JMP or jump-and-store-address-in-IXR, JSX, used for subroutines. In addition to the accumulator, skip instructions were provided that read the index register, the results of a comparison and for four of the front-panel switches.
  
  ### ATP add-on
  
  In January 1971, Raytheon announced a new add-on for the 704 system, the Array Transform Processor, or ATP. This required an entire 3U case of its own. This was essentially a vector processor dedicated to performing fast Fourier transforms (FFT), with arrays from 2 to 8192 complex numbers. A typical 2048 FFT could be accomplished in "only 150 milliseconds!" A system consisting of a 704, the ATP and enough memory to hold the data ran to about $40,000 (equivalent to $289,039 in 2022).
  
  It was this ATP add-on which made the 704 and the later RDS500 so popular as a seismic data processing system, the ATP speeding up the many digital signal processing techniques such as filtering, deconvolution and correlation which were essential in enhancing the seismic data for interpretation.
  
  