text:
/***************************************************************************//**
 * @file
 * @brief Security Management Unit (SMU) peripheral API
 *******************************************************************************
 * # License
 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
 *******************************************************************************
 *
 * SPDX-License-Identifier: Zlib
 *
 * The licensor of this software is Silicon Laboratories Inc.
 *
 * This software is provided 'as-is', without any express or implied
 * warranty. In no event will the authors be held liable for any damages
 * arising from the use of this software.
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
 * freely, subject to the following restrictions:
 *
 * 1. The origin of this software must not be misrepresented; you must not
 *    claim that you wrote the original software. If you use this software
 *    in a product, an acknowledgment in the product documentation would be
 *    appreciated but is not required.
 * 2. Altered source versions must be plainly marked as such, and must not be
 *    misrepresented as being the original software.
 * 3. This notice may not be removed or altered from any source distribution.
 *
 ******************************************************************************/

#ifndef EM_SMU_H
#define EM_SMU_H

#include "em_device.h"
#if defined(SMU_COUNT) && (SMU_COUNT > 0)

#include "em_assert.h"
#include "em_bus.h"

#include <stdint.h>
#include <stdbool.h>

#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************************//**
 * @addtogroup emlib
 * @{
 ******************************************************************************/

/***************************************************************************//**
 * @addtogroup SMU
 * @brief Security Management Unit (SMU) Peripheral API.
 *
 * @details
 *   SMU forms the control and status/reporting component of bus-level
 *   security in EFM32/EFR32 devices.
 *
 *   Peripheral-level protection is provided via the peripheral protection unit
 *   (PPU). PPU provides hardware access barrier to any peripheral that is
 *   configured to be protected. When an attempt is made to access a peripheral
 *   without the required privilege/security level, PPU detects the fault
 *   and intercepts the access. No write or read of the peripheral register
 *   space occurs, and an all-zero value is returned if the access is a read.
 *
 *   @subsection Usage example
 *   @include em_smu_init.c
 * @{
 ******************************************************************************/

/*******************************************************************************
 ********************************   ENUMS   ************************************
 ******************************************************************************/

/** SMU peripheral identifiers. */
typedef enum {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
  smuPeripheralACMP0      = _SMU_PPUPATD0_ACMP0_SHIFT,         /**< SMU peripheral identifier for ACMP0.     */
  smuPeripheralACMP1      = _SMU_PPUPATD0_ACMP1_SHIFT,         /**< SMU peripheral identifier for ACMP1.     */
  smuPeripheralADC0       = _SMU_PPUPATD0_ADC0_SHIFT,          /**< SMU peripheral identifier for ADC0.      */
  smuPeripheralCMU        = _SMU_PPUPATD0_CMU_SHIFT,           /**< SMU peripheral identifier for CMU.       */
  smuPeripheralCRYOTIMER  = _SMU_PPUPATD0_CRYOTIMER_SHIFT,     /**< SMU peripheral identifier for CRYOTIMER. */
  smuPeripheralCRYPTO0    = _SMU_PPUPATD0_CRYPTO0_SHIFT,       /**< SMU peripheral identifier for CRYPTO0.   */
  smuPeripheralCRYPTO1    = _SMU_PPUPATD0_CRYPTO1_SHIFT,       /**< SMU peripheral identifier for CRYPTO1.   */
  smuPeripheralCSEN       = _SMU_PPUPATD0_CSEN_SHIFT,          /**< SMU peripheral identifier for CSEN.      */
  smuPeripheralVDAC0      = _SMU_PPUPATD0_VDAC0_SHIFT,         /**< SMU peripheral identifier for VDAC0.     */
  smuPeripheralPRS        = _SMU_PPUPATD0_PRS_SHIFT,           /**< SMU peripheral identifier for PRS.       */
  smuPeripheralEMU        = _SMU_PPUPATD0_EMU_SHIFT,           /**< SMU peripheral identifier for EMU.       */
  smuPeripheralFPUEH      = _SMU_PPUPATD0_FPUEH_SHIFT,         /**< SMU peripheral identifier for FPUEH.     */
  smuPeripheralGPCRC      = _SMU_PPUPATD0_GPCRC_SHIFT,         /**< SMU peripheral identifier for GPCRC.     */
  smuPeripheralGPIO       = _SMU_PPUPATD0_GPIO_SHIFT,          /**< SMU peripheral identifier for GPIO.      */
  smuPeripheralI2C0       = _SMU_PPUPATD0_I2C0_SHIFT,          /**< SMU peripheral identifier for I2C0.      */
  smuPeripheralI2C1       = _SMU_PPUPATD0_I2C1_SHIFT,          /**< SMU peripheral identifier for I2C1.      */
  smuPeripheralIDAC0      = _SMU_PPUPATD0_IDAC0_SHIFT,         /**< SMU peripheral identifier for IDAC0.     */
  smuPeripheralMSC        = _SMU_PPUPATD0_MSC_SHIFT,           /**< SMU peripheral identifier for MSC.       */
  smuPeripheralLDMA       = _SMU_PPUPATD0_LDMA_SHIFT,          /**< SMU peripheral identifier for LDMA.      */
  smuPeripheralLESENSE    = _SMU_PPUPATD0_LESENSE_SHIFT,       /**< SMU peripheral identifier for LESENSE.   */
  smuPeripheralLETIMER0   = _SMU_PPUPATD0_LETIMER0_SHIFT,      /**< SMU peripheral identifier for LETIMER0.  */
  smuPeripheralLEUART0    = _SMU_PPUPATD0_LEUART0_SHIFT,       /**< SMU peripheral identifier for LEUART0.   */
  smuPeripheralPCNT0      = _SMU_PPUPATD0_PCNT0_SHIFT,         /**< SMU peripheral identifier for PCNT0.     */
  smuPeripheralPCNT1      = _SMU_PPUPATD0_PCNT1_SHIFT,         /**< SMU peripheral identifier for PCNT1.     */
  smuPeripheralPCNT2      = _SMU_PPUPATD0_PCNT2_SHIFT,         /**< SMU peripheral identifier for PCNT2.     */
  smuPeripheralRMU        = 32 + _SMU_PPUPATD1_RMU_SHIFT,      /**< SMU peripheral identifier for RMU.       */
  smuPeripheralRTCC       = 32 + _SMU_PPUPATD1_RTCC_SHIFT,     /**< SMU peripheral identifier for RTCC.      */
  smuPeripheralSMU        = 32 + _SMU_PPUPATD1_SMU_SHIFT,      /**< SMU peripheral identifier for SMU.       */
  smuPeripheralTIMER0     = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,   /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTIMER1     = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,   /**< SMU peripheral identifier for TIMER1.    */
  smuPeripheralTRNG0      = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,    /**< SMU peripheral identifier for TRNG0.     */
  smuPeripheralUSART0     = 32 + _SMU_PPUPATD1_USART0_SHIFT,   /**< SMU peripheral identifier for USART0.    */
  smuPeripheralUSART1     = 32 + _SMU_PPUPATD1_USART1_SHIFT,   /**< SMU peripheral identifier for USART1.    */
  smuPeripheralUSART2     = 32 + _SMU_PPUPATD1_USART2_SHIFT,   /**< SMU peripheral identifier for USART2.    */
  smuPeripheralUSART3     = 32 + _SMU_PPUPATD1_USART3_SHIFT,   /**< SMU peripheral identifier for USART3.    */
  smuPeripheralWDOG0      = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,    /**< SMU peripheral identifier for WDOG0.     */
  smuPeripheralWDOG1      = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,    /**< SMU peripheral identifier for WDOG1.     */
  smuPeripheralWTIMER0    = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,  /**< SMU peripheral identifier for WTIMER0.   */
  smuPeripheralWTIMER1    = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT,  /**< SMU peripheral identifier for WTIMER1.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
  smuPeripheralACMP0      = _SMU_PPUPATD0_ACMP0_SHIFT,         /**< SMU peripheral identifier for ACMP0.     */
  smuPeripheralACMP1      = _SMU_PPUPATD0_ACMP1_SHIFT,         /**< SMU peripheral identifier for ACMP1.     */
  smuPeripheralADC0       = _SMU_PPUPATD0_ADC0_SHIFT,          /**< SMU peripheral identifier for ADC0.      */
  smuPeripheralCMU        = _SMU_PPUPATD0_CMU_SHIFT,           /**< SMU peripheral identifier for CMU.       */
  smuPeripheralCRYOTIMER  = _SMU_PPUPATD0_CRYOTIMER_SHIFT,     /**< SMU peripheral identifier for CRYOTIMER. */
  smuPeripheralCRYPTO0    = _SMU_PPUPATD0_CRYPTO0_SHIFT,       /**< SMU peripheral identifier for CRYPTO0.   */
  smuPeripheralCRYPTO1    = _SMU_PPUPATD0_CRYPTO1_SHIFT,       /**< SMU peripheral identifier for CRYPTO1.   */
#if defined(_SMU_PPUPATD0_CSEN_SHIFT)
  smuPeripheralCSEN       = _SMU_PPUPATD0_CSEN_SHIFT,          /**< SMU peripheral identifier for CSEN.      */
#endif
#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
  smuPeripheralVDAC0      = _SMU_PPUPATD0_VDAC0_SHIFT,         /**< SMU peripheral identifier for VDAC0.     */
#endif
  smuPeripheralPRS        = _SMU_PPUPATD0_PRS_SHIFT,           /**< SMU peripheral identifier for PRS.       */
  smuPeripheralEMU        = _SMU_PPUPATD0_EMU_SHIFT,           /**< SMU peripheral identifier for EMU.       */
  smuPeripheralFPUEH      = _SMU_PPUPATD0_FPUEH_SHIFT,         /**< SMU peripheral identifier for FPUEH.     */
  smuPeripheralGPCRC      = _SMU_PPUPATD0_GPCRC_SHIFT,         /**< SMU peripheral identifier for GPCRC.     */
  smuPeripheralGPIO       = _SMU_PPUPATD0_GPIO_SHIFT,          /**< SMU peripheral identifier for GPIO.      */
  smuPeripheralI2C0       = _SMU_PPUPATD0_I2C0_SHIFT,          /**< SMU peripheral identifier for I2C0.      */
  smuPeripheralI2C1       = _SMU_PPUPATD0_I2C1_SHIFT,          /**< SMU peripheral identifier for I2C1.      */
#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
  smuPeripheralIDAC0      = _SMU_PPUPATD0_IDAC0_SHIFT,         /**< SMU peripheral identifier for IDAC0.     */
#endif
  smuPeripheralMSC        = _SMU_PPUPATD0_MSC_SHIFT,           /**< SMU peripheral identifier for MSC.       */
  smuPeripheralLDMA       = _SMU_PPUPATD0_LDMA_SHIFT,          /**< SMU peripheral identifier for LDMA.      */
  smuPeripheralLESENSE    = _SMU_PPUPATD0_LESENSE_SHIFT,       /**< SMU peripheral identifier for LESENSE.   */
  smuPeripheralLETIMER0   = _SMU_PPUPATD0_LETIMER0_SHIFT,      /**< SMU peripheral identifier for LETIMER0.  */
  smuPeripheralLEUART0    = _SMU_PPUPATD0_LEUART0_SHIFT,       /**< SMU peripheral identifier for LEUART0.   */
  smuPeripheralPCNT0      = _SMU_PPUPATD0_PCNT0_SHIFT,         /**< SMU peripheral identifier for PCNT0.     */
  smuPeripheralRMU        = 32 + _SMU_PPUPATD1_RMU_SHIFT,      /**< SMU peripheral identifier for RMU.       */
  smuPeripheralRTCC       = 32 + _SMU_PPUPATD1_RTCC_SHIFT,     /**< SMU peripheral identifier for RTCC.      */
  smuPeripheralSMU        = 32 + _SMU_PPUPATD1_SMU_SHIFT,      /**< SMU peripheral identifier for SMU.       */
  smuPeripheralTIMER0     = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,   /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTIMER1     = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,   /**< SMU peripheral identifier for TIMER1.    */
  smuPeripheralTRNG0      = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,    /**< SMU peripheral identifier for TRNG0.     */
  smuPeripheralUSART0     = 32 + _SMU_PPUPATD1_USART0_SHIFT,   /**< SMU peripheral identifier for USART0.    */
  smuPeripheralUSART1     = 32 + _SMU_PPUPATD1_USART1_SHIFT,   /**< SMU peripheral identifier for USART1.    */
  smuPeripheralUSART2     = 32 + _SMU_PPUPATD1_USART2_SHIFT,   /**< SMU peripheral identifier for USART2.    */
  smuPeripheralWDOG0      = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,    /**< SMU peripheral identifier for WDOG0.     */
  smuPeripheralWDOG1      = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,    /**< SMU peripheral identifier for WDOG1.     */
  smuPeripheralWTIMER0    = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,  /**< SMU peripheral identifier for WTIMER0.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
#if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
  smuPeripheralACMP0      = _SMU_PPUPATD0_ACMP0_SHIFT,         /**< SMU peripheral identifier for ACMP0.     */
#endif
#if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
  smuPeripheralACMP1      = _SMU_PPUPATD0_ACMP1_SHIFT,         /**< SMU peripheral identifier for ACMP1.     */
#endif
#if defined(_SMU_PPUPATD0_ADC0_SHIFT)
  smuPeripheralADC0       = _SMU_PPUPATD0_ADC0_SHIFT,          /**< SMU peripheral identifier for ADC0.      */
#endif
  smuPeripheralCMU        = _SMU_PPUPATD0_CMU_SHIFT,           /**< SMU peripheral identifier for CMU.       */
  smuPeripheralCRYOTIMER  = _SMU_PPUPATD0_CRYOTIMER_SHIFT,     /**< SMU peripheral identifier for CRYOTIMER. */
  smuPeripheralCRYPTO     = _SMU_PPUPATD0_CRYPTO0_SHIFT,       /**< SMU peripheral identifier for CRYPTO0.   */
#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
  smuPeripheralVDAC0      = _SMU_PPUPATD0_VDAC0_SHIFT,         /**< SMU peripheral identifier for VDAC0.     */
#endif
  smuPeripheralPRS        = _SMU_PPUPATD0_PRS_SHIFT,           /**< SMU peripheral identifier for PRS.       */
  smuPeripheralEMU        = _SMU_PPUPATD0_EMU_SHIFT,           /**< SMU peripheral identifier for EMU.       */
  smuPeripheralFPUEH      = _SMU_PPUPATD0_FPUEH_SHIFT,         /**< SMU peripheral identifier for FPUEH.     */
  smuPeripheralGPCRC      = _SMU_PPUPATD0_GPCRC_SHIFT,         /**< SMU peripheral identifier for GPCRC.     */
  smuPeripheralGPIO       = _SMU_PPUPATD0_GPIO_SHIFT,          /**< SMU peripheral identifier for GPIO.      */
  smuPeripheralI2C0       = _SMU_PPUPATD0_I2C0_SHIFT,          /**< SMU peripheral identifier for I2C0.      */
#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
  smuPeripheralIDAC0      = _SMU_PPUPATD0_IDAC0_SHIFT,         /**< SMU peripheral identifier for IDAC0.     */
#endif
  smuPeripheralMSC        = _SMU_PPUPATD0_MSC_SHIFT,           /**< SMU peripheral identifier for MSC.       */
  smuPeripheralLDMA       = _SMU_PPUPATD0_LDMA_SHIFT,          /**< SMU peripheral identifier for LDMA.      */
#if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
  smuPeripheralLESENSE    = _SMU_PPUPATD0_LESENSE_SHIFT,       /**< SMU peripheral identifier for LESENSE.   */
#endif
  smuPeripheralLETIMER0   = _SMU_PPUPATD0_LETIMER0_SHIFT,      /**< SMU peripheral identifier for LETIMER0.  */
  smuPeripheralLEUART     = _SMU_PPUPATD0_LEUART0_SHIFT,       /**< SMU peripheral identifier for LEUART0.   */
#if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
  smuPeripheralPCNT0      = _SMU_PPUPATD0_PCNT0_SHIFT,         /**< SMU peripheral identifier for PCNT0.     */
#endif
  smuPeripheralRMU        = _SMU_PPUPATD0_RMU_SHIFT,           /**< SMU peripheral identifier for RMU.       */
  smuPeripheralRTCC       = _SMU_PPUPATD0_RTCC_SHIFT,          /**< SMU peripheral identifier for RTCC.      */
  smuPeripheralSMU        = _SMU_PPUPATD0_SMU_SHIFT,           /**< SMU peripheral identifier for SMU.       */
  smuPeripheralTIMER0     = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,   /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTIMER1     = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,   /**< SMU peripheral identifier for TIMER1.    */
  smuPeripheralTRNG0      = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,    /**< SMU peripheral identifier for TRNG0.     */
  smuPeripheralUSART0     = 32 + _SMU_PPUPATD1_USART0_SHIFT,   /**< SMU peripheral identifier for USART0.    */
  smuPeripheralUSART1     = 32 + _SMU_PPUPATD1_USART1_SHIFT,   /**< SMU peripheral identifier for USART1.    */
  smuPeripheralWDOG0      = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,    /**< SMU peripheral identifier for WDOG0.     */
  smuPeripheralWDOG1      = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,    /**< SMU peripheral identifier for WDOG1.     */
  smuPeripheralWTIMER0    = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,  /**< SMU peripheral identifier for WTIMER0.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
  smuPeripheralACMP0     = _SMU_PPUPATD0_ACMP0_SHIFT,          /**< SMU peripheral identifier for ACMP0.     */
  smuPeripheralACMP1     = _SMU_PPUPATD0_ACMP1_SHIFT,          /**< SMU peripheral identifier for ACMP1.     */
  smuPeripheralACMP2     = _SMU_PPUPATD0_ACMP2_SHIFT,          /**< SMU peripheral identifier for ACMP2.     */
  smuPeripheralACMP3     = _SMU_PPUPATD0_ACMP3_SHIFT,          /**< SMU peripheral identifier for ACMP3.     */
  smuPeripheralADC0      = _SMU_PPUPATD0_ADC0_SHIFT,           /**< SMU peripheral identifier for ADC0.      */
  smuPeripheralADC1      = _SMU_PPUPATD0_ADC1_SHIFT,           /**< SMU peripheral identifier for ADC1.      */
  smuPeripheralCAN0      = _SMU_PPUPATD0_CAN0_SHIFT,           /**< SMU peripheral identifier for CAN0.      */
  smuPeripheralCAN1      = _SMU_PPUPATD0_CAN1_SHIFT,           /**< SMU peripheral identifier for CAN1.      */
  smuPeripheralCMU       = _SMU_PPUPATD0_CMU_SHIFT,            /**< SMU peripheral identifier for CMU.       */
  smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT,      /**< SMU peripheral identifier for CRYOTIMER. */
  smuPeripheralCRYPTO0   = _SMU_PPUPATD0_CRYPTO0_SHIFT,        /**< SMU peripheral identifier for CRYPTO0.   */
  smuPeripheralCSEN      = _SMU_PPUPATD0_CSEN_SHIFT,           /**< SMU peripheral identifier for CSEN.      */
  smuPeripheralVDAC0     = _SMU_PPUPATD0_VDAC0_SHIFT,          /**< SMU peripheral identifier for VDAC0.     */
  smuPeripheralPRS       = _SMU_PPUPATD0_PRS_SHIFT,            /**< SMU peripheral identifier for PRS.       */
  smuPeripheralEBI       = _SMU_PPUPATD0_EBI_SHIFT,            /**< SMU peripheral identifier for EBI.       */
  smuPeripheralEMU       = _SMU_PPUPATD0_EMU_SHIFT,            /**< SMU peripheral identifier for EMU.       */
#if defined(_SMU_PPUPATD0_ETH_SHIFT)
  smuPeripheralETH       = _SMU_PPUPATD0_ETH_SHIFT,            /**< SMU peripheral identifier for ETH.       */
#endif
  smuPeripheralFPUEH     = _SMU_PPUPATD0_FPUEH_SHIFT,          /**< SMU peripheral identifier for FPUEH.     */
  smuPeripheralGPCRC     = _SMU_PPUPATD0_GPCRC_SHIFT,          /**< SMU peripheral identifier for GPCRC.     */
  smuPeripheralGPIO      = _SMU_PPUPATD0_GPIO_SHIFT,           /**< SMU peripheral identifier for GPIO.      */
  smuPeripheralI2C0      = _SMU_PPUPATD0_I2C0_SHIFT,           /**< SMU peripheral identifier for I2C0.      */
  smuPeripheralI2C1      = _SMU_PPUPATD0_I2C1_SHIFT,           /**< SMU peripheral identifier for I2C1.      */
  smuPeripheralI2C2      = _SMU_PPUPATD0_I2C2_SHIFT,           /**< SMU peripheral identifier for I2C2.      */
  smuPeripheralIDAC0     = _SMU_PPUPATD0_IDAC0_SHIFT,          /**< SMU peripheral identifier for IDAC0.     */
  smuPeripheralMSC       = _SMU_PPUPATD0_MSC_SHIFT,            /**< SMU peripheral identifier for MAC.       */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
  smuPeripheralLCD       = _SMU_PPUPATD0_LCD_SHIFT,            /**< SMU peripheral identifier for LCD.       */
#endif
  smuPeripheralLDMA      = _SMU_PPUPATD0_LDMA_SHIFT,           /**< SMU peripheral identifier for LDMA.      */
  smuPeripheralLESENSE   = _SMU_PPUPATD0_LESENSE_SHIFT,        /**< SMU peripheral identifier for LESENSE.   */
  smuPeripheralLETIMER0  = _SMU_PPUPATD0_LETIMER0_SHIFT,       /**< SMU peripheral identifier for LETIMER0.  */
  smuPeripheralLETIMER1  = _SMU_PPUPATD0_LETIMER1_SHIFT,       /**< SMU peripheral identifier for LETIMER1.  */
  smuPeripheralLEUART0   = _SMU_PPUPATD0_LEUART0_SHIFT,        /**< SMU peripheral identifier for LEUART0.   */
  smuPeripheralLEUART1   = _SMU_PPUPATD0_LEUART1_SHIFT,        /**< SMU peripheral identifier for LEUART1.   */
  smuPeripheralPCNT0     = 32 + _SMU_PPUPATD1_PCNT0_SHIFT,     /**< SMU peripheral identifier for PCNT0.     */
  smuPeripheralPCNT1     = 32 + _SMU_PPUPATD1_PCNT1_SHIFT,     /**< SMU peripheral identifier for PCNT1.     */
  smuPeripheralPCNT2     = 32 + _SMU_PPUPATD1_PCNT2_SHIFT,     /**< SMU peripheral identifier for PCNT2.     */
#if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
  smuPeripheralQSPI0     = 32 + _SMU_PPUPATD1_QSPI0_SHIFT,     /**< SMU peripheral identifier for QSPI0.     */
#endif
  smuPeripheralRMU       = 32 + _SMU_PPUPATD1_RMU_SHIFT,       /**< SMU peripheral identifier for RMU.       */
  smuPeripheralRTC       = 32 + _SMU_PPUPATD1_RTC_SHIFT,       /**< SMU peripheral identifier for RTC.       */
  smuPeripheralRTCC      = 32 + _SMU_PPUPATD1_RTCC_SHIFT,      /**< SMU peripheral identifier for RTCC.      */
#if defined(_SMU_PPUPATD1_SDIO_SHIFT)
  smuPeripheralSDIO      = 32 + _SMU_PPUPATD1_SDIO_SHIFT,      /**< SMU peripheral identifier for SDIO.      */
#endif
  smuPeripheralSMU       = 32 + _SMU_PPUPATD1_SMU_SHIFT,       /**< SMU peripheral identifier for SMU.       */
  smuPeripheralTIMER0    = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,    /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTIMER1    = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,    /**< SMU peripheral identifier for TIMER1.    */
  smuPeripheralTIMER2    = 32 + _SMU_PPUPATD1_TIMER2_SHIFT,    /**< SMU peripheral identifier for TIMER2.    */
  smuPeripheralTIMER3    = 32 + _SMU_PPUPATD1_TIMER3_SHIFT,    /**< SMU peripheral identifier for TIMER3.    */
  smuPeripheralTIMER4    = 32 + _SMU_PPUPATD1_TIMER4_SHIFT,    /**< SMU peripheral identifier for TIMER4.    */
  smuPeripheralTIMER5    = 32 + _SMU_PPUPATD1_TIMER5_SHIFT,    /**< SMU peripheral identifier for TIMER5.    */
  smuPeripheralTIMER6    = 32 + _SMU_PPUPATD1_TIMER6_SHIFT,    /**< SMU peripheral identifier for TIMER6.    */
  smuPeripheralTRNG0     = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,     /**< SMU peripheral identifier for TRNG0.     */
  smuPeripheralUART0     = 32 + _SMU_PPUPATD1_UART0_SHIFT,     /**< SMU peripheral identifier for UART0.     */
  smuPeripheralUART1     = 32 + _SMU_PPUPATD1_UART1_SHIFT,     /**< SMU peripheral identifier for UART1.     */
  smuPeripheralUSART0    = 32 + _SMU_PPUPATD1_USART0_SHIFT,    /**< SMU peripheral identifier for USART0.    */
  smuPeripheralUSART1    = 32 + _SMU_PPUPATD1_USART1_SHIFT,    /**< SMU peripheral identifier for USART1.    */
  smuPeripheralUSART2    = 32 + _SMU_PPUPATD1_USART2_SHIFT,    /**< SMU peripheral identifier for USART2.    */
  smuPeripheralUSART3    = 32 + _SMU_PPUPATD1_USART3_SHIFT,    /**< SMU peripheral identifier for USART3.    */
  smuPeripheralUSART4    = 32 + _SMU_PPUPATD1_USART4_SHIFT,    /**< SMU peripheral identifier for USART4.    */
  smuPeripheralUSART5    = 32 + _SMU_PPUPATD1_USART5_SHIFT,    /**< SMU peripheral identifier for USART5.    */
#if defined(_SMU_PPUPATD1_USB_SHIFT)
  smuPeripheralUSB       = 32 + _SMU_PPUPATD1_USB_SHIFT,       /**< SMU peripheral identifier for USB.       */
#endif
  smuPeripheralWDOG0     = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,     /**< SMU peripheral identifier for WDOG0.     */
  smuPeripheralWDOG1     = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,     /**< SMU peripheral identifier for WDOG1.     */
  smuPeripheralWTIMER0   = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,   /**< SMU peripheral identifier for WTIMER0.   */
  smuPeripheralWTIMER1   = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT,   /**< SMU peripheral identifier for WTIMER1.   */
  smuPeripheralWTIMER2   = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT,   /**< SMU peripheral identifier for WTIMER2.   */
  smuPeripheralWTIMER3   = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT,   /**< SMU peripheral identifier for WTIMER3.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
  smuPeripheralACMP0     = _SMU_PPUPATD0_ACMP0_SHIFT,          /**< SMU peripheral identifier for ACMP0.     */
  smuPeripheralACMP1     = _SMU_PPUPATD0_ACMP1_SHIFT,          /**< SMU peripheral identifier for ACMP1.     */
  smuPeripheralACMP2     = _SMU_PPUPATD0_ACMP2_SHIFT,          /**< SMU peripheral identifier for ACMP2.     */
  smuPeripheralADC0      = _SMU_PPUPATD0_ADC0_SHIFT,           /**< SMU peripheral identifier for ADC0.      */
  smuPeripheralADC1      = _SMU_PPUPATD0_ADC1_SHIFT,           /**< SMU peripheral identifier for ADC1.      */
  smuPeripheralCAN0      = _SMU_PPUPATD0_CAN0_SHIFT,           /**< SMU peripheral identifier for CAN0.      */
  smuPeripheralCAN1      = _SMU_PPUPATD0_CAN1_SHIFT,           /**< SMU peripheral identifier for CAN1.      */
  smuPeripheralCMU       = _SMU_PPUPATD0_CMU_SHIFT,            /**< SMU peripheral identifier for CMU.       */
  smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT,      /**< SMU peripheral identifier for CRYOTIMER. */
  smuPeripheralCRYPTO0   = _SMU_PPUPATD0_CRYPTO0_SHIFT,        /**< SMU peripheral identifier for CRYPTO0.   */
  smuPeripheralCSEN      = _SMU_PPUPATD0_CSEN_SHIFT,           /**< SMU peripheral identifier for CSEN.      */
  smuPeripheralVDAC0     = _SMU_PPUPATD0_VDAC0_SHIFT,          /**< SMU peripheral identifier for VDAC0.     */
  smuPeripheralPRS       = _SMU_PPUPATD0_PRS_SHIFT,            /**< SMU peripheral identifier for PRS.       */
  smuPeripheralEBI       = _SMU_PPUPATD0_EBI_SHIFT,            /**< SMU peripheral identifier for EBI.       */
  smuPeripheralEMU       = _SMU_PPUPATD0_EMU_SHIFT,            /**< SMU peripheral identifier for EMU.       */
#if defined(_SMU_PPUPATD0_ETH_SHIFT)
  smuPeripheralETH       = _SMU_PPUPATD0_ETH_SHIFT,            /**< SMU peripheral identifier for ETH.       */
#endif
  smuPeripheralFPUEH     = _SMU_PPUPATD0_FPUEH_SHIFT,          /**< SMU peripheral identifier for FPUEH.     */
  smuPeripheralGPCRC     = _SMU_PPUPATD0_GPCRC_SHIFT,          /**< SMU peripheral identifier for GPCRC.     */
  smuPeripheralGPIO      = _SMU_PPUPATD0_GPIO_SHIFT,           /**< SMU peripheral identifier for GPIO.      */
  smuPeripheralI2C0      = _SMU_PPUPATD0_I2C0_SHIFT,           /**< SMU peripheral identifier for I2C0.      */
  smuPeripheralI2C1      = _SMU_PPUPATD0_I2C1_SHIFT,           /**< SMU peripheral identifier for I2C1.      */
  smuPeripheralIDAC0     = _SMU_PPUPATD0_IDAC0_SHIFT,          /**< SMU peripheral identifier for IDAC0.     */
  smuPeripheralMSC       = _SMU_PPUPATD0_MSC_SHIFT,            /**< SMU peripheral identifier for MAC.       */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
  smuPeripheralLCD       = _SMU_PPUPATD0_LCD_SHIFT,            /**< SMU peripheral identifier for LCD.       */
#endif
  smuPeripheralLDMA      = _SMU_PPUPATD0_LDMA_SHIFT,           /**< SMU peripheral identifier for LDMA.      */
  smuPeripheralLESENSE   = _SMU_PPUPATD0_LESENSE_SHIFT,        /**< SMU peripheral identifier for LESENSE.   */
  smuPeripheralLETIMER0  = _SMU_PPUPATD0_LETIMER0_SHIFT,       /**< SMU peripheral identifier for LETIMER0.  */
  smuPeripheralLETIMER1  = _SMU_PPUPATD0_LETIMER1_SHIFT,       /**< SMU peripheral identifier for LETIMER1.  */
  smuPeripheralLEUART0   = _SMU_PPUPATD0_LEUART0_SHIFT,        /**< SMU peripheral identifier for LEUART0.   */
  smuPeripheralLEUART1   = _SMU_PPUPATD0_LEUART1_SHIFT,        /**< SMU peripheral identifier for LEUART1.   */
  smuPeripheralPCNT0     = 32 + _SMU_PPUPATD1_PCNT0_SHIFT,     /**< SMU peripheral identifier for PCNT0.     */
  smuPeripheralPCNT1     = 32 + _SMU_PPUPATD1_PCNT1_SHIFT,     /**< SMU peripheral identifier for PCNT1.     */
  smuPeripheralPCNT2     = 32 + _SMU_PPUPATD1_PCNT2_SHIFT,     /**< SMU peripheral identifier for PCNT2.     */
#if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
  smuPeripheralQSPI0     = 32 + _SMU_PPUPATD1_QSPI0_SHIFT,     /**< SMU peripheral identifier for QSPI0.     */
#endif
  smuPeripheralRMU       = 32 + _SMU_PPUPATD1_RMU_SHIFT,       /**< SMU peripheral identifier for RMU.       */
  smuPeripheralRTC       = 32 + _SMU_PPUPATD1_RTC_SHIFT,       /**< SMU peripheral identifier for RTC.       */
  smuPeripheralRTCC      = 32 + _SMU_PPUPATD1_RTCC_SHIFT,      /**< SMU peripheral identifier for RTCC.      */
#if defined(_SMU_PPUPATD1_SDIO_SHIFT)
  smuPeripheralSDIO      = 32 + _SMU_PPUPATD1_SDIO_SHIFT,      /**< SMU peripheral identifier for SDIO.      */
#endif
  smuPeripheralSMU       = 32 + _SMU_PPUPATD1_SMU_SHIFT,       /**< SMU peripheral identifier for SMU.       */
  smuPeripheralTIMER0    = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,    /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTIMER1    = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,    /**< SMU peripheral identifier for TIMER1.    */
  smuPeripheralTIMER2    = 32 + _SMU_PPUPATD1_TIMER2_SHIFT,    /**< SMU peripheral identifier for TIMER2.    */
  smuPeripheralTIMER3    = 32 + _SMU_PPUPATD1_TIMER3_SHIFT,    /**< SMU peripheral identifier for TIMER3.    */
  smuPeripheralTRNG0     = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,     /**< SMU peripheral identifier for TRNG0.     */
  smuPeripheralUART0     = 32 + _SMU_PPUPATD1_UART0_SHIFT,     /**< SMU peripheral identifier for UART0.     */
  smuPeripheralUART1     = 32 + _SMU_PPUPATD1_UART1_SHIFT,     /**< SMU peripheral identifier for UART1.     */
  smuPeripheralUSART0    = 32 + _SMU_PPUPATD1_USART0_SHIFT,    /**< SMU peripheral identifier for USART0.    */
  smuPeripheralUSART1    = 32 + _SMU_PPUPATD1_USART1_SHIFT,    /**< SMU peripheral identifier for USART1.    */
  smuPeripheralUSART2    = 32 + _SMU_PPUPATD1_USART2_SHIFT,    /**< SMU peripheral identifier for USART2.    */
  smuPeripheralUSART3    = 32 + _SMU_PPUPATD1_USART3_SHIFT,    /**< SMU peripheral identifier for USART3.    */
  smuPeripheralUSART4    = 32 + _SMU_PPUPATD1_USART4_SHIFT,    /**< SMU peripheral identifier for USART4.    */
#if defined(_SMU_PPUPATD1_USB_SHIFT)
  smuPeripheralUSB       = 32 + _SMU_PPUPATD1_USB_SHIFT,       /**< SMU peripheral identifier for USB.       */
#endif
  smuPeripheralWDOG0     = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,     /**< SMU peripheral identifier for WDOG0.     */
  smuPeripheralWDOG1     = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,     /**< SMU peripheral identifier for WDOG1.     */
  smuPeripheralWTIMER0   = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,   /**< SMU peripheral identifier for WTIMER0.   */
  smuPeripheralWTIMER1   = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT,   /**< SMU peripheral identifier for WTIMER1.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
  smuPeripheralACMP0     = _SMU_PPUPATD0_ACMP0_SHIFT,          /**< SMU peripheral identifier for ACMP0.     */
  smuPeripheralACMP1     = _SMU_PPUPATD0_ACMP1_SHIFT,          /**< SMU peripheral identifier for ACMP1.     */
  smuPeripheralADC0      = _SMU_PPUPATD0_ADC0_SHIFT,           /**< SMU peripheral identifier for ADC0.      */
  smuPeripheralCAN0      = _SMU_PPUPATD0_CAN0_SHIFT,           /**< SMU peripheral identifier for CAN0.      */
  smuPeripheralCMU       = _SMU_PPUPATD0_CMU_SHIFT,            /**< SMU peripheral identifier for CMU.       */
  smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT,      /**< SMU peripheral identifier for CRYOTIMER. */
  smuPeripheralCRYPTO0   = _SMU_PPUPATD0_CRYPTO0_SHIFT,        /**< SMU peripheral identifier for CRYPTO0.   */
  smuPeripheralCSEN      = _SMU_PPUPATD0_CSEN_SHIFT,           /**< SMU peripheral identifier for CSEN.      */
  smuPeripheralVDAC0     = _SMU_PPUPATD0_VDAC0_SHIFT,          /**< SMU peripheral identifier for VDAC0.     */
  smuPeripheralPRS       = _SMU_PPUPATD0_PRS_SHIFT,            /**< SMU peripheral identifier for PRS.       */
  smuPeripheralEMU       = _SMU_PPUPATD0_EMU_SHIFT,            /**< SMU peripheral identifier for EMU.       */
  smuPeripheralGPCRC     = _SMU_PPUPATD0_GPCRC_SHIFT,          /**< SMU peripheral identifier for GPCRC.     */
  smuPeripheralGPIO      = _SMU_PPUPATD0_GPIO_SHIFT,           /**< SMU peripheral identifier for GPIO.      */
  smuPeripheralI2C0      = _SMU_PPUPATD0_I2C0_SHIFT,           /**< SMU peripheral identifier for I2C0.      */
  smuPeripheralI2C1      = _SMU_PPUPATD0_I2C1_SHIFT,           /**< SMU peripheral identifier for I2C1.      */
  smuPeripheralMSC       = _SMU_PPUPATD0_MSC_SHIFT,            /**< SMU peripheral identifier for MAC.       */
#if defined(_SMU_PPUPATD0_LCD_SHIFT)
  smuPeripheralLCD       = _SMU_PPUPATD0_LCD_SHIFT,            /**< SMU peripheral identifier for LCD.       */
#endif
  smuPeripheralLDMA      = _SMU_PPUPATD0_LDMA_SHIFT,           /**< SMU peripheral identifier for LDMA.      */
  smuPeripheralLESENSE   = _SMU_PPUPATD0_LESENSE_SHIFT,        /**< SMU peripheral identifier for LESENSE.   */
  smuPeripheralLETIMER0  = _SMU_PPUPATD0_LETIMER0_SHIFT,       /**< SMU peripheral identifier for LETIMER0.  */
  smuPeripheralLEUART0   = _SMU_PPUPATD0_LEUART0_SHIFT,        /**< SMU peripheral identifier for LEUART0.   */
  smuPeripheralPCNT0     = _SMU_PPUPATD0_PCNT0_SHIFT,          /**< SMU peripheral identifier for PCNT0.     */
  smuPeripheralRMU       = _SMU_PPUPATD0_RMU_SHIFT,            /**< SMU peripheral identifier for RMU.       */
  smuPeripheralRTCC      = _SMU_PPUPATD0_RTCC_SHIFT,           /**< SMU peripheral identifier for RTCC.      */
  smuPeripheralSMU       = _SMU_PPUPATD0_SMU_SHIFT,            /**< SMU peripheral identifier for SMU.       */
  smuPeripheralTIMER0    = _SMU_PPUPATD0_TIMER0_SHIFT,         /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTIMER1    = _SMU_PPUPATD0_TIMER1_SHIFT,         /**< SMU peripheral identifier for TIMER0.    */
  smuPeripheralTRNG0     = _SMU_PPUPATD0_TRNG0_SHIFT,          /**< SMU peripheral identifier for TRNG0.     */
  smuPeripheralUART0     = _SMU_PPUPATD0_UART0_SHIFT,          /**< SMU peripheral identifier for UART0.     */
  smuPeripheralUSART0    = _SMU_PPUPATD0_USART0_SHIFT,         /**< SMU peripheral identifier for USART0.    */
  smuPeripheralUSART1    = _SMU_PPUPATD0_USART1_SHIFT,         /**< SMU peripheral identifier for USART1.    */
  smuPeripheralUSART2    = _SMU_PPUPATD0_USART2_SHIFT,         /**< SMU peripheral identifier for USART2.    */
  smuPeripheralUSART3    = 32 + _SMU_PPUPATD1_USART3_SHIFT,    /**< SMU peripheral identifier for USART3.    */
  smuPeripheralWDOG0     = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,     /**< SMU peripheral identifier for WDOG0.     */
  smuPeripheralWTIMER0   = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,   /**< SMU peripheral identifier for WTIMER0.   */
  smuPeripheralWTIMER1   = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT,   /**< SMU peripheral identifier for WTIMER1.   */

#elif defined(_SILICON_LABS_32B_SERIES_2)
#if defined(SMU_PPUPATD0_SCRATCHPAD)
  smuPeripheralSCRATCHPAD   = _SMU_PPUPATD0_SCRATCHPAD_SHIFT,     /**< SMU peripheral identifier for SCRATCHPAD */
#endif
  smuPeripheralEMU          = _SMU_PPUPATD0_EMU_SHIFT,            /**< SMU peripheral identifier for EMU       */
  smuPeripheralCMU          = _SMU_PPUPATD0_CMU_SHIFT,            /**< SMU peripheral identifier for CMU       */
  smuPeripheralHFXO         = _SMU_PPUPATD0_HFXO0_SHIFT,          /**< SMU peripheral identifier for HFXO0     */
  smuPeripheralHFRCO0       = _SMU_PPUPATD0_HFRCO0_SHIFT,         /**< SMU peripheral identifier for HFRCO0    */
  smuPeripheralFSRCO        = _SMU_PPUPATD0_FSRCO_SHIFT,          /**< SMU peripheral identifier for FSRCO     */
  smuPeripheralDPLL0        = _SMU_PPUPATD0_DPLL0_SHIFT,          /**< SMU peripheral identifier for DPLL0     */
  smuPeripheralLFXO         = _SMU_PPUPATD0_LFXO_SHIFT,           /**< SMU peripheral identifier for LFXO      */
  smuPeripheralLFRCO        = _SMU_PPUPATD0_LFRCO_SHIFT,          /**< SMU peripheral identifier for LFRCO     */
  smuPeripheralULFRCO       = _SMU_PPUPATD0_ULFRCO_SHIFT,         /**< SMU peripheral identifier for ULFRCO    */
  smuPeripheralMSC          = _SMU_PPUPATD0_MSC_SHIFT,            /**< SMU peripheral identifier for MSC       */
  smuPeripheralICACHE0      = _SMU_PPUPATD0_ICACHE0_SHIFT,        /**< SMU peripheral identifier for ICACHE0   */
  smuPeripheralPRS          = _SMU_PPUPATD0_PRS_SHIFT,            /**< SMU peripheral identifier for PRS       */
  smuPeripheralGPIO         = _SMU_PPUPATD0_GPIO_SHIFT,           /**< SMU peripheral identifier for GPIO      */
  smuPeripheralLDMA         = _SMU_PPUPATD0_LDMA_SHIFT,           /**< SMU peripheral identifier for LDMA      */
  smuPeripheralLDMAXBAR     = _SMU_PPUPATD0_LDMAXBAR_SHIFT,       /**< SMU peripheral identifier for LDMAXBAR  */
  smuPeripheralTIMER0       = _SMU_PPUPATD0_TIMER0_SHIFT,         /**< SMU peripheral identifier for TIMER0    */
  smuPeripheralTIMER1       = _SMU_PPUPATD0_TIMER1_SHIFT,         /**< SMU peripheral identifier for TIMER1    */
  smuPeripheralTIMER2       = _SMU_PPUPATD0_TIMER2_SHIFT,         /**< SMU peripheral identifier for TIMER2    */
  smuPeripheralTIMER3       = _SMU_PPUPATD0_TIMER3_SHIFT,         /**< SMU peripheral identifier for TIMER3    */
  smuPeripheralUSART0       = _SMU_PPUPATD0_USART0_SHIFT,         /**< SMU peripheral identifier for USART0    */
  smuPeripheralUSART1       = _SMU_PPUPATD0_USART1_SHIFT,         /**< SMU peripheral identifier for USART1    */
#if USART_COUNT > 2
  smuPeripheralUSART2       = _SMU_PPUPATD0_USART2_SHIFT,         /**< SMU peripheral identifier for USART2    */
#endif
  smuPeripheralBURTC        = _SMU_PPUPATD0_BURTC_SHIFT,          /**< SMU peripheral identifier for BURTC     */
  smuPeripheralI2C1         = _SMU_PPUPATD0_I2C1_SHIFT,           /**< SMU peripheral identifier for I2C1      */
  smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT,   /**< SMU peripheral identifier for CHIPTESTCTRL*/
#if defined(SMU_PPUPATD0_LVGD)
  smuPeripheralLVGD         = _SMU_PPUPATD0_LVGD_SHIFT,           /**< SMU peripheral identifier for LVGD      */
#endif
  smuPeripheralSYSCFG       = _SMU_PPUPATD0_SYSCFG_SHIFT,         /**< SMU peripheral identifier for SYSCFG    */
  smuPeripheralBURAM        = _SMU_PPUPATD0_BURAM_SHIFT,          /**< SMU peripheral identifier for BURAM     */
  smuPeripheralIFADCDEBUG   = _SMU_PPUPATD0_IFADCDEBUG_SHIFT,     /**< SMU peripheral identifier for IFADCDEBUG*/
  smuPeripheralGPCRC        = _SMU_PPUPATD0_GPCRC_SHIFT,          /**< SMU peripheral identifier for GPCRC     */
#if defined(_SMU_PPUPATD0_RTCC_SHIFT)
  smuPeripheralRTCC         = _SMU_PPUPATD0_RTCC_SHIFT,           /**< SMU peripheral identifier for RTCC      */
#endif
#if defined(_SMU_PPUPATD1_RTCC_SHIFT)
  smuPeripheralRTCC         = 32 + _SMU_PPUPATD1_RTCC_SHIFT,      /**< SMU peripheral identifier for RTCC      */
#endif
#if defined(_SMU_PPUPATD1_DCDC_SHIFT)
  smuPeripheralDCDC         = 32 + _SMU_PPUPATD1_DCDC_SHIFT,      /**< SMU peripheral identifier for DCDC      */
#endif
#if defined(_SMU_PPUPATD1_PDM_SHIFT)
  smuPeripheralPDM          = 32 + _SMU_PPUPATD1_PDM_SHIFT,       /**< SMU peripheral identifier for PDM       */
#endif
#if defined(_SMU_PPUPATD1_RFSENSE_SHIFT)
  smuPeripheralRFSENSE      = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT,   /**< SMU peripheral identifier for RFSENSE   */
#endif
  smuPeripheralLETIMER0     = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT,  /**< SMU peripheral identifier for LETIMER   */
  smuPeripheralIADC0        = 32 + _SMU_PPUPATD1_IADC0_SHIFT,     /**< SMU peripheral identifier for IADC0     */
#if defined(ACMP_PRESENT)
  smuPeripheralACMP0        = 32 + _SMU_PPUPATD1_ACMP0_SHIFT,     /**< SMU peripheral identifier for ACMP0     */
  smuPeripheralACMP1        = 32 + _SMU_PPUPATD1_ACMP1_SHIFT,     /**< SMU peripheral identifier for ACMP1     */
#endif
  smuPeripheralI2C0         = 32 + _SMU_PPUPATD1_I2C0_SHIFT,      /**< SMU peripheral identifier for I2C0      */
#if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT)
  smuPeripheralHFRCOEM23    = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */
#endif
  smuPeripheralWDOG0        = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,     /**< SMU peripheral identifier for WDOG0     */
#if defined(_SMU_PPUPATD1_WDOG1_SHIFT)
  smuPeripheralWDOG1        = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,     /**< SMU peripheral identifier for WDOG1     */
#endif
  smuPeripheralAMUXCP0      = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT,   /**< SMU peripheral identifier for AMUXCP0   */
  smuPeripheralRADIOAES     = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT,  /**< SMU peripheral identifier for RADIOAES  */
#if defined(_SMU_PPUPATD1_EUART0_SHIFT)
  smuPeripheralEUART0       = 32 + _SMU_PPUPATD1_EUART0_SHIFT,    /**< SMU peripheral identifier for EUART0    */
#endif
  smuPeripheralBUFC         = 32 + _SMU_PPUPATD1_BUFC_SHIFT,      /**< SMU peripheral identifier for BUFC      */
  smuPeripheralSMU          = 32 + _SMU_PPUPATD1_SMU_SHIFT,       /**< SMU peripheral identifier for SMU       */
#if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT)
  smuPeripheralSMUCFGNS     = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT,  /**< SMU peripheral identifier for SMUCFGNS  */
#endif
  smuPeripheralAHBRADIO     = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT,  /**< SMU peripheral identifier for AHBRADIO  */
#if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT)
  smuPeripheralSEMAILBOX    = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */
#endif
#if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT)
  smuPeripheralCRYPTOACC    = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */
#endif
#else
#error "No peripherals defined for SMU for this device configuration."
#endif
  smuPeripheralEnd
} SMU_Peripheral_TypeDef;

/** SMU peripheral privileged access enablers. */
typedef struct {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
  bool privilegedACMP0      : 1;     /**< Privileged access enabler for ACMP0.     */
  bool privilegedACMP1      : 1;     /**< Privileged access enabler for ACMP1.     */
  bool privilegedADC0       : 1;     /**< Privileged access enabler for ADC0.      */
  bool privilegedReserved0  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved1  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedCMU        : 1;     /**< Privileged access enabler for CMU.       */
  bool privilegedReserved2  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedCRYOTIMER  : 1;     /**< Privileged access enabler for CRYOTIMER. */
  bool privilegedCRYPTO0    : 1;     /**< Privileged access enabler for CRYPTO0.   */
  bool privilegedCRYPTO1    : 1;     /**< Privileged access enabler for CRYPTO1.   */
  bool privilegedCSEN       : 1;     /**< Privileged access enabler for CSEN.      */
  bool privilegedVDAC0      : 1;     /**< Privileged access enabler for VDAC0.     */
  bool privilegedPRS        : 1;     /**< Privileged access enabler for PRS.       */
  bool privilegedEMU        : 1;     /**< Privileged access enabler for EMU.       */
  bool privilegedFPUEH      : 1;     /**< Privileged access enabler for FPUEH.     */
  bool privilegedReserved3  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedGPCRC      : 1;     /**< Privileged access enabler for GPCRC.     */
  bool privilegedGPIO       : 1;     /**< Privileged access enabler for GPIO.      */
  bool privilegedI2C0       : 1;     /**< Privileged access enabler for I2C0.      */
  bool privilegedI2C1       : 1;     /**< Privileged access enabler for I2C1.      */
  bool privilegedIDAC0      : 1;     /**< Privileged access enabler for IDAC0.     */
  bool privilegedMSC        : 1;     /**< Privileged access enabler for MSC.       */
  bool privilegedLDMA       : 1;     /**< Privileged access enabler for LDMA.      */
  bool privilegedLESENSE    : 1;     /**< Privileged access enabler for LESENSE.   */
  bool privilegedLETIMER0   : 1;     /**< Privileged access enabler for LETIMER0.  */
  bool privilegedLEUART0    : 1;     /**< Privileged access enabler for LEUART0.   */
  bool privilegedReserved4  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedPCNT0      : 1;     /**< Privileged access enabler for PCNT0.     */
  bool privilegedPCNT1      : 1;     /**< Privileged access enabler for PCNT1.     */
  bool privilegedPCNT2      : 1;     /**< Privileged access enabler for PCNT2.     */
  bool privilegedReserved5  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved6  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved7  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedRMU        : 1;     /**< Privileged access enabler for RMU.       */
  bool privilegedRTCC       : 1;     /**< Privileged access enabler for RTCC.      */
  bool privilegedSMU        : 1;     /**< Privileged access enabler for SMU.       */
  bool privilegedReserved8  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedTIMER0     : 1;     /**< Privileged access enabler for TIMER0.    */
  bool privilegedTIMER1     : 1;     /**< Privileged access enabler for TIMER1.    */
  bool privilegedTRNG0      : 1;     /**< Privileged access enabler for TRNG0.     */
  bool privilegedUSART0     : 1;     /**< Privileged access enabler for USART0.    */
  bool privilegedUSART1     : 1;     /**< Privileged access enabler for USART1.    */
  bool privilegedUSART2     : 1;     /**< Privileged access enabler for USART2.    */
  bool privilegedUSART3     : 1;     /**< Privileged access enabler for USART3.    */
  bool privilegedWDOG0      : 1;     /**< Privileged access enabler for WDOG0.     */
  bool privilegedWDOG1      : 1;     /**< Privileged access enabler for WDOG1.     */
  bool privilegedWTIMER0    : 1;     /**< Privileged access enabler for WTIMER0.   */
  bool privilegedWTIMER1    : 1;     /**< Privileged access enabler for WTIMER1.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
  bool privilegedACMP0      : 1;     /**< Privileged access enabler for ACMP0.     */
  bool privilegedACMP1      : 1;     /**< Privileged access enabler for ACMP1.     */
  bool privilegedADC0       : 1;     /**< Privileged access enabler for ADC0.      */
  bool privilegedReserved0  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved1  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedCMU        : 1;     /**< Privileged access enabler for CMU.       */
  bool privilegedReserved2  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedCRYOTIMER  : 1;     /**< Privileged access enabler for CRYOTIMER. */
  bool privilegedCRYPTO0    : 1;     /**< Privileged access enabler for CRYPTO0.   */
  bool privilegedCRYPTO1    : 1;     /**< Privileged access enabler for CRYPTO1.   */
  bool privilegedCSEN       : 1;     /**< Privileged access enabler for CSEN.      */
  bool privilegedVDAC0      : 1;     /**< Privileged access enabler for VDAC0.     */
  bool privilegedPRS        : 1;     /**< Privileged access enabler for PRS.       */
  bool privilegedEMU        : 1;     /**< Privileged access enabler for EMU.       */
  bool privilegedFPUEH      : 1;     /**< Privileged access enabler for FPUEH.     */
  bool privilegedReserved3  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedGPCRC      : 1;     /**< Privileged access enabler for GPCRC.     */
  bool privilegedGPIO       : 1;     /**< Privileged access enabler for GPIO.      */
  bool privilegedI2C0       : 1;     /**< Privileged access enabler for I2C0.      */
  bool privilegedI2C1       : 1;     /**< Privileged access enabler for I2C1.      */
  bool privilegedIDAC0      : 1;     /**< Privileged access enabler for IDAC0.     */
  bool privilegedMSC        : 1;     /**< Privileged access enabler for MSC.       */
  bool privilegedLDMA       : 1;     /**< Privileged access enabler for LDMA.      */
  bool privilegedLESENSE    : 1;     /**< Privileged access enabler for LESENSE.   */
  bool privilegedLETIMER0   : 1;     /**< Privileged access enabler for LETIMER0.  */
  bool privilegedLEUART0    : 1;     /**< Privileged access enabler for LEUART0.   */
  bool privilegedReserved4  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedPCNT0      : 1;     /**< Privileged access enabler for PCNT0.     */
  bool privilegedReserved5  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved6  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved7  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved8  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedRMU        : 1;     /**< Privileged access enabler for RMU.       */
  bool privilegedRTCC       : 1;     /**< Privileged access enabler for RTCC.      */
  bool privilegedSMU        : 1;     /**< Privileged access enabler for SMU.       */
  bool privilegedReserved9  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedTIMER0     : 1;     /**< Privileged access enabler for TIMER0.    */
  bool privilegedTIMER1     : 1;     /**< Privileged access enabler for TIMER1.    */
  bool privilegedTRNG0      : 1;     /**< Privileged access enabler for TRNG0.     */
  bool privilegedUSART0     : 1;     /**< Privileged access enabler for USART0.    */
  bool privilegedUSART1     : 1;     /**< Privileged access enabler for USART1.    */
  bool privilegedUSART2     : 1;     /**< Privileged access enabler for USART2.    */
  bool privilegedWDOG0      : 1;     /**< Privileged access enabler for WDOG0.     */
  bool privilegedWDOG1      : 1;     /**< Privileged access enabler for WDOG1.     */
  bool privilegedWTIMER0    : 1;     /**< Privileged access enabler for WTIMER0.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
  bool privilegedACMP0      : 1;     /**< Privileged access enabler for ACMP0.     */
  bool privilegedACMP1      : 1;     /**< Privileged access enabler for ACMP1.     */
  bool privilegedADC0       : 1;     /**< Privileged access enabler for ADC0.      */
  bool privilegedReserved0  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved1  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedCMU        : 1;     /**< Privileged access enabler for CMU.       */
  bool privilegedReserved2  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedCRYOTIMER  : 1;     /**< Privileged access enabler for CRYOTIMER. */
  bool privilegedCRYPTO     : 1;     /**< Privileged access enabler for CRYPTO.    */
  bool privilegedVDAC0      : 1;     /**< Privileged access enabler for VDAC0.     */
  bool privilegedPRS        : 1;     /**< Privileged access enabler for PRS.       */
  bool privilegedEMU        : 1;     /**< Privileged access enabler for EMU.       */
  bool privilegedFPUEH      : 1;     /**< Privileged access enabler for FPUEH.     */
  bool privilegedReserved3  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedGPCRC      : 1;     /**< Privileged access enabler for GPCRC.     */
  bool privilegedGPIO       : 1;     /**< Privileged access enabler for GPIO.      */
  bool privilegedI2C0       : 1;     /**< Privileged access enabler for I2C0.      */
  bool privilegedIDAC0      : 1;     /**< Privileged access enabler for IDAC0.     */
  bool privilegedMSC        : 1;     /**< Privileged access enabler for MSC.       */
  bool privilegedLDMA       : 1;     /**< Privileged access enabler for LDMA.      */
  bool privilegedLESENSE    : 1;     /**< Privileged access enabler for LESENSE.   */
  bool privilegedLETIMER0   : 1;     /**< Privileged access enabler for LETIMER0.  */
  bool privilegedLEUART     : 1;     /**< Privileged access enabler for LEUART0.   */
  bool privilegedReserved4  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedPCNT0      : 1;     /**< Privileged access enabler for PCNT0.     */
  bool privilegedReserved5  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved6  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved7  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved8  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedRMU        : 1;     /**< Privileged access enabler for RMU.       */
  bool privilegedRTCC       : 1;     /**< Privileged access enabler for RTCC.      */
  bool privilegedSMU        : 1;     /**< Privileged access enabler for SMU.       */

  bool privilegedReserved9  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedTIMER0     : 1;     /**< Privileged access enabler for TIMER0.    */
  bool privilegedTIMER1     : 1;     /**< Privileged access enabler for TIMER1.    */
  bool privilegedTRNG0      : 1;     /**< Privileged access enabler for TRNG0.     */
  bool privilegedUSART0     : 1;     /**< Privileged access enabler for USART0.    */
  bool privilegedUSART1     : 1;     /**< Privileged access enabler for USART1.    */
  bool privilegedWDOG0      : 1;     /**< Privileged access enabler for WDOG0.     */
  bool privilegedWDOG1      : 1;     /**< Privileged access enabler for WDOG1.     */
  bool privilegedWTIMER0    : 1;     /**< Privileged access enabler for WTIMER0.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
  bool privilegedACMP0      : 1;     /**< Privileged access enabler for ACMP0.     */
  bool privilegedACMP1      : 1;     /**< Privileged access enabler for ACMP1.     */
  bool privilegedACMP2      : 1;     /**< Privileged access enabler for ACMP2.     */
  bool privilegedACMP3      : 1;     /**< Privileged access enabler for ACMP3.     */
  bool privilegedADC0       : 1;     /**< Privileged access enabler for ADC0.      */
  bool privilegedADC1       : 1;     /**< Privileged access enabler for ADC1.      */
  bool privilegedCAN0       : 1;     /**< Privileged access enabler for CAN0.      */
  bool privilegedCAN1       : 1;     /**< Privileged access enabler for CAN1.      */
  bool privilegedCMU        : 1;     /**< Privileged access enabler for CMU.       */
  bool privilegedCRYOTIMER  : 1;     /**< Privileged access enabler for CRYOTIMER. */
  bool privilegedCRYPTO0    : 1;     /**< Privileged access enabler for CRYPTO0.   */
  bool privilegedCSEN       : 1;     /**< Privileged access enabler for CSEN.      */
  bool privilegedVDAC0      : 1;     /**< Privileged access enabler for VDAC0.     */
  bool privilegedPRS        : 1;     /**< Privileged access enabler for PRS.       */
  bool privilegedEBI        : 1;     /**< Privileged access enabler for EBI.       */
  bool privilegedEMU        : 1;     /**< Privileged access enabler for EMU.       */
  bool privilegedETH        : 1;     /**< Privileged access enabler for ETH.       */
  bool privilegedFPUEH      : 1;     /**< Privileged access enabler for FPUEH.     */
  bool privilegedGPCRC      : 1;     /**< Privileged access enabler for GPCRC.     */
  bool privilegedGPIO       : 1;     /**< Privileged access enabler for GPIO.      */
  bool privilegedI2C0       : 1;     /**< Privileged access enabler for I2C0.      */
  bool privilegedI2C1       : 1;     /**< Privileged access enabler for I2C1.      */
  bool privilegedI2C2       : 1;     /**< Privileged access enabler for I2C2.      */
  bool privilegedIDAC0      : 1;     /**< Privileged access enabler for IDAC0.     */
  bool privilegedMSC        : 1;     /**< Privileged access enabler for MAC.       */
  bool privilegedLCD        : 1;     /**< Privileged access enabler for LCD.       */
  bool privilegedLDMA       : 1;     /**< Privileged access enabler for LDMA.      */
  bool privilegedLESENSE    : 1;     /**< Privileged access enabler for LESENSE.   */
  bool privilegedLETIMER0   : 1;     /**< Privileged access enabler for LETIMER0.  */
  bool privilegedLETIMER1   : 1;     /**< Privileged access enabler for LETIMER1.  */
  bool privilegedLEUART0    : 1;     /**< Privileged access enabler for LEUART0.   */
  bool privilegedLEUART1    : 1;     /**< Privileged access enabler for LEUART1.   */
  bool privilegedPCNT0      : 1;     /**< Privileged access enabler for PCNT0.     */
  bool privilegedPCNT1      : 1;     /**< Privileged access enabler for PCNT1.     */
  bool privilegedPCNT2      : 1;     /**< Privileged access enabler for PCNT2.     */
  bool privilegedQSPI0      : 1;     /**< Privileged access enabler for QSPI0.     */
  bool privilegedRMU        : 1;     /**< Privileged access enabler for RMU.       */
  bool privilegedRTC        : 1;     /**< Privileged access enabler for RTC.       */
  bool privilegedRTCC       : 1;     /**< Privileged access enabler for RTCC.      */
  bool privilegedSDIO       : 1;     /**< Privileged access enabler for SDIO.      */
  bool privilegedSMU        : 1;     /**< Privileged access enabler for SMU.       */
  bool privilegedTIMER0     : 1;     /**< Privileged access enabler for TIMER0.    */
  bool privilegedTIMER1     : 1;     /**< Privileged access enabler for TIMER1.    */
  bool privilegedTIMER2     : 1;     /**< Privileged access enabler for TIMER2.    */
  bool privilegedTIMER3     : 1;     /**< Privileged access enabler for TIMER3.    */
  bool privilegedTIMER4     : 1;     /**< Privileged access enabler for TIMER4.    */
  bool privilegedTIMER5     : 1;     /**< Privileged access enabler for TIMER5.    */
  bool privilegedTIMER6     : 1;     /**< Privileged access enabler for TIMER6.    */
  bool privilegedTRNG0      : 1;     /**< Privileged access enabler for TRNG0.     */
  bool privilegedUART0      : 1;     /**< Privileged access enabler for UART0.     */
  bool privilegedUART1      : 1;     /**< Privileged access enabler for UART1.     */
  bool privilegedUSART0     : 1;     /**< Privileged access enabler for USART0.    */
  bool privilegedUSART1     : 1;     /**< Privileged access enabler for USART1.    */
  bool privilegedUSART2     : 1;     /**< Privileged access enabler for USART2.    */
  bool privilegedUSART3     : 1;     /**< Privileged access enabler for USART3.    */
  bool privilegedUSART4     : 1;     /**< Privileged access enabler for USART4.    */
  bool privilegedUSART5     : 1;     /**< Privileged access enabler for USART5.    */
  bool privilegedUSB        : 1;     /**< Privileged access enabler for USB.       */
  bool privilegedWDOG0      : 1;     /**< Privileged access enabler for WDOG0.     */
  bool privilegedWDOG1      : 1;     /**< Privileged access enabler for WDOG1.     */
  bool privilegedWTIMER0    : 1;     /**< Privileged access enabler for WTIMER0.   */
  bool privilegedWTIMER1    : 1;     /**< Privileged access enabler for WTIMER1.   */
  bool privilegedWTIMER2    : 1;     /**< Privileged access enabler for WTIMER2.   */
  bool privilegedWTIMER3    : 1;     /**< Privileged access enabler for WTIMER3.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
  bool privilegedACMP0      : 1;     /**< Privileged access enabler for ACMP0.     */
  bool privilegedACMP1      : 1;     /**< Privileged access enabler for ACMP1.     */
  bool privilegedADC0       : 1;     /**< Privileged access enabler for ADC0.      */
  bool privilegedCAN0       : 1;     /**< Privileged access enabler for CAN0.      */
  bool privilegedCMU        : 1;     /**< Privileged access enabler for CMU.       */
  bool privilegedCRYOTIMER  : 1;     /**< Privileged access enabler for CRYOTIMER. */
  bool privilegedCRYPTO0    : 1;     /**< Privileged access enabler for CRYPTO0.   */
  bool privilegedCSEN       : 1;     /**< Privileged access enabler for CSEN.      */
  bool privilegedVDAC0      : 1;     /**< Privileged access enabler for VDAC0.     */
  bool privilegedPRS        : 1;     /**< Privileged access enabler for PRS.       */
  bool privilegedEMU        : 1;     /**< Privileged access enabler for EMU.       */
  bool privilegedGPCRC      : 1;     /**< Privileged access enabler for GPCRC.     */
  bool privilegedGPIO       : 1;     /**< Privileged access enabler for GPIO.      */
  bool privilegedI2C0       : 1;     /**< Privileged access enabler for I2C0.      */
  bool privilegedI2C1       : 1;     /**< Privileged access enabler for I2C1.      */
  bool privilegedMSC        : 1;     /**< Privileged access enabler for MAC.       */
  bool privilegedLCD        : 1;     /**< Privileged access enabler for LCD.       */
  bool privilegedLDMA       : 1;     /**< Privileged access enabler for LDMA.      */
  bool privilegedLESENSE    : 1;     /**< Privileged access enabler for LESENSE.   */
  bool privilegedLETIMER0   : 1;     /**< Privileged access enabler for LETIMER0.  */
  bool privilegedLEUART0    : 1;     /**< Privileged access enabler for LEUART0.   */
  bool privilegedPCNT0      : 1;     /**< Privileged access enabler for PCNT0.     */
  bool privilegedRMU        : 1;     /**< Privileged access enabler for RMU.       */
  bool privilegedRTCC       : 1;     /**< Privileged access enabler for RTCC.      */
  bool privilegedSMU        : 1;     /**< Privileged access enabler for SMU.       */
  bool privilegedTIMER0     : 1;     /**< Privileged access enabler for TIMER0.    */
  bool privilegedTIMER1     : 1;     /**< Privileged access enabler for TIMER1.    */
  bool privilegedTRNG0      : 1;     /**< Privileged access enabler for TRNG0.     */
  bool privilegedUART0      : 1;     /**< Privileged access enabler for UART0.     */
  bool privilegedUSART0     : 1;     /**< Privileged access enabler for USART0.    */
  bool privilegedUSART1     : 1;     /**< Privileged access enabler for USART1.    */
  bool privilegedUSART2     : 1;     /**< Privileged access enabler for USART2.    */
  bool privilegedUSART3     : 1;     /**< Privileged access enabler for USART3.    */
  bool privilegedWDOG0      : 1;     /**< Privileged access enabler for WDOG0.     */
  bool privilegedWTIMER0    : 1;     /**< Privileged access enabler for WTIMER0.   */
  bool privilegedWTIMER1    : 1;     /**< Privileged access enabler for WTIMER1.   */

#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
  bool privilegedACMP0      : 1;     /**< Privileged access enabler for ACMP0.     */
  bool privilegedACMP1      : 1;     /**< Privileged access enabler for ACMP1.     */
  bool privilegedACMP2      : 1;     /**< Privileged access enabler for ACMP2.     */
  bool privilegedADC0       : 1;     /**< Privileged access enabler for ADC0.      */
  bool privilegedADC1       : 1;     /**< Privileged access enabler for ADC1.      */
  bool privilegedCAN0       : 1;     /**< Privileged access enabler for CAN0.      */
  bool privilegedCAN1       : 1;     /**< Privileged access enabler for CAN1.      */
  bool privilegedCMU        : 1;     /**< Privileged access enabler for CMU.       */
  bool privilegedCRYOTIMER  : 1;     /**< Privileged access enabler for CRYOTIMER. */
  bool privilegedCRYPTO0    : 1;     /**< Privileged access enabler for CRYPTO0.   */
  bool privilegedCSEN       : 1;     /**< Privileged access enabler for CSEN.      */
  bool privilegedVDAC0      : 1;     /**< Privileged access enabler for VDAC0.     */
  bool privilegedPRS        : 1;     /**< Privileged access enabler for PRS.       */
  bool privilegedEBI        : 1;     /**< Privileged access enabler for EBI.       */
  bool privilegedEMU        : 1;     /**< Privileged access enabler for EMU.       */
  bool privilegedFPUEH      : 1;     /**< Privileged access enabler for FPUEH.     */
  bool privilegedGPCRC      : 1;     /**< Privileged access enabler for GPCRC.     */
  bool privilegedGPIO       : 1;     /**< Privileged access enabler for GPIO.      */
  bool privilegedI2C0       : 1;     /**< Privileged access enabler for I2C0.      */
  bool privilegedI2C1       : 1;     /**< Privileged access enabler for I2C1.      */
  bool privilegedIDAC0      : 1;     /**< Privileged access enabler for IDAC0.     */
  bool privilegedMSC        : 1;     /**< Privileged access enabler for MAC.       */
  bool privilegedLCD        : 1;     /**< Privileged access enabler for LCD.       */
  bool privilegedLDMA       : 1;     /**< Privileged access enabler for LDMA.      */
  bool privilegedLESENSE    : 1;     /**< Privileged access enabler for LESENSE.   */
  bool privilegedLETIMER0   : 1;     /**< Privileged access enabler for LETIMER0.  */
  bool privilegedLETIMER1   : 1;     /**< Privileged access enabler for LETIMER1.  */
  bool privilegedLEUART0    : 1;     /**< Privileged access enabler for LEUART0.   */
  bool privilegedLEUART1    : 1;     /**< Privileged access enabler for LEUART1.   */
  bool privilegedReserved0  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved1  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedReserved2  : 1;     /**< Reserved privileged access enabler.      */
  bool privilegedPCNT0      : 1;     /**< Privileged access enabler for PCNT0.     */
  bool privilegedPCNT1      : 1;     /**< Privileged access enabler for PCNT1.     */
  bool privilegedPCNT2      : 1;     /**< Privileged access enabler for PCNT2.     */
  bool privilegedPDM        : 1;     /**< Privileged access enabler for PDM.       */
  bool privilegedQSPI0      : 1;     /**< Privileged access enabler for QSPI0.     */
  bool privilegedRMU        : 1;     /**< Privileged access enabler for RMU.       */
  bool privilegedRTC        : 1;     /**< Privileged access enabler for RTC.       */
  bool privilegedRTCC       : 1;     /**< Privileged access enabler for RTCC.      */
  bool privilegedSDIO       : 1;     /**< Privileged access enabler for SDIO.      */
  bool privilegedSMU        : 1;     /**< Privileged access enabler for SMU.       */
  bool privilegedTIMER0     : 1;     /**< Privileged access enabler for TIMER0.    */
  bool privilegedTIMER1     : 1;     /**< Privileged access enabler for TIMER1.    */
  bool privilegedTIMER2     : 1;     /**< Privileged access enabler for TIMER2.    */
  bool privilegedTIMER3     : 1;     /**< Privileged access enabler for TIMER3.    */
  bool privilegedTRNG0      : 1;     /**< Privileged access enabler for TRNG0.     */
  bool privilegedUART0      : 1;     /**< Privileged access enabler for UART0.     */
  bool privilegedUART1      : 1;     /**< Privileged access enabler for UART1.     */
  bool privilegedUSART0     : 1;     /**< Privileged access enabler for USART0.    */
  bool privilegedUSART1     : 1;     /**< Privileged access enabler for USART1.    */
  bool privilegedUSART2     : 1;     /**< Privileged access enabler for USART2.    */
  bool privilegedUSART3     : 1;     /**< Privileged access enabler for USART3.    */
  bool privilegedUSART4     : 1;     /**< Privileged access enabler for USART4.    */
  bool privilegedUSB        : 1;     /**< Privileged access enabler for USB.       */
  bool privilegedWDOG0      : 1;     /**< Privileged access enabler for WDOG0.     */
  bool privilegedWDOG1      : 1;     /**< Privileged access enabler for WDOG1.     */
  bool privilegedWTIMER0    : 1;     /**< Privileged access enabler for WTIMER0.   */
  bool privilegedWTIMER1    : 1;     /**< Privileged access enabler for WTIMER1.   */

#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
  bool privilegedReserved0    : 1;
  bool privilegedEMU          : 1;  /**< Privileged access enabler for EMU          */
  bool privilegedCMU          : 1;  /**< Privileged access enabler for CMU          */
  bool privilegedHFXO0        : 1;  /**< Privileged access enabler for HFXO0        */
  bool privilegedHFRCO0       : 1;  /**< Privileged access enabler for HFRCO0       */
  bool privilegedFSRCO        : 1;  /**< Privileged access enabler for FSRCO        */
  bool privilegedDPLL0        : 1;  /**< Privileged access enabler for DPLL0        */
  bool privilegedLFXO         : 1;  /**< Privileged access enabler for LFXO         */
  bool privilegedLFRCO        : 1;  /**< Privileged access enabler for LFRCO        */
  bool privilegedULFRCO       : 1;  /**< Privileged access enabler for ULFRCO       */
  bool privilegedMSC          : 1;  /**< Privileged access enabler for MSC          */
  bool privilegedICACHE0      : 1;  /**< Privileged access enabler for ICACHE0      */
  bool privilegedPRS          : 1;  /**< Privileged access enabler for PRS          */
  bool privilegedGPIO         : 1;  /**< Privileged access enabler for GPIO         */
  bool privilegedLDMA         : 1;  /**< Privileged access enabler for LDMA         */
  bool privilegedLDMAXBAR     : 1;  /**< Privileged access enabler for LDMAXBAR     */
  bool privilegedTIMER0       : 1;  /**< Privileged access enabler for TIMER0       */
  bool privilegedTIMER1       : 1;  /**< Privileged access enabler for TIMER1       */
  bool privilegedTIMER2       : 1;  /**< Privileged access enabler for TIMER2       */
  bool privilegedTIMER3       : 1;  /**< Privileged access enabler for TIMER3       */
  bool privilegedUSART0       : 1;  /**< Privileged access enabler for USART0       */
  bool privilegedUSART1       : 1;  /**< Privileged access enabler for USART1       */
  bool privilegedUSART2       : 1;  /**< Privileged access enabler for USART2       */
  bool privilegedBURTC        : 1;  /**< Privileged access enabler for BURTC        */
  bool privilegedI2C1         : 1;  /**< Privileged access enabler for I2C1         */
  bool privilegedCHIPTESTCTRL : 1;  /**< Privileged access enabler for CHIPTESTCTRL */
  bool privilegedLVGD         : 1;  /**< Privileged access enabler for LVGD         */
  bool privilegedSYSCFG       : 1;  /**< Privileged access enabler for SYSCFG       */
  bool privilegedBURAM        : 1;  /**< Privileged access enabler for BURAM        */
  bool privilegedIFADCDEBUG   : 1;  /**< Privileged access enabler for IFADCDEBUG   */
  bool privilegedGPCRC        : 1;  /**< Privileged access enabler for GPCRC        */
  bool privilegedRTCC         : 1;  /**< Privileged access enabler for RTCC         */

  bool privilegedLETIMER0     : 1;  /**< Privileged access enabler for LETIMER      */
  bool privilegedIADC0        : 1;  /**< Privileged access enabler for IADC0        */
  bool privilegedACMP0        : 1;  /**< Privileged access enabler for ACMP0        */
  bool privilegedACMP1        : 1;  /**< Privileged access enabler for ACMP1        */
  bool privilegedI2C0         : 1;  /**< Privileged access enabler for I2C0         */
  bool privilegedHFRCOEM23    : 1;  /**< Privileged access enabler for HFRCOEM23    */
  bool privilegedWDOG0        : 1;  /**< Privileged access enabler for WDOG0        */
  bool privilegedWDOG1        : 1;  /**< Privileged access enabler for WDOG1        */
  bool privilegedAMUXCP0      : 1;  /**< Privileged access enabler for AMUXCP0      */
  bool privilegedRADIOAES     : 1;  /**< Privileged access enabler for RADIOAES     */
  bool privilegedBUFC         : 1;  /**< Privileged access enabler for BUFC         */
  bool privilegedSMU          : 1;  /**< Privileged access enabler for SMU          */
  bool privilegedAHBRADIO     : 1;  /**< Privileged access enabler for AHBRADIO     */
  bool privilegedSEMAILBOX    : 1;  /**< Privileged access enabler for SEMAILBOX    */

#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
  bool privilegedSCRATCHPAD   : 1;  /**< Privileged access enabler for SCRATCHPAD   */
  bool privilegedEMU          : 1;  /**< Privileged access enabler for EMU          */
  bool privilegedCMU          : 1;  /**< Privileged access enabler for CMU          */
  bool privilegedHFXO0        : 1;  /**< Privileged access enabler for HFXO0        */
  bool privilegedHFRCO0       : 1;  /**< Privileged access enabler for HFRCO0       */
  bool privilegedFSRCO        : 1;  /**< Privileged access enabler for FSRCO        */
  bool privilegedDPLL0        : 1;  /**< Privileged access enabler for DPLL0        */
  bool privilegedLFXO         : 1;  /**< Privileged access enabler for LFXO         */
  bool privilegedLFRCO        : 1;  /**< Privileged access enabler for LFRCO        */
  bool privilegedULFRCO       : 1;  /**< Privileged access enabler for ULFRCO       */
  bool privilegedMSC          : 1;  /**< Privileged access enabler for MSC          */
  bool privilegedICACHE0      : 1;  /**< Privileged access enabler for ICACHE0      */
  bool privilegedPRS          : 1;  /**< Privileged access enabler for PRS0         */
  bool privilegedGPIO         : 1;  /**< Privileged access enabler for GPIO         */
  bool privilegedLDMA         : 1;  /**< Privileged access enabler for LDMA         */
  bool privilegedLDMAXBAR     : 1;  /**< Privileged access enabler for LDMAXBAR     */
  bool privilegedTIMER0       : 1;  /**< Privileged access enabler for TIMER0       */
  bool privilegedTIMER1       : 1;  /**< Privileged access enabler for TIMER1       */
  bool privilegedTIMER2       : 1;  /**< Privileged access enabler for TIMER2       */
  bool privilegedTIMER3       : 1;  /**< Privileged access enabler for TIMER3       */
  bool privilegedUSART0       : 1;  /**< Privileged access enabler for USART0       */
  bool privilegedUSART1       : 1;  /**< Privileged access enabler for USART1       */
  bool privilegedBURTC        : 1;  /**< Privileged access enabler for BURTC        */
  bool privilegedI2C1         : 1;  /**< Privileged access enabler for I2C1         */
  bool privilegedCHIPTESTCTRL : 1;  /**< Privileged access enabler for CHIPTESTCTRL */
  bool privilegedSYSCFGCFGNS  : 1;  /**< Privileged access enabler for SYSCFGCFGNS  */
  bool privilegedSYSCFG       : 1;  /**< Privileged access enabler for SYSCFG       */
  bool privilegedBURAM        : 1;  /**< Privileged access enabler for BURAM        */
  bool privilegedIFADCDEBUG   : 1;  /**< Privileged access enabler for IFADCDEBUG   */
  bool privilegedGPCRC        : 1;  /**< Privileged access enabler for GPCRC        */
  bool privilegedDCI          : 1;  /**< Privileged access enabler for DCI          */
  bool privilegedReserved0    : 1;  /**< Reserved privileged access enabler         */

  bool privilegedDCDC         : 1;  /**< Privileged access enabler for DCDC         */
  bool privilegedPDM          : 1;  /**< Privileged access enabler for PDM          */
  bool privilegedRFSENSE      : 1;  /**< Privileged access enabler for RFSENSE      */
  bool privilegedRADIOAES     : 1;  /**< Privileged access enabler for RADIOAES     */
  bool privilegedSMU          : 1;  /**< Privileged access enabler for SMU          */
  bool privilegedSMUCFGNS     : 1;  /**< Privileged access enabler for SMUCFGNS     */
  bool privilegedRTCC         : 1;  /**< Privileged access enabler for RTCC         */
  bool privilegedLETIMER0     : 1;  /**< Privileged access enabler for LETIMER0     */
  bool privilegedIADC0        : 1;  /**< Privileged access enabler for IADC0        */
  bool privilegedI2C0         : 1;  /**< Privileged access enabler for I2C0         */
  bool privilegedWDOG0        : 1;  /**< Privileged access enabler for WDOG0        */
  bool privilegedAMUXCP0      : 1;  /**< Privileged access enabler for AMUXCP0      */
  bool privilegedEUART0       : 1;  /**< Privileged access enabler for EUART0       */
  bool privilegedBUFC         : 1;  /**< Privileged access enabler for BUFC         */
  bool privilegedCRYPTOACC    : 1;  /**< Privileged access enabler for CRYPTOACC    */
  bool privilegedAHBRADIO     : 1;  /**< Privileged access enabler for AHBRADIO     */

#else
#error "No peripherals defined for SMU for this device configuration"
#endif
} SMU_PrivilegedAccess_TypeDef;

/*******************************************************************************
 ******************************   STRUCTS   ************************************
 ******************************************************************************/

/** SMU initialization structure. */
typedef struct {
  union {
    uint32_t reg[2];                      /**< Peripheral access control array.*/
    SMU_PrivilegedAccess_TypeDef access;  /**< Peripheral access control array.*/
  } ppu;
  bool enable;                            /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/
} SMU_Init_TypeDef;

/** Default SMU initialization structure settings. */
#define SMU_INIT_DEFAULT {                                        \
    { { 0 } },             /* No peripherals access protected. */ \
    true                   /* Enable SMU.*/                       \
}

/*******************************************************************************
 *****************************   PROTOTYPES   **********************************
 ******************************************************************************/

/***************************************************************************//**
 * @brief
 *   Enable or disable PPU of SMU.
 *
 * @param[in] enable
 *   Set to true to enable PPU; set to false otherwise.
 ******************************************************************************/
__STATIC_INLINE void SMU_EnablePPU(bool enable)
{
#if defined (_SMU_PPUCTRL_ENABLE_SHIFT)
  BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable);
#else
  (void)enable;
#endif
}

/***************************************************************************//**
 * @brief
 *   Initialize PPU of SMU.
 *
 * @param[in] init
 *   Pointer to initialization structure that defines which peripherals should
 *   only be accessed from privileged mode, and if PPU should be enabled.
 ******************************************************************************/
__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
{
  SMU->PPUPATD0 = init->ppu.reg[0];
  SMU->PPUPATD1 = init->ppu.reg[1];

  SMU_EnablePPU(init->enable);
}

/***************************************************************************//**
 * @brief
 *   Change access settings for a peripheral.
 *
 * @details
 *   Set to limit access of a peripheral from privileged mode.
 *
 * @param[in] peripheral
 *   ID of the peripheral to change access settings for.
 *
 * @param[in] privileged
 *   Set to true if the peripheral should only be accessed from privileged
 *   mode; set to false otherwise.
 ******************************************************************************/
__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,
                                             bool privileged)
{
  EFM_ASSERT(peripheral < smuPeripheralEnd);

  if (peripheral < 32) {
    BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged);
  } else {
    BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged);
  }
}

/***************************************************************************//**
 * @brief
 *   Get ID of the peripheral that caused an access fault.
 *
 * @note
 *   The return value is only valid if @ref SMU_IF_PPUPRIV interrupt flag
 *   is set.
 *
 * @return
 *   ID of the peripheral that caused an access fault.
 ******************************************************************************/
__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
{
  return (SMU_Peripheral_TypeDef)SMU->PPUFS;
}

/***************************************************************************//**
 * @brief
 *   Clear one or more pending SMU interrupts.
 *
 * @param[in] flags
 *   Bitwise logic OR of SMU interrupt sources to clear.
 ******************************************************************************/
__STATIC_INLINE void SMU_IntClear(uint32_t flags)
{
#if defined (SMU_HAS_SET_CLEAR)
  SMU->IF_CLR = flags;
#else
  SMU->IFC = flags;
#endif
}

/***************************************************************************//**
 * @brief
 *   Disable one or more SMU interrupts.
 *
 * @param[in] flags
 *   SMU interrupt sources to disable.
 ******************************************************************************/
__STATIC_INLINE void SMU_IntDisable(uint32_t flags)
{
#if defined (SMU_HAS_SET_CLEAR)
  SMU->IEN_CLR = flags;
#else
  SMU->IEN &= ~flags;
#endif
}

/***************************************************************************//**
 * @brief
 *   Enable one or more SMU interrupts.
 *
 * @note
 *   Depending on the use, a pending interrupt may already be set prior to
 *   enabling the interrupt. To ignore a pending interrupt, consider using
 *   SMU_IntClear() prior to enabling the interrupt.
 *
 * @param[in] flags
 *   SMU interrupt sources to enable.
 ******************************************************************************/
__STATIC_INLINE void SMU_IntEnable(uint32_t flags)
{
#if defined (SMU_HAS_SET_CLEAR)
  SMU->IEN_SET = flags;
#else
  SMU->IEN |= flags;
#endif
}

/***************************************************************************//**
 * @brief
 *   Get pending SMU interrupts.
 *
 * @return
 *   SMU interrupt sources pending.
 ******************************************************************************/
__STATIC_INLINE uint32_t SMU_IntGet(void)
{
  return SMU->IF;
}

/***************************************************************************//**
 * @brief
 *   Get enabled and pending SMU interrupt flags.
 *   Useful for handling more interrupt sources in the same interrupt handler.
 *
 * @note
 *   Interrupt flags are not cleared by this function.
 *
 * @return
 *   Pending and enabled SMU interrupt sources.
 *   The return value is the bitwise AND combination of
 *   - the OR combination of enabled interrupt sources in SMU_IEN register
 *     and
 *   - the OR combination of valid interrupt flags in SMU_IF register.
 ******************************************************************************/
__STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
{
  uint32_t tmp;

  // Store SMU->IEN in temporary variable to define explicit order
  // of volatile accesses.
  tmp = SMU->IEN;

  // Bitwise AND of pending and enabled interrupts.
  return SMU->IF & tmp;
}

/***************************************************************************//**
 * @brief
 *   Set one or more pending SMU interrupts from SW.
 *
 * @param[in] flags
 *   SMU interrupt sources to set to pending.
 ******************************************************************************/
__STATIC_INLINE void SMU_IntSet(uint32_t flags)
{
#if defined (SMU_HAS_SET_CLEAR)
  SMU->IF_SET = flags;
#else
  SMU->IFS = flags;
#endif
}

/** @} (end addtogroup SMU) */
/** @} (end addtogroup emlib) */

#ifdef __cplusplus
}
#endif

#endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
#endif // EM_SMU_H


text:
require 'spec_helper'

describe 'aide', type: 'class' do

  context 'default parameters on RedHat 7' do
    let (:facts) {{
      :osfamily               => 'RedHat',
      :operatingsystemrelease => '7',
    }}
    it {
      should contain_class('aide')
      should contain_package('aide').with({
        'ensure' => 'latest',
        'name'   => 'aide',
      })
     # DB file
     should contain_file('/var/lib/aide/aide.db').with_owner('root')
     should contain_file('/var/lib/aide/aide.db').with_group('root')
     should contain_file('/var/lib/aide/aide.db').with_mode('0600')
    }

    describe 'should allow package to be absent' do
      let(:params) {{ :version => 'absent', :package => ['aide'], }}
      it { should contain_package('aide').with_ensure('absent') }
    end

    describe 'should allow package name to be overridden' do
      let(:params) {{ :version => 'latest', :package => ['notaide'], }}
      it { should contain_package('notaide').with_ensure('latest') }
    end

  end

end

redpajama_set_name: RedPajamaGithub


text:
/***********************************************************************************************************************************
Server Test Harness
***********************************************************************************************************************************/
#include "build.auto.h"

#include <arpa/inet.h>
#include <netinet/in.h>
#include <string.h>
#include <sys/socket.h>
#include <unistd.h>

#include <openssl/conf.h>
#include <openssl/ssl.h>

#include "common/crypto/common.h"
#include "common/error.h"
#include "common/io/socket/server.h"
#include "common/io/tls/server.h"
#include "common/io/tls/session.h"
#include "common/log.h"
#include "common/type/buffer.h"
#include "common/type/json.h"
#include "common/wait.h"

#include "common/harnessDebug.h"
#include "common/harnessServer.h"
#include "common/harnessTest.h"

/***********************************************************************************************************************************
Command enum
***********************************************************************************************************************************/
typedef enum
{
    hrnServerCmdAbort,
    hrnServerCmdAccept,
    hrnServerCmdClose,
    hrnServerCmdDone,
    hrnServerCmdExpect,
    hrnServerCmdReply,
    hrnServerCmdSleep,
} HrnServerCmd;

/***********************************************************************************************************************************
Constants
***********************************************************************************************************************************/
#define HRN_SERVER_HOST                                             "tls.test.pgbackrest.org"

/**********************************************************************************************************************************/
void hrnServerInit(void)
{
    FUNCTION_HARNESS_VOID();

    // Set correct permissions on private keys
    THROW_ON_SYS_ERROR(
        chmod(strZ(strNewFmt("%s/" HRN_SERVER_CERT_PREFIX "server.key", hrnPathRepo())), 0600) == -1, FileModeError,
        "unable to set mode on server key");
    THROW_ON_SYS_ERROR(
        chmod(strZ(strNewFmt("%s/" HRN_SERVER_CERT_PREFIX "client.key", hrnPathRepo())), 0600) == -1, FileModeError,
        "unable to set mode on client key");

    // Add hostname when running in a container
    if (testContainer())
    {
        if (system("echo \"127.0.0.1 " HRN_SERVER_HOST "\" | sudo tee -a /etc/hosts > /dev/null") != 0)
            THROW(AssertError, "unable to add test host to /etc/hosts");
    }

    FUNCTION_HARNESS_RETURN_VOID();
}

/***********************************************************************************************************************************
Send commands to the server
***********************************************************************************************************************************/
static void
hrnServerScriptCommand(IoWrite *write, HrnServerCmd cmd, const Variant *data)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
        FUNCTION_HARNESS_PARAM(ENUM, cmd);
        FUNCTION_HARNESS_PARAM(VARIANT, data);
    FUNCTION_HARNESS_END();

    ASSERT(write != NULL);

    ioWriteStrLine(write, jsonFromUInt(cmd));
    ioWriteStrLine(write, jsonFromVar(data));
    ioWriteFlush(write);

    FUNCTION_HARNESS_RETURN_VOID();
}

/**********************************************************************************************************************************/
IoWrite *hrnServerScriptBegin(IoWrite *write)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
    FUNCTION_HARNESS_END();

    ASSERT(write != NULL);

    FUNCTION_HARNESS_RETURN(IO_WRITE, write);
}

void hrnServerScriptEnd(IoWrite *write)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
    FUNCTION_HARNESS_END();

    ASSERT(write != NULL);

    hrnServerScriptCommand(write, hrnServerCmdDone, NULL);

    FUNCTION_HARNESS_RETURN_VOID();
}

/**********************************************************************************************************************************/
void
hrnServerScriptAbort(IoWrite *write)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
    FUNCTION_HARNESS_END();

    hrnServerScriptCommand(write, hrnServerCmdAbort, NULL);

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptAccept(IoWrite *write)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
    FUNCTION_HARNESS_END();

    hrnServerScriptCommand(write, hrnServerCmdAccept, NULL);

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptClose(IoWrite *write)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
    FUNCTION_HARNESS_END();

    hrnServerScriptCommand(write, hrnServerCmdClose, NULL);

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptExpect(IoWrite *write, const String *data)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
        FUNCTION_HARNESS_PARAM(STRING, data);
    FUNCTION_HARNESS_END();

    ASSERT(data != NULL);

    hrnServerScriptCommand(write, hrnServerCmdExpect, VARSTR(data));

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptExpectZ(IoWrite *write, const char *data)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
        FUNCTION_HARNESS_PARAM(STRINGZ, data);
    FUNCTION_HARNESS_END();

    ASSERT(data != NULL);

    hrnServerScriptCommand(write, hrnServerCmdExpect, VARSTRZ(data));

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptReply(IoWrite *write, const String *data)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
        FUNCTION_HARNESS_PARAM(STRING, data);
    FUNCTION_HARNESS_END();

    ASSERT(data != NULL);

    hrnServerScriptCommand(write, hrnServerCmdReply, VARSTR(data));

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptReplyZ(IoWrite *write, const char *data)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
        FUNCTION_HARNESS_PARAM(STRINGZ, data);
    FUNCTION_HARNESS_END();

    ASSERT(data != NULL);

    hrnServerScriptCommand(write, hrnServerCmdReply, VARSTRZ(data));

    FUNCTION_HARNESS_RETURN_VOID();
}

void
hrnServerScriptSleep(IoWrite *write, TimeMSec sleepMs)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_WRITE, write);
        FUNCTION_HARNESS_PARAM(TIME_MSEC, sleepMs);
    FUNCTION_HARNESS_END();

    ASSERT(sleepMs > 0);

    hrnServerScriptCommand(write, hrnServerCmdSleep, VARUINT64(sleepMs));

    FUNCTION_HARNESS_RETURN_VOID();
}

/**********************************************************************************************************************************/
void hrnServerRun(IoRead *read, HrnServerProtocol protocol, HrnServerRunParam param)
{
    FUNCTION_HARNESS_BEGIN();
        FUNCTION_HARNESS_PARAM(IO_READ, read);
        FUNCTION_HARNESS_PARAM(ENUM, protocol);
        FUNCTION_HARNESS_PARAM(UINT, param.port);
        FUNCTION_HARNESS_PARAM(STRING, param.certificate);
        FUNCTION_HARNESS_PARAM(STRING, param.key);
    FUNCTION_HARNESS_END();

    ASSERT(read != NULL);

    // Set port to index 0 if not specified
    if (param.port == 0)
        param.port = hrnServerPort(0);

    // Initialize ssl and create a context
    IoServer *tlsServer = NULL;

    if (protocol == hrnServerProtocolTls)
    {
        ASSERT((param.certificate != NULL && param.key != NULL) || (param.certificate == NULL && param.key == NULL));

        // If certificate and key are not set then use defaults
        if (param.certificate == NULL)
        {
            param.certificate = strNewFmt("%s/" HRN_SERVER_CERT_PREFIX "server.crt", hrnPathRepo());
            param.key = strNewFmt("%s/" HRN_SERVER_CERT_PREFIX "server.key", hrnPathRepo());
        }

        tlsServer = tlsServerNew(STRDEF(HRN_SERVER_HOST), param.ca, param.key, param.certificate, 5000);
    }

    IoServer *socketServer = sckServerNew(STRDEF("localhost"), param.port, 5000);

    // Loop until no more commands
    IoSession *serverSession = NULL;
    bool done = false;

    do
    {
        HrnServerCmd cmd = jsonToUInt(ioReadLine(read));
        const Variant *data = jsonToVar(ioReadLine(read));

        switch (cmd)
        {
            case hrnServerCmdAbort:
            {
                // Only makes since to abort in TLS, otherwise it is just a close
                ASSERT(protocol == hrnServerProtocolTls);

                ioSessionFree(serverSession);
                serverSession = NULL;

                break;
            }

            case hrnServerCmdAccept:
            {
                serverSession = ioServerAccept(socketServer, NULL);

                // Start TLS if requested
                if (protocol == hrnServerProtocolTls)
                    serverSession = ioServerAccept(tlsServer, serverSession);

                break;
            }

            case hrnServerCmdClose:
            {
                if (serverSession == NULL)
                    THROW(AssertError, "session is already closed");

                ioSessionClose(serverSession);
                ioSessionFree(serverSession);
                serverSession = NULL;

                break;
            }

            case hrnServerCmdDone:
                done = true;
                break;

            case hrnServerCmdExpect:
            {
                const String *expected = varStr(data);

                // Read as much as possible
                Buffer *buffer = bufNew(strSize(expected));

                TRY_BEGIN()
                {
                    ioRead(ioSessionIoRead(serverSession), buffer);
                }
                CATCH(FileReadError)
                {
                    // If nothing was read then throw the original error
                    if (bufEmpty(buffer))
                        THROW_FMT(AssertError, "server expected '%s' but got EOF", strZ(expected));
                }
                TRY_END();

                // Treat any ? characters as wildcards so variable elements (e.g. auth hashes) can be ignored
                String *actual = strNewBuf(buffer);

                for (unsigned int actualIdx = 0; actualIdx < strSize(actual); actualIdx++)
                {
                    if (strZ(expected)[actualIdx] == '?')
                        ((char *)strZ(actual))[actualIdx] = '?';
                }

                // Error if actual does not match expected
                if (!strEq(actual, expected))
                    THROW_FMT(AssertError, "server expected '%s' but got '%s'", strZ(expected), strZ(actual));

                break;
            }

            case hrnServerCmdReply:
                ioWrite(ioSessionIoWrite(serverSession), BUFSTR(varStr(data)));
                ioWriteFlush(ioSessionIoWrite(serverSession));
                break;

            case hrnServerCmdSleep:
                sleepMSec(varUInt64Force(data));
                break;
        }
    }
    while (!done);

    // Free servers
    ioServerFree(tlsServer);
    ioServerFree(socketServer);

    FUNCTION_HARNESS_RETURN_VOID();
}

/**********************************************************************************************************************************/
const String *hrnServerHost(void)
{
    return strNewZ(testContainer() ? HRN_SERVER_HOST : "127.0.0.1");
}

/**********************************************************************************************************************************/
unsigned int hrnServerPort(unsigned int portIdx)
{
    ASSERT(portIdx < HRN_SERVER_PORT_MAX);

    return 44443 + (HRN_SERVER_PORT_MAX * testIdx()) + portIdx;
}


text:
layout: post
title: "Toyo Time!"
excerpt: "My companion large format camera."
tags: [toyo, photography, large format, class]
date: 2015-09-01
ogimage: "20150901-btozier-toyo-time.jpg"
---

{% include _figures.html
  base_image_filename="20150901-btozier-toyo-time.jpg"
  title="Toyo Time!"
  alt="A large format camera fills the image"
  caption="Toyo Field 45AII"
%}

This (Toyo Field Camera WCC #9) is going to be my companion for a little while. I'm comfortable with handling it and setting it up, but it will take a little while before I get past those "D'OH!" points, like forgetting to take the dark slide out before pressing the shutter release.

Our first assignment is to make a portrait. We practiced on our fellow students---my partner was a new-to-me fellow named Neal. He was pretty photogenic, lucky for me, too bad he got me in return. However, since he's really new to photography, I paid for my lack of photo poise with knowledge about how to set up lights.

A fair trade!

Now begins the wait... ... ... we're not going to be developing this film for two weeks!

So far, I've discovered that large format is even *more* meditative than working with medium format cameras. I suppose with practice I could get very quick at setting it up, but focusing, setting the aperture and shutter speed, and loading the film all require a certain amount of attention *and* intention.

![](/images/adhoc/2015-09-01-simply.jpg "Sean Bean as Boromir saying 'One does not simply make snapshots with large format'")
{: .image-adhoc}

Thank you, Mr Bean. You explained that quite well.


text:
<?php

### Check Whether User Can Manage Database
if(!current_user_can('manage_database')) {
	die('Access Denied');
}

### Variables Variables Variables
$base_name = plugin_basename('wp-dbmanager/database-manager.php');
$base_page = 'admin.php?page='.$base_name;

### Form Processing
if($_POST['do']) {
	// Lets Prepare The Variables
	$optimize = $_POST['optimize'];

	// Decide What To Do
	switch($_POST['do']) {
		case __('Optimize', 'wp-dbmanager'):
			check_admin_referer('wp-dbmanager_optimize');
			if(!empty($optimize)) {
				foreach($optimize as $key => $value) {
					if($value == 'yes') {
						$tables_string .=  '`, `'.$key;
					}
				}
			} else {
				$text = ''.__('No Tables Selected', 'wp-dbmanager').'';
			}
			$selected_tables = substr($tables_string, 3);
			$selected_tables .= '`';
			if(!empty($selected_tables)) {
				$optimize2 = $wpdb->query("OPTIMIZE TABLE $selected_tables");
				if(!$optimize2) {
					$text = ''.sprintf(__('Table(s) \'%s\' NOT Optimized', 'wp-dbmanager'), str_replace('`', '', $selected_tables)).'';
				} else {
					$text = ''.sprintf(__('Table(s) \'%s\' Optimized', 'wp-dbmanager'), str_replace('`', '', $selected_tables)).'';
				}
			}
			break;
	}
}

### Show Tables
$tables = $wpdb->get_col("SHOW TABLES");
?>
<?php if(!empty($text)) { echo '

'.$text.'

'; } ?>

<form method="post" action="<?php echo admin_url('admin.php?page='.plugin_basename(__FILE__)); ?>">
	<?php wp_nonce_field('wp-dbmanager_optimize'); ?>

<?php _e('Optimize Database', 'wp-dbmanager'); ?>

					<?php _e('Tables', 'wp-dbmanager'); ?>
					<?php _e('Options', 'wp-dbmanager'); ?>

				<?php
					foreach($tables as $table_name) {
						if($no%2 == 0) {
							$style = '';
						} else {
							$style = ' class="alternate"';
						}
						$no++;
						echo "
$table_name	\n";
						echo "<input type=\"radio\" id=\"$table_name-no\" name=\"optimize[$table_name]\" value=\"no\" /> ".__('No', 'wp-dbmanager')."     <input type=\"radio\" id=\"$table_name-yes\" name=\"optimize[$table_name]\" value=\"yes\" checked=\"checked\" /> ".__('Yes', 'wp-dbmanager').'
';
					}
				?>

				<?php _e('Database should be optimize once every month.', 'wp-dbmanager'); ?>

				<input type="submit" name="do" value="<?php _e('Optimize', 'wp-dbmanager'); ?>" class="button" />  <input type="button" name="cancel" value="<?php _e('Cancel', 'wp-dbmanager'); ?>" class="button" onclick="javascript:history.go(-1)" />

</form>