He holds a joint appointment in the Laboratory for Analysis and Architecture of Systems, a CNRS research unit. Dr Piat obtained his Phd thesis in electronic and signal processing from the INSA of Rennes in 2010. His work dealt with loop partitioning for dataflow models to target multi-core architectures with signal processing applications. He is now working on the integration of robotics algorithms on FPGA-based dedicated hardware. His main research interests include dataflow-models, hardware/software co-design, embedded vision processing and robotics.