Mr. Swan helped create a number of new EDA tools at Cadence and has worked directly with SoC designers at large customers around the world to help them adopt new tools and methodologies. In the area of SoC modeling standards, he helped lead development of System-C and authored a book, served in the OSCI/Accellera board of directors, and was technical working group chairman for the IEEE SystemC LRM development. He has also been active in the development and standardization of the SystemVerilog OVM and UVM verification methodologies. Stuart graduated from Stanford University with a BSEE with honors.