He received a Ph.D. in Embedded Systems from National University of Singapore in 2014. Prior to his Ph.D., he was a research engineer for more than 7 years at ST Microelectronics (India and Grenoble) and LSI Corporation (India). Following his Ph.D., he was a post-doctoral fellow at the University of Southampton from 2014 to 2015 and a researcher at IMEC from 2015 to 2017. His research focuses on neuromorphic computing, from algorithm development to architectural exploration. His other research interests include System-level design techniques for lifetime and energy optimization, Soft-error tolerance of FPGA configuration bitstream, Synchronous data flow graph based task mapping and scheduling, Probabilistic energy and performance optimization of multiprocessor systems, architectural adaptations for lifetime improvement of multiprocessor, and Design-for-testability (DFT) of multi-power domain SoC.