Her research interests are in the areas of formal and semi-formal design verification, with emphasis on full design validation, and digital system reliability. Valeria joined the faculty at Michigan after being in the Advanced Technology Group of Synopsys for four years as a lead developer of Vera and Magellan, two popular verification tools. In 2005, she authored a book on symbolic simulation. Valeria serves in several conference program committees, including DATE, DAC and ICCAD, and she is an Associated Editor for the IEEE Transactions on CAD. In addition, she has been leading the effort for the development of the verification section in the International Technology Roadmap for Semiconductors report since 2004. She received her M.S. and a Ph.D. degree in Electrical Engineering from Stanford University in 1998 and 2003, respectively.