of the substrate 1 is uncovered inside the opening 3 see fig2 the opening 3 defines a region for an mos transistor subsequently a first layer 4 a second layer 5 and a third layer 6 are produced in the opening 3 such that the opening 3 is essentially filled up see fig3 the first layer 4 is deposited undoped to a thickness of for example 300 nm the second layer is deposited for example p doped to a thickness of for example 20 nm the doping occurs for example by adding boron in a concentration of at least 10 19 cm 3 the third layer 6 is deposited n doped it has a thickness of approximately 100 nm subsequently a gate dielectric 7 is grown or deposited on the surface of the third layer 6 see fig4 the gate dielectric 7 is composed for example of sio 2 or of a nitride sio 2 compound a gate electrode 8 is produced above the gate dielectric 7 this occurs for example by surface wide deposition of a polysilicon layer that is doped via ion implantation or occupation an oxide layer is deposited on the polysilicon layer using a cvd process this double layer composed of the polysilicon layer and of the oxide layer is phototechnically structured the gate electrode 8 and a first oxide layer 9 are thereby produced as a result of the common structuring the first oxide layer 9 and the gate electrode 8 have common sidewalls perpendicular to the surface of the substrate 1 subsequently a second oxide layer is deposited in conformity the second oxide layer is anisotropically etched using a dry etching so that sidewall insulations 10 of sio 2 are produced at both.