resistive bit structure is provided by encapsulation of the gmr stack by means of a ta crsi barrier both the tops and the side walls of the gmr bits are protected by passivation in the manner described above the side walls of the gmr bits are not exposed either during permalloy via etch or thereafter therefore oxygen asher photoresist removal and conventional wet chemical strips can be used without damage to the passivated gmr bits an alternative embodiment of the present invention will now be illustrated by reference to fig1 to 15 referring to fig1 an underlayer 40 which may be a monolithic integrated circuit serves as a substrate for a gmr stack 42 underlayer 40 preferably includes a dielectric layer separating the gmr stack from an integrated circuit the dielectric layer may be for example a 500 u00e5 seed sin layer not shown a crsi barrier layer 44 is deposited on top of gmr stack 42 a sin ion mill mask 46 is fabricated in a known manner on top of crsi layer 44 for example a relatively thick sin layer can be deposited upon crsi layer 44 and patterned using a photoresist and reactive ion etch layer 44 may for example be an 800 u00e5 thick crsi layer crsi is preferred because in addition to being a good oxygen barrier and etch stop crsi has a bulk resistivity low enough to allow sense line contact and high enough to minimize shunting ion mill mask 46 may be a 2000 u00e5 sin layer other suitable dielectric materials such as sio 2.