input terminals 22 and 12 and no signals are applied to the terminals 13 and 29 in a corresponding manner an output signal r w cyc req will be produced at the output terminal of the or gate 31 if a busy ii signal is applied to the input terminal 13 simultaneously with an r w req ii signal to terminal 29 and no signals are applied to the terminals 12 and 22 the arbitration operation comes into effect if busy i and busy ii signals are applied substantially contemporaneously to the input terminals 12 and 13 the nature of the latch 14 is such that if the busy i signal obtains preference an output signal based on the busy i will be produced at the q terminal of the flip flop 17 and applied to enable the and gate 21 to transmit the r w req i signal therethrough at the same time the q output signal of the flip flop 17 goes low and disables the nand gate 24 preventing the delayed busy ii signal from passing through that nand gate to the setting terminal of the flip flop 26 on the other hand if the busy ii signal applied to the input terminal 13 obtains preference it will disable the nand gate 16 by driving the output of the inverter 19 low just to be sure that the latch 14 has had time to respond to a busy i signal if such a signal has just preceded the busy ii signal the busy ii signal is required to pass through the delay element 23 to delay it by approximately 50 ns before being applied to the nand gate 24 if the latch 14 has not been actuated in response to a.