to obtain cavities 520 620 and 420 surmounting the diffused source region 52 drain region 62 and gate region 42 it is noted here that the dimension of the cavities is greater than the aperture of the orifice this selective removal may be carried out by any known means for example by means of an oxidizing chemical agent such as a solution comprising 40 ml of 70 hno 3 20 ml of h 2 o 2 5 ml of 0 5 hf or by isotropic plasma etching next one or more electrically conducting materials are deposited by known methods allowing the previously obtained cavities to be simultaneously filled fig1 in order to obtain the source region 52 the drain region 62 and the gate region 42 these regions being surmounted by electrically conducting zones for example metallizations 53 63 and 43 and connection vias 91 which are also electrically conducting between these metallizations and the surface of the integrated circuit since the aperture of the cavities is greater than that of the orifices the areas of the metallizations 43 53 63 are greater than the vias aperture this permits a decrease in the contact resistance without increasing the lateral dimensions of the vias which permits one to maintain the integration density of the interconnections in this regard the cavities 420 520 620 and the etching orifices 90 may be filled with tungsten w for example by chemical vapor deposition cvd known per se for example within the 500 u00b0 c to 600 u00b0 c temperature range or else by ald atomic layer deposition also known per se for example within the 200 u00b0 c to 300 u00b0 c temperature range it is also possible to use copper cu cobalt.