begins with a p type substrate 102 as shown in fig7 a stis 126 can be formed in substrate 102 using a conventional cmos sti loop as can be seen in fig7 b mask 702 enables formation of stis 126 additionally as part of the sti loop a polish stop nitride layer 704 typically silicon nitride is provided following the formation of stis 126 the body 104 can be formed turning to fig7 c mask 706 is used to form the dnwell 118 preferably an n type material such as phosphorous or arsenic is implanted into substrate 102 the body 104 is then formed in the region above the dnwell 118 as shown in fig7 d by implantation of a p type material such as boron using mask 708 as shown in fig7 f and 7g the electrode regions 106 and 108 and barrier region 114 are formed through a self aligning technique turning first to fig7 e the insulating layer 142 and gate electrode 110 are formed over at least a portion of the channel not shown and a p type material boron for example and as shown are implanted into the barrier region additionally the angle of the arrows indicating the path of the ions is for illustrative purposes and is not necessarily accurate once the barrier region 114 is formed insulating sidewalls or layers 142 and 144 are formed and a n type material such as phosphorous or arsenic is implanted to form the electrode regions 106 and 108 as can be seen in fig7 f prior to the formation of the electrode regions 106 and 108 and the barrier region 114 mask 716 is.