fl v fr is less sensitive to variations in the interconnect when compared to variation in local etch and finger height however the same is not true for the beam self test outputs interconnect capacitance mismatch does indeed cause self test outputs to exceed the noise floor however in a majority of the cases considered the output magnitude does not rival that produced by the other defects this implies that variations of up to 5 in the interconnect capacitance are unlikely to falsely indicate asymmetry in the micromechanical structure of the accelerometer only a beam bridge defect that is located close to its anchor point will produce a beam self test output difference that is not significantly larger than that produced by interconnect mismatch because simulation alone is not sufficient for validating the differential bist approach disclosed here a prototype was designed and fabricated in which a subset of the bist features was added to the accelerometer design of wu et al u201c a low noise low offset chopper stabilized capacitive readout amplifier for cmos mems accelerometers u201d supra the bist implementation was limited to finger self test for the purpose of validation the layout of the prototype design is shown in fig8 the technology used is a three metal one poly 06 u03bcm cmos process the control circuitry for bist is illustrated in fig9 the two phases of the modulation voltage signal are v mp and v mn the digital self test input pin si is driven to a logic zero during normal operation for si 0 the capacitive network reduces to the one shown in fig5 a self test is activated when si 1 for this case.