as illustrated in fig2 b this time delayed sequence for sampling streams is readily generated in system clock 14 shown in fig1 by a basic clock reference running at the range sampling frequency of 500 mhz further the basic system impulse repetition frequency prf o is formed by simple digital divide by two circuits applied to the system clock frequency to generate the velocity filter corresponding to a velocity v 1 as represented by fig2 b requires that variable time delay 19 provide a sequence of delays u03b4td 1 2 u03b4td 1 n 1 u03b4td 1 consecutively to the start of each range sampling stream the time separation between the start of each range sampling stream is pri o where u03b4td 1 follows from equation 1 and therefore variable time delay 19 may be a programmable multiple tapped analog delay line capable of producing the required sequence of delays the programming for which is inputted by a total motion compensation delay control issued from velocity control computer 15 a commercially available active programmable delay line may be adapted in one or more units in series for this purpose the sampling sequence as depicted by fig2 b is inputted to analog to digital converter adc j 20 where j is the filter index j o to m which issues digitized inputs to memory locations for all consecutive range bins in the desired.