the first mentioned memory circuit 5 1 input terminals 22 2 22 3 22 n correspond to that shown at 22 1 silicon controlled rectifier elements 6 2 6 3 6 n are same with that shown at 6 1 resistors 7 2 7 3 7 n and 8 2 8 3 8 n correspond to those 7 1 and 8 1 respectively condensers 9 2 9 3 9 n and 12 2 12 3 12 n correspond to those denoted 9 1 and 12 1 respectively semiconductor diodes 10 2 10 3 10 n and 11 2 11 3 11 n correspond to those denoted 10 1 and 11 1 respectively the respective yarn defects signals delivered from the sensors 4 1 4 2 4 3 4 n are shown in fig1 at 1b 2b 3b nb representatively and by way of example these yarn defects signals 1b 2b 3b nb are conveyed through scanning contacts 14a 1 14a 2 14a 3 14a n of scanners 14 15 to a first information processor 19 shown only schematically by a block as its successive inputs on the other hand the memoried signals in the temporary memories 5 1 5 2 5 3 5 n as being shown representatively and only by way of example at 3c and nc in fig1 are taken out and conveyed through respective scanning contacts 14b 1 14b 2 14b 3.