of the feedback loop the digital loop filter 314 is preferably programmable to selectively attenuate noise components for example if the adc is known to generate a noise spur at 500 khz the digital loop filter 314 can be designed to have a gain of zero or substantially zero at 500 khz thus preventing the 500 khz spur from appearing at the output of the synthesizer given the flexibility with which digital filters can be designed particularly fir finite impulse response filters frequency u201c zeroes u201d can be added to the transfer function of the digital loop filter 314 as needed for an arbitrary number of noise frequencies from any source preferably the transfer function of the digital loop filter 314 is field programmable to accommodate particular noise characteristics of any target application the synthesizer 300 is preferably implemented on a circuit board assembly that includes a combination of digital and analog components in the preferred embodiment the digital phase detector 312 digital loop filter 314 and sigma delta modulator 316 are provided together in a single digital component such as an fpga field programmable gate array or an asic application specific integrated circuit this is not required however alternatively they can be provided separately or in the form of discrete logic some components can be provided in separate fpgas asics or discrete logic and others can be provided together the digital phase.