data source the second generator and the first and second dividers produce a phase slip rate signal to select the appropriate one of the first and second division factors for the first divider and to select the appropriate one of the third and fourth division factors for the second divider application_number US 70280376 A description referring to fig1 the pll arrangement shown combines the low frequency slip rate s with the high reference frequency f r generated by reference crystal oscillator 1 and pulse generator 2 to produce the output rate f o generated by the voltage controlled oscillator 3 and pulse generator 4 the output frequency f o is varied by varying the slip rate s the reference frequency is divided by a j or k counter 5 and the output frequency f o is divided by an l or m counter 6 the output of counters 5 and 6 have their phase compared in phase comparator 7 which may be in the form of an exclusive or gate or the comparator of fig9 described hereinbelow the phase error signal from comparator 7 is coupled through a loop low pass filter 8 to voltage controlled oscillator 3 to appropriately lock the output frequency f o a requirement for the division integers j k l and m is that the difference jm kl is small typically equal to 1 when there is no phase slipping counters 5 and 6 divide by j and l respectively so that f 0 l j f r during a phase slip counters 5 and 6 divide by k and m respectively so that f 0 39 m k.