gate structure 16 in this preferred embodiment the floating gate 16 extends completely across the thin oxide layer 12 and overlaps the thick oxide regions 14 on both sides of the active area an oxide layer 18 is formed covering the floating gate 16 on its upper surface and along all edges to totally electrically isolate the gate 16 a second layer of polycrystalline silicon is then deposited over the substrate and patterned to form a control gate 20 the second layer is patterned to preferably completely cover the floating gate 16 and to have the same width as gate 16 in the active area defined by thin oxide 12 as shown in fig1 this control gate 20 may extend beyond the floating gate 16 in the thick or field oxide region 14 and typically continues across the integrated circuit to form the control gate of a plurality of other memory cells either after patterning of the floating gate 16 or the preferably self aligned control gate 20 those portions of the active region not covered by the gates are doped with an n type impurity to provide source and drain regions on opposite sides of the floating gate the formation of self aligned gate structures including the stacked gate arrangement is known in the art as illustrated by the above referenced u s pat no 4 142 926 openings may be made in the thin oxide 12 on opposite.