field mode interference elimination circuit 115 includes a summation circuit 205 having a high impedance positive input 205 a electrically connected to the voltage s across the secondary winding 105 b and a high impedance negative input 205 b electrically connected to the voltage r across the mode detect winding 110 if an external magnetic field is applied to the planar transformer arrangement 100 a common mode interference voltage will be superimposed on both the voltage s across the secondary winding 105 b and the voltage r across the mode detect winding 110 however since the interference voltage appears across both windings 105 b 110 the summation circuit 205 operates to cancel the interference voltage effects of the externally applied magnetic field thereby generating the output signal 125 free of common mode interference referring now to fig3 a through 3 c there is seen top bottom and cross sectional views respectively of the exemplary planar transformer 105 and exemplary mode detect winding 110 shown in fig1 as shown in fig3 a through 3 c the windings 105 a 105 b 110 of the exemplary planar transformer arrangement 100 may be implemented for example as meandering traces on a planar medium 300 e g a printed circuit board or an integrated circuit which forms an open magnetic path between the primary and secondary windings 105 a 105 b of the planar transformer 105 referring now to fig5 there is seen a second exemplary planar transformer arrangement 500 according to the present invention the planar transformer arrangement 500 includes primary circuitry 505 a arranged on one side of a planar medium.