period t step 2 comprising said pulse output signals are generated by dividing the oscillating frequency output signal by frequency divider one or more said frequency dividers could be used if a plurality of said frequency dividers are used they are serially connected and the following frequency divider divides the output signal from the preceding frequency divider then the outputs of the plurality of frequency dividers are combined by a logic circuit to generate several pulse output signals wherein said step 2 can also be implemented by a counter generating one or more pulse output signals wherein step 3 comprising when oscillating output signal is the first level the each second capacitor is superimposed and pulse signal controls the discharging of corresponding second capacitor to generate the ramp voltage when the ramp voltage reaches the discharge reference voltage the frequency jitter output signal changes to the first level comparing to the oscillating frequency output signal said first level is delayed a period of time which is determined by the quantity and capacity of the discharge capacitors when oscillating frequency output signal is the second level the each second capacitor is superimposed and pulse output signal controls the charging of corresponding second capacitor to generate the ramp voltage when the ramp voltage reaches the charge reference voltage the frequency jitter output signal.