with the prior art which has been processed to create a plurality of individual circuits 12 1 12 2 12 3 12 n therein where n is an integer typically although not necessarily the circuits 12 1 12 n are fabricated in the wafer 10 by the well known planer technology process the planer technology process is practiced by first obtaining individual wafers 10 from an ingot not shown of substantially pure semiconductor material thereafter at least one layer not shown of a different type of semiconductor material is epitaxially grown on the upper surface of each wafer 10 the uppermost epitaxially grown layer on each wafer 10 is passivated and then etched following etching interconnections between the passivated regions exposed after etching are established to create the circuits 12 1 12 n on each wafer 10 in practice those wafers 10 which are to yield a particular type or code of circuits 12 1 12 n are processed in a batch of approximately fifty wafers each wafer 10 in the batch is subjected to the same set of process operations as the others while the wafers 10 in a given batch are subjected to the same processing operations the original order of the wafers in the batch is usually not maintained between processing steps for example the first wafer in the batch during etching may not be first in the batch during passivation referring to fig2 after fabrication of the circuits 12 1 12 n in each wafer 10 each wafer in the batch is typically probed by two or more probes 14 which are displaced to.