in a range of for example from approximately 20 nm to approximately 50 nm the layers 25 can be sio 2 by means of a conventional wet oxidation process or a sion silicon oxynitride referring now to fig5 a thick polysilicon layer 30 is deposited with a conventional low pressure chemical vapor deposition lpcvd process to fill the trenches an operation step preferably performed in a furnace a cvd process allows conformal deposition of the polysilicon material 30 to cause the polysilicon material to be void free referring to fig6 a cmp operation is performed to result in planarized surfaces 40 to remove the polysilicon from all areas except in the patterned windows and the trenches and stopping at the sin layer 15 the planarization process preferably a conventional chemical mechanical polishing cmp is used to provide the planar surfaces other known techniques can be used with similar results referring now to fig7 a fresh pad nitride layer 45 is deposited the pad nitride layer 45 thickness can be for example in a range of approximately 50 nm to approximately 100 nm and adjusted to match the total nitride thickness of for example approximately 80 nm to approximately 100 nm still referring to fig7 a gate last cmos device integration process individually conventional steps can now be used to fabricate fet transistors not shown and need not be further discussed gate last is also often referred to as a replacement metal gate process see for example u s pat no 7 776 757 and.