the diviser is selected to be 6 the fundamental frequency turns out to be 1773 96 hz for an error of 8 3 while this error can be reduced by increasing the master clock signal such an increase will place constraints on the method of manufacture and yield of the frequency synthesizer 330 however this error may be reduced in accordance with the invention by utilizing an intermediate frequency which is an integral submultiple of the stepping frequency and also an integral submultiple of the master clock frequency for example an intermediate frequency of 1 4 the stepping frequency or four times the fundamental output tone frequency has been selected for frequency synthesizer 330 for the highest tone of the high group the intermediate frequency is therefore 4 u00d7 1638 6552 hz dividing the master clock frequency by the intermediate frequency produces a required diviser of m 25 99 for zero error rounding this off to m 26 produces negligible error in the actual dtmf output tone fundamental frequency however the intermediate frequency is now derived by sequencing the programmable counter 350 through 26 different sequential count states because the intermediate frequency is only 1 4 of the stepping frequency these 26 count states must be further subdivided to provide 4 pulses on signal step increment h for each cycle of the 26 count states since the 26 count states are not integrally divisible by the number 4 the stepping pulses on signal step.