fgt transistor may also be a floating potential instead of ground if a short circuit exists between the gate and the source of the access transistor the gate of the access transistor is found at the same electrical potential as the source of the floating gate transistor v s which is compatible with the application of a floating potential on line atl i fig7 illustrates an embodiment of a rdec 2 decoder according to the invention wherein the signal v at is delivered by the source s of a mos transistor the drain d of which is connected to the output out i of the rdec decoder the mos transistor is driven by the signal erase and its drain delivers a control signal v at which is floating when the signal erase is set to 0 although the application of a zero voltage or of a floating potential on the gates of the access transistors during the erasing phases was suggested above it is obvious that the signal v at might be set to another value if the voltage v s applied on the source of the floating gate transistors was different from 0 for example some erasing methods involve a negative source voltage in this case a negative voltage would be applied on the gate of the access transistors during the erasing phases an alternative to the decoder described above includes providing during the programming phases the application of voltage vcc instead of voltage vpp on the gates of the cgt k transistors in order to.