oscillator circuit 22 for a longer period of time this extends the period of the major clock by adding the delay line of the programmable delay line 52 57 each time that the programmable divider circuit 40 overflows the taps on the delay line 52 57 are programmable with each tap representing one half to two nanoseconds in this way the period of the major clock output signal from the programmable divider 40 on the signal line 44 is incremented in very small increments fig4 a and 4b show contiguous logical circuit diagrams of a clock rate timer system 100 for comparing the frequency of an input clock signal dram clk or scsi clk obtained from the tuned ring oscillator circuit 20 with the frequency of a reference pulse index edge the logic circuits are formed from standard cells and building blocks provided from the at amp t 1 25 micron cmos library the dram clk operates typically at frequencies in the range of 10 24 mhz and is provided at an input terminal 102 the scsi clk typically operates at 20 mhz and is provided at an input terminal 104 the index edge is provided at an input terminal 106 and is derived from the edge of the spindle index pulse for a.