acceptable address word adr1 and in full line an examination process when the receiving location is fed with the acceptable address word adr2 in addition thereto fig4 shows the logic values written into the individual result register locations of the examination result register er in each of these two examination operations when the address word adr1 is received the decoder dec while being fed at its decoder inputs de1 and de2 with the segment bit pattern 34 00 34 of address word segment a issues the logic value 34 1 34 at its decoder output da0 when during examination of segment a the and elements and0 to and3 have the filter register locations of filter register fra connected thereto a logical 34 1 34 appears at the output of and0 and a logical 34 1 34 via or element or is written into the result register location of result register er belonging to segment a during decoding of address word segment b the filter register locations of frb are coupled to and0 to and3 and a logical 34 1 34 is generated due to the presence of a logical 34 1 34 at the decoder output da2 and in the filter register location of frb that is coupled to and2 and is written into the result register location of examination result register er corresponding to segment b the examination and assessment of the remaining segments c through f takes place in the same manner the manner in which the filter registers fra and belonging to the individual.