as that of the conventional adder however power benefits are obtained through configuration of accuracy in the approximate mode the error correction stage is power gated with foot and or head switches 410 and power reduction over the conventional adder design can be achieved the switches 410 are controlled by a mode signal 409 the foot head switches are placed between the voltage ground supply and a given block of functional circuitry the block 39 s leakage is stopped when the switch cuts off the current path from supply to ground to achieve higher performance or lower power consumption we can reduce the carry chain depth k of sub adders however when k is less than n 4 it is impossible to correct all errors and achieve 100 correct results within one clock cycle since the error correction paths become critical to achieve correct results in the pipelined implementation the error correction stage should be extended to multiple stages fig5 illustrates such a pipelined adder implementation k n 8 case in which four pipeline stages are required to achieve a 100 accurate result in the pipelined adder each stage 501 502 503 504 is structured as in fig4 and generates a result with different accuracy the output accuracy increases as the number of pipeline stages increases the output of.