consumption thereof can be suppressed as described above the supply of the clock signal to the upper bit section can be reduced as a result the number of times of the operations of the flip flops provided in the upper bit section can be decreased if the number of times of the operations of the flip flops is decreased the power consumption can be suppressed also since the circuit elements such as the flip flops in the counter circuit are not operated the generation of noise is possibly reduced in addition the mask circuit sections shown in fig3 may be provided to be plural in the counter circuit in this case when the outputs of flip flops from a first stage to a stage just before the relevant stage become u201c 1 u201d each of these mask circuit sections validates a clock signal to be supplied to the relevant flip flop the counter circuit explained in the first embodiment is a 3 bit counter circuit of the flip flops f 0 to f 2 however the number of times of operations of the flip flops to a full count increases as the number of bits increases in this case a circuit configuration may be employed in accordance with a second embodiment of the present invention next the counter circuit according to the second embodiment of the present invention will be described below it is supposed that the counter circuit is a 6 bit counter circuit.