block from memory and places its own write in the write queue 301 through the read path multiplexor 305 and processor data bus where it is processed in the normal manner as all write requests if the write queue is not available then the scrub controller ignores the detection and continues it normal activity referring now to fig4 a there is shown a state diagram 400 for typical memory scrub process according to the prior art memory scrub is a process of systematically reading every location of a dram over a period of time for the purpose of detecting accumulated storage errors if a correctable error is detected by the error correction code ecc circuits in the memory controller the corrected data is written back to the dram through the ecc circuits to reestablish the data in memory without errors since dram soft errors accumulate slowly the scrub process needs to complete a sweep of the dram over several tens of hours therefore the scrub process operates in the idle state at step 401 until some infrequent periodic event for example some quantity of dram refreshes are detected at steps 402 and 403 at such detection the scrub process initiates a scrub read to the next block of memory once out of the wait loop defined at steps 401 402 403 a scrub event commences by first reinitializing the wait counter u201c wait_cnt u201d 404 to pace out the period to the next scrub then a block of data say 256 bytes is read from memory at the scrub address contained within a counter and checked through the ecc.