data information in the subframe 28 consists of seven channels a b g the seven channels are assigned with channel numbers and are arranged in the order of the channel numbers in the subframe 28 following the first or leading channel assigned to a particular one or the third one of the time slots in the subframe 28 after the overhead 27 as shown in the figure accordingly the pointer p in the overhead 27 indicates three 3 referring to fig3 the frame aligner 30 shown therein according to an embodiment of the present invention comprises a buffer memory 11 a writing circuit 12 an input clock generator 13 an input frame synchronous signal generator 14 a read circuit 15 an output clock generator 16 and an output frame synchronous signal generator 17 similar to the known frame aligner 10 in fig1 but the frame aligner 30 further comprises a demultiplexer 31 for separating the input frame signal into the overhead portion and the subframe portion as a separated overhead portion and a separated subframe portion respectively a multiplexer 32 for multiplexing a subframe signal read from the buffer memory 11 and a fresh overhead signal to produce the output frame signal and a pointer arithmetic circuit 33 for preparing the fresh overhead signal the demultiplexer 31 receives the input frame signal 23 fig4 the input clock 22 fig4 and the input frame synchronous signal 21 fig4 and separates the overhead portion 27 from the subframe portion 28 of the frame signal to deliver the separated overhead portion and the separated subframe portion to the pointer arithmetic circuit 33 and the buffer memory 11 respectively the demultiplexer 31 also produces a write unable signal to the writing circuit 12 when the.