previous embodiment a single multilayer circuitized laminate structure 50 a is provided which as in the previous embodiment aligns with the capture pads 44 a 44 b and is secured to the dielectric sheet 34 a as previously described however in this embodiment the chips 22 a and 22 b can be connected through circuitry 42 a on the dielectric sheet 34 a as well as through the circuitry 56 a alternatively individual multilayer circuit laminate structures not shown could be provided for each of the chips 22 a and 22 b while still allowing the chips to be connected through circuitry 42 a in another embodiment of the invention shown in fig7 a dielectric sheet 80 is provided which covers all of the individual chips 82 formed on a wafer 84 and is laminated to the wafer again this is a low modulus dielectric material such as ptfe or polyimide this dielectric sheet is drilled just as previously described to form vias 86 and circuitry 88 with capture pads 90 however the amount of circuitry 88 that can be provided on the wafer is limited because of the proximity of the chips of course adjacent chips 82 that are to act as a unit such as particularly memory chips can be connected by the circuitry 88 and diced as a unit this is merely the first step and when the chips are diced and separated.