the input voltages of this differential amplifier 12 are also the voltage vr likewise the output voltage of the second stage differential amplifier 12 is also a voltage produced by amplifying an offset voltage similarly to the first stage of the differential amplifier 11 the third stage is the same since the amplification stages are capacitively coupled in this manner and each stage is input with the reference voltage vr the first stage offset voltage is not transmitted to the latter stages hence the offset voltage of the entire amplification circuit becomes the offset voltage of the final stage i e the final amplifier 13 therefore with a three stage constitution such as the one in this example the offset voltage calculated upon input can be considered as a fraction of the gain of the previous two stages and hence can be reduced in magnitude considerably next a voltage comparison operation will be described during the period of this operation the switches s 2 s 4 annexed with the symbol u03c6 2 in fig1 are on and the other switches s 1 s 3 s 5 s 6 s 7 s 8 s 9 s 10 are off at this timing in the successive approximation ad converter shown in fig2 the switch s 1 is off and the switch s 2 is on the inputs of each differential stage the differential amplifiers 11 12 and the final amplifier 13 are removed from the reference voltage vr since the switches s 15 through s 20 are off as a result the differential amplifiers 11 12 and the final amplifier 13 perform amplification in accordance with the variation in the.