the first line layer 71 in the dram of the third embodiment having the configuration fabricated by the above fabrication method when a laser beam blows the fuse element 9 in the dram shown in fig5 a hole is formed in the fuse element 9 the diameter of the hole is approximately equal to the hole formed conventionally accordingly it is possible to increase the integration of the semiconductor integrated circuit namely the dram having the configuration shown in fig5 because it is not required to increase the interval between adjacent fuse elements furthermore because it is not required to blow the fuse element 9 in depth the blowing time of the laser beam to the fuse element 9 can be reduced as described above because the semiconductor integrated circuit of the third embodiment has the configuration in which the surface of the insulating layer 14 formed on the semiconductor substrate 1 and the capacitor made up of the electrodes 2 and 4 and the insulating layer 3 is approximately smoothed by using the chemical mechanical polishing process and because the fuse element 9 is formed over the insulating layer 14 in a laminating direction it is possible to increase the integration of the semiconductor integrated circuit without any influence caused by holes generated by an off focus of the laser beam and a laser blowing process accordingly it is possible to form both the memory cell sections 16 and the logical section 17 in the same semiconductor chip without preventing a high integration of the logical section 17 shown in fig2 this provides a semiconductor memory of high integration including a mixed logic section without any influence caused by holes generated by.