appear at all four inputs to gate 32 which then causes latch circuit 34 to set the delay timing is selected to be long enough to allow latch circuit 34 to set before such time out at the expiration of this delay period delay circuit 15 applies a logic level 0 signal to gate 32 which causes a logic level 1 signal to appear at the s1 input of latch circuit 34 however this signal has no impact since latch circuit 34 had previously been set in the event that clock c had also failed the clock selection circuit would not enable clock c but would enable the next properly operating clock circuit in the clock selection sequence if one copy of the clock selection control circuit is powered down and then up it may go into an unstable state and cause a new clock circuit to be selected even though a failure did not occur in the previously selected clock circuit if the new clock circuit is not fully operational alarms and degradation of service can result this problem is eliminated through use of first and second inhibit leads inhibit a and inhibit b respectively and or gates 18 28 37 and 47 if copy 0 is to be powered down processing unit b.