upon the practice of the exemplary embodiments of this invention fig1 a shows a si substrate 10 having an overlying oxide layer 12 e g 3 u03bcm and overlying si and sti regions 14 a 14 b a conventional hfo 2 tin deposition may provide gate stack layers 16 and 18 respectively the hfo 2 layer 16 may be considered as the high k layer e g k in a range of about 20 25 as compared to 3 9 for sio 2 and may have a thickness in a range of about 1 3 nm the tin layer 18 may be considered as the metal or metal like layer and may have a thickness of about 10 nm layers 16 and 18 together form the as yet unpatterned mhk gate stack this initial structure may represent a standard soi or without box bulk cmos with a mhk gate stack note that the exemplary embodiments of this invention are not limited for use with hfo 2 as the high k material and other metal oxide based materials may be used as well such as a uniform or a composite layer comprised of one or more of ta 2 o 5 tio 2 al 2 o 3 y 2 o 3 and la 2 o 5 materials other than tin that may be used for the metal containing layer 18 include but need not be limited to one or more of ta tan tacn tasin tasi aln w and mo fig1 b shows the deposition of an amorphous si or a poly si layer 20 which may have a thickness in.