if the data were off chip furthermore wide internal busses are more feasible inside a memory chip than across chip boundaries because of size and electrical characteristic considerations in a preferred approach the present invention has two modes 34 smart 34 and 34 standard 34 in the 34 smart 34 mode the processor core is enabled to process data in the data memory 18 if instructed to begin processing in the 34 standard 34 mode the processing core is prevented from processing the default operating mode is the 34 standard 34 mode in the 34 standard 34 mode thedevice operates as a memory device as shown in fig5 a the host processor38 of the system dynamically switches the operating mode by writing to a mode pin of the smart memory 10 the mode pin may comprise a no care pin on a typical memory device such as pin 11 in fig1 a by using a mode pin the operating mode of the device is guaranteed and software bugs cannot inadvertently switch the mode in another alternative the mode pin could be used as an extra address pin thus when addressed in one particular range the smart memory would function in the standard mode when addressed in another range it would function in the smart mode in another embodiment the mode of a smart memory device could be switched without the use of a mode pin with this.