cells arranged in 32 memory cell blocks each memory cell block in memory cell array 135 contains 64 kilobytes of floating gate transistor memory cells data stored in each memory cell block is erased independently as described below without disturbing data stored in other memory cell blocks a command execution logic module 140 receives the above described interface signals from controller 105 command execution logic module 140 controls internal state machine 130 which provides write and block erase timing sequences to memory cell array 135 through x interface circuit 145 and y interface circuit 150 y interface circuit 150 provides access to individual memory cells through data lines in memory cell array 135 y interface circuit 150 includes a y decoder circuit y select gates sense amplifiers and write erase bit compare and verify circuits x interface circuit 145 provides access to rows of memory cells through wordlines in memory cell array 135 which are electrically coupled to control gates also called select gates of floating gate transistors in memory cell array 135 x interface circuit 145 includes decoding and control circuits for erasing individual blocks of memory cells in memory cell array 135 fig2 shows a state diagram of a prior art state machine for controlling an erase operation in a flash memory a similar state machine is described in u s pat no 5 619 453 the disclosure of which is hereby incorporated by reference for its description of the state diagram therein the operation includes a plurality of interconnected execution cycles including incremental cycles and other cycles the execution cycles of the erase operation are arranged in a plurality of interconnected groups including a pre program group 210.