is fed to the clock pulse terminal c p the terminals j and k are 34 1 0 34 as shown in fig7 d by 30g so that the terminals q and q hold the condition 34 1 0 34 as shown in fig7 e by 31g the above mentioned output waveform shown in fig7 e changes from high level to low level at the trailing end of an initial waveform 32 where the amplitude of the input signal shown in fig7 a starts to increase that is at the point 31c in fig7 e and also changes from low level to high level at the trailing end of an initial waveform where the amplitude of the input signal starts to be restored that is at the point 31f in fig7 e accordingly as compared with the prior art level detecting circuit which produces time lags shown by t 1 and t 2 in fig6 b due to the time constant of the circuit the level detecting circuit used in this invention can greatly shorten its time lags because it produces the output waveform as shown in fig7 e further since the aforesaid output waveform shown in fig7 e is used only to detect whether the amplitude of the input signal shown in fig6 a or fig7 a is larger or smaller than the working level of the level detector if a transistor or the like is previously set by.