execution 401 see fig4 the data flow check logic 43 see fig2 compares the ids of instructions writing results into the result field 31 to the locker ids of all shelved instructions when the locker ids match the updating ids those lockers are removed 602 when both lockers of an instruction are removed that instruction becomes ready to execute 401 to allow the unshelving of an instruction and sending it to execution at the same time that a new instruction enters the dynamic register file 11 which is not locked and which can also proceed to execution multiple execution units such as arithmetic logic units alu 45 47 and the associated multiplexers 49 51 53 and 55 are provided the dynamic register file 11 also has a first out port illustrated at 39 in fig2 and at the fifo output ports 114 125 in fig9 a results are moved from the fifo output 114 125 collectively first out port 39 of the dynamic register file 11 into the register file 17 the dynamic register file 11 has the data flow in ports 151 in fig2 and 106 108 91 and 85 in fig9 a and 9b and the data flow out ports 145 147 and 149 in fig9 a and 9b the data flow out ports 145 147 149 are used to issue instructions and their operands to execution in a data flow manner as illustrated in fig4 and 6 and the data flow in ports 151 106 108 91 and 85 are used to write results of those instructions back into the dynamic register file 11 the results and.