metal lines since the source line of any sector is now individually selected by the transistor ms table 1______________________________________ program erase programming inhibit read______________________________________sl fl 0 0 vref1bl fl 0 9 iloadrow 5 0 10 18 10 18 vref2row 0 4 6 7 0 9 9 vref3ssl fl 0 0 vref4bsl fl 9 9 vref4other bls fl vinhibit vinhibit fl e g 9v e g 9v p substrate 20 0 0 0conditions for erasing cells 0 through 7and for programming and reading cell 5 ofan eight nand cell string______________________________________ in the present invention the nand memory cell configuration is used in an analog storage device in spite of the unpredictable resistances to be encountered in the nand connected cells during playback this is achieved by reading a cell by a two step or multi step read wherein a high read current is first used to obtain a quickly settling though inaccurate readout voltage followed by a very low substantially zero readout current to allow the readout voltage to resettle at a more accurate readout voltage because of the now negligible voltage drops across the other resistances in the nand connection because of the very low current as an alternative a similar effect can be obtained by discharging the hold capacitor ch before each read by momentarily shorting the capacitor to ground through an n channel device then when a read operation is initiated the read current will be initially relatively high.