same dimension may have different total wire lengths thus we can further optimize total wire length by using a top down approach while keeping a placement dimension the same or even smaller based on the example mentioned above fig7 a shows the result of rearranging one of the placements of the root node while keeping dimensions the same then at least one placement can be chosen with the smallest wire length the similar step can be performed for each of the constraints from the top to the bottom of the hierarchy tree fig7 b 7d show some placements for wire length optimization as a result at least one placement with a smallest wire length can be selected from the placements to optimize the wire length for each of the nodes in the hierarchy tree by using the top down process it is to be noted that during the top down process for wire length optimization the u201c current best u201d placement for the root note is always used for calculating the differences caused by various placements within the current node after the placement with smallest total wire length is chosen for the current node the u201c current best u201d placement for the root node is updated accordingly then the process moves on to the next node in the hierarchy and the optimization process continues fig8 illustrates an original layout and its extracted constraint tree an ic design comprising device modules m 1 m 2 m 3 m 4.