bus connected into a ring shape the positional relation among the processor modules becomes indefinite and hence allocation of processing amounts to the respective processor modules becomes difficult in terms of the performance it is preferable to uniformly allocate the processing amount to the respective processor modules but this may produce an overflow in the queue memory according to the present invention an amount of data stored in the queue memory is monitored at all times and data input from the external circuit is temporarily forbidden when the monitored data amount exceeds an upper limit preset with respect to the capacity of the queue memory thus restraining the generation of data in the previous processor module as a result the remaining processor modules can be controlled to operate at a speed which is suitable for the processor module having the largest processing amount and the lowest processing speed among all of the connected modules in other words the present invention is able to provide a processor system which can perform control of the multistage connection hereinafter one embodiment of the processor system will be described by referring to fig6 the system according to this embodiment includes therein a counter for counting an amount of data stored in the queue memory a comparator for judging whether or not a value of the counter exceeds an upper limit that is a value of capacity of the queue memory the number of latches constituting the pipe line and a control circuit adapted to forbid input from the external circuit in accordance with the output from the comparator fig6 shows a block diagram of one module this module includes therein a bus interface bi 641 a transfer table memory tt 642 a parameter.