node 29 equals v we i r fb the second differential amplifier da 2 comprises an operational amplifier a 4 with its non inverting input 40 connected to the first terminal of the fifth impedance load 32 and the first terminal of the sixth impedance load 36 the second terminal of the fifth impedance load 32 is connected to node 34 that forms the non inverting input of the operational amplifier oa 1 the second terminal of the sixth impedance load 36 is connected to the system ground 38 the inverting input 44 of the operational amplifier a 4 is connected to the first terminal of the seventh impedance load 30 and the first terminal of the eighth impedance load 42 the second terminal of the seventh impedance load 30 is connected to node 29 that forms the output of the operational amplifier oa 1 the second terminal of the eighth impedance load 42 connects to the output of the operational amplifier a 4 it is preferable to provide all impedance loads equal in value and obtain an output voltage at the operational amplifier a 4 equal to i r fb the implementation of da 1 and da 2 are not limited to the example embodiment shown in fig6 both differential amplifiers da 1 and da 2 are required to provide an output equal to the difference of their inputs with unity gain the differential amplifier da 1 is required to draw minimal current from the reference electrode re and the differential amplifier da 2 is required to provide sufficient output current for the subsequent stage to simplify the design da 1 consists of da 2 with additional.