electrode portions 204 and 224 may comprise polysilicon and silicides the gate dielectric layers 202 and 222 may be formed of silicon oxide silicon oxy nitride silicon nitride nitrogen doped silicon oxide high k dielectrics or combinations thereof the high k dielectrics may include metal oxides metal silicates metal nitrides transition metal oxides transition metal silicates metal aluminates and transition metal nitrides or combinations thereof the gate dielectric layers 202 and 222 may be formed by any process known in the art e g thermal oxidation nitridation sputter deposition or chemical vapor deposition the physical thickness of the gate dielectric layers 202 and 222 may be in the range of 5 to 100 angstroms the gate electrode portions 204 and 224 may be formed of doped polysilicon polysilicon germanium metals metal silicides metal nitrides or conductive metal oxides in a preferred embodiment the gate electrodes are formed of doped polysilicon spacers 206 and 226 which may be formed of composite oxide nitride materials are formed along either side of the nmos and pmos gate sidewalls by depositing one or more layers of silicon oxide silicon nitride and or silicon oxy nitride followed by wet or dry etching away portions of the one or more layers it will be appreciated that the spacers may include first forming an offset liner not shown e g oxide adjacent the gate structure to space a subsequently formed ldd doped region away from the gate structure in addition ion implanted source and drain s d.