to go high and switch u2018 on u2019 the nmos transistors 94 96 in the first and second output stages 90 110 when the nmos transistors 94 96 in the first output stage 90 switch u2018 on u2019 current in the first output stage 90 flows from high 98 through the capacitor 100 and nmos transistors 94 96 to ground 102 this flow of current effectively charges the capacitor 100 and discharges the first node represented in fig6 as node_ 1 105 when the first node 105 goes low the schmitt trigger 104 outputs low to the inverter 106 which in turn outputs high to the gate terminal of the pmos transistor 112 in the second output stage 110 in this case the high at the gate terminal of the pmos transistor 112 causes the pmos transistor 112 to switch u2018 off u2019 and thus current in the second output stage 110 flows from high 98 through the capacitor 100 and nmos transistors 94 96 to ground 102 this flow of current in the second output stage 110 effectively charges the capacitor 100 in the second output stage 110 and discharges the second node represented in fig6 as node_ 2 107 when the second node 107 goes low the schmitt trigger 104 outputs low to the inverter 106 which in turn outputs high on the clock detect signal output signal represented in fig6 as clk_det_ 2 this high on the clock detect output signal is indicative of the input signal being present still referring to fig6 at a point b.