each supplied by the output of individual nand gates the rs flip flops are constructed in the known way by cross coupling inputs and outputs of a pair of nor gates the q and q outputs of the flip flop 211 are shown in fig4 as q 211 and q 211 respectively the output of the flip flop 212 is shown as q 212 in the present embodiment two latch elements 221 and 222 are provided which are connected to each other and to the counter 210 the inputs of the latch 221 are connected to corresponding outputs of the counter 210 and the output of the counter is latched or stored in the latch 221 with the rising edge of a clock signal q 211 which is applied to the input l of the latch 221 this stored value is then made available at the outputs of the latch 221 beginning with the negative going edge of the clock signal the inputs of the latch 222 are connected to the output of the latch 221 and operates in corresponding fashion to store the signal presented to its inputs at the time of the positive going signal applied to the input terminal l in this way the output of the counter 210 representing the state of the counter is stored successively in the latches 221 and 222 which together manifest the state of the counter 210 at the two preceding clock pulses applied to the terminals l the outputs of the two latch.