single step channel erase however this also requires the added complexity of building the memory array inside a triple well a channel erase condition may also be realized by applying an additional voltage pulse of higher negative value to the gate wordlines while the source is biased at the same potential as the substrate ground after the regular erase pulse this procedure is illustrated in fig6 as can be seen a positive pulse of about 5v is applied between source and substrate for a period of about 10 ms at the same time the gate substrate voltage is taken to negative 10v at the end of the 10 ms period when the source substrate voltage is reduced to zero the voltage between the gate and substrate is increased to negative 15 volts and held at that potential for an additional 5 ms while this approach can be implemented on a flash memory without a triple well surrounding the array it has the disadvantage of requiring extra erase time and the supply of a higher negative voltage a more convenient approach illustrated in fig7 a is to discharge the source toward the substrate potential or other area of common voltage at the end of the regular erase pulse while the negative voltage to the control gate wordlines.