application_number US 64164803 A description referring now specifically to a prior art method of forming copper plugs overlying a layer of copper which is shown in cross section in fig1 the cross section of fig1 shows 10 a semiconductor surface typically the surface of a semiconductor silicon substrate 12 a first layer of dielectric deposited over the surface of layer 10 14 a second layer of dielectric deposited over the surface of the first etch stop layer esl 12 of dielectric 16 first copper plugs formed in the first layer 12 of dielectric 18 second copper plugs formed in the second layer 14 of dielectric copper plugs 18 align with copper plugs 16 20 a first etch stop layer esl created over the surface of the first layer 12 of dielectric and 22 a second etch stop layer esl created over the surface of the second layer 14 of dielectric the methods and procedures that are used to create the interconnect arrangement that is shown in cross section in fig1 are well known in the art this and the observation that these methods are not germane to the invention obviate a need for further explanation of these methods and procedures at this time referring now specifically to the cross section that is shown in fig2 there is shown 10 a semiconductor surface typically the surface of a semiconductor silicon substrate 12 a first layer of dielectric deposited over the surface of layer 10 14 a second layer of dielectric deposited over the surface of the first etch stop layer esl 24 16 first copper plugs formed in the first layer 12 of dielectric 20 a first etch stop layer esl created over the surface of the first adhesion promotion layer 24 18 second copper plugs formed in.