a series of real and imaginary channel response chip values associated with a td cdma time slot are illustrated the channel response values are divided into a real portion crr and an imaginary portion cri the real channel response crr is processed by the circuit 100 while the imaginary channel response cri is processed in tandem by the circuit 200 in fig2 a register r r is preferably a 16 location register which receives the real portion of the channel response crr each location ci i 0 to 15 of register r r has f bits per location where f is a selected data bit size preferably 10 the number of locations corresponds with the preferred channel code size which is currently specified as 16 in 3gpp and is preferably a power of 2 in number the real component circuit 100 includes a plurality of components a 1 a 14 each adder component has an adder having two inputs and a single output which is the sum of the two inputs adder components a 1 a 8 are preferably configured as illustrated in fig4 adder components a 9 a 14 are preferably simple adders adder components a 1 a 2 a 3 a 4 receive input from the odd locations of register r r and perform either addition or subtraction on their pair.