of the nanowire 110 and on the soi pad regions 106 and 108 a second gate dielectric layer high k layer 504 such as for example hafnium oxide hfo 2 is formed around the first gate dielectric layer 502 a metal layer 506 such as for example tantalum nitride tan is formed on the second gate dielectric layer 504 the metal layer 506 is surrounded by polysilicon layer 404 of fig3 doping the polysilicon layer 404 with impurities such as boron p type or phosphorus n type makes the polysilicon layer 404 conductive the metal layer 506 is removed by an etching process such as for example rie from the nanowire 110 and the soi pad regions 106 and 108 that are outside of the channel region and results in the gate 402 fig4 b illustrates a cross sectional view of a portion of the nanowire 110 along the line b b of fig3 fig5 illustrates the spacer portions 604 formed along opposing sides of the polysilicon layer 404 the spacers are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by rie the spacer walls 604 are formed around portions of the nanowire 110 that extend from the polysilicon layer 404.