the memory address of each memory request operate to select a pair of words from two of the memory blocks the circuits include a binary decoder circuit 10 40 and a plurality of nand gates 10 41 through 10 44 which connect to the 00 through 11 decode outputs as shown each of the nand gates 10 41 through 1 44 generate a different one of the row address strobe signals dras0 through dras3 which are applied to the 256k dram chips of a corresponding one of the word blocks within the stack of each of the signals dras0 through dras3 are logically anded with a memory row address timing signal memras from timing circuits 10 10 and applied to the row address strobe ras input terminals of the 256k dram chips the least significant bit address signals addlsb and addlsb 1 are decoded as follows ______________________________________address values block selectedaddlsb 1 addlsb by row strobe______________________________________0 0 0 amp 10 1 1 amp 21 0 2 amp 31 1 3 only ______________________________________ additionally the memory stack 10 2 receives early column timing and late column timing signals from a selector circuit 10 6 in response to least significant address bit signal addlsb that is when bit signal addlsb is a binary zero the 34 0 34 inputs are selected to be applied as outputs when signal addlsb is a binary one the 34 1 34 inputs are selected as outputs the early column and late column timing signals are applied to the column address strobe cas input terminals of the 256k dram.