0 to 13 of the 3 bit adder 10 to generate a control signal 9 u2032 which has a width of 3 bits and has a range of values of from 0 to 6 i e the values of the control signal 9 u2032 are restricted to modulo 7 values to this end the means 11 comprises three half adders 14 2 14 4 an and gate 16 and an or gate 17 three d type flip flops 18 1 18 3 are used to delay the control signal 9 u2032 by one clock cycle precisely one d type flip flop 18 i being assigned to each bit line of the control signal 9 u2032 a 1 of n decoder 19 which is driven by the control signal 9 u2032 and generates the control signal 9 that directly controls the switching elements of the switching network 7 u2032 is provided at the output of the control apparatus 8 u2032 the control signal 9 which is output by the 1 of n decoder is a signal having a width of n 7 bits precisely one single bit of the total of 7 bits having a logic 1 as a function of the first control signal table 1 indicates the assignment between the values of the control signal 9 u2032 and the values of the control signal 9 fig7 shows a circuit diagram of an inventive dem block 4 u2033 as part of an inventive sd adc the dem block 4 u2033 comprising the inventive control apparatus 8 u2032 as shown in fig6.