pin p 0 3 of the control chip u 1 a data input pin di of the storage chip u 2 is connected to the input output pin p 0 2 of the control chip u 1 and connected to a first terminal of the capacitor c 6 via the resistor r 5 the first terminal of the capacitor c 6 is connected to the collector of the transistor q 1 a second terminal of the capacitor c 6 is grounded a clock pin sclk of the storage chip u 2 is connected to the input output pin p 0 0 of the control chip u 1 and connected to the first terminal of the capacitor c 6 via the resistor r 4 a data output pin do of the storage chip u 2 is connected to the input output pin p 0 1 of the control chip u 1 and connected to the first terminal of the capacitor c 6 via the resistor r 3 ground pins vss of the storage chip u 2 are grounded a voltage pin vdd of the storage chip u 2 is connected to the first terminal of the capacitor c 6 and the collector of the transistor q the base of the transistor q is connected to the input output pin p 1.