of transistor 73 and thus with the conductive element 80 and the drain well 76 with which conductive link 84 communicates known fabrication processes may be used to form the various features of transistors 72 and 73 as well as the underlying insulative layer 71 overlying insulative layer 90 and contact elements 85 88 an electrical schematic representation of a voltage shunting element 70 of the type shown in fig8 is provided in fig9 0045 fig1 depicts a combined block diagram enlarged schematic representation of another insert 18 of fig2 illustrating esd structure 40 as comprising a fusible element 44 fusible element 44 is configured to electrically connect to contact pad 31 through conductive element 32 a similarly fusible element 44 is configured to electrically connect to the contact member 22 through conductive element 32 b 0046 fig1 is a top plan layout of fusible element 44 of fig1 as implemented on a silicon substrate 12 not shown fusible element 44 may be implemented using metal a metal alloy polysilicon or other conducting material and may be fabricated by know processes fusible element 44 is shaped so as to fuse during an esd event if fusible element 44 fuses or is u201c blown u201d during an esd event the fused or u201c blown u201d fusible element 44.