character taken from its memory 5 this character is received in register 4 of the slave microprocessor 2 as well as moreover in all the registers 4 of all the other slave microprocessors not shown let us suppose that it is indeed microprocessor 2 for which this character is intended and that processing is taking place there at the time of reception of this character when the interruption mechanism 7 is initialized any processing in progress is interrupted for processing the character received in register 4 the initialization for enabling signal is received on line 11 connecting mechanism 7 to mechanism 9 and it is combined at the input of mechanism 7 with the 34 register 4 full 34 signal received over line 12 connecting mechanism 7 to register 4 since it is functionally an and gate mechanism 7 when the two signals are present at its inputs 11 and 12 empties register 8 of the address then present for substituting a new one which will cause reading of register 4 and reception of the character contained therein in memory 5 through bus 10 according to the invention the enabling signal is transmitted at the end of the processing in progress at the time of reception of the character until that time the character received in register 4 was masked by interrupt mechanism 7 then the above described procedure takes place and register 4 unloads an echo character for transmission purposes in series form over bus 3 and for reception in parallel form in register 4 of the master microprocessor 1 before being recognized in the recognition device 6 between reception in register 4 of the slave microprocessor 2 of the character transmitted by the master microprocessor 1 and recognition by device 6 of the master microprocessor 1 of the.