on a single chip the method includes covering a gate dielectric layer with a sacrificial layer of silicon nitride using a masks for defining line structures in the layer of silicon nitride for the bit line implant processes depositing a dielectric material among the line structures to fill gaps among the line structures planarizing the deposited oxide and said layer of silicon nitride removing the silicon nitride and applying a layer of polysilicon material patterning wordlines in the array portion and transistor gate structures in said non array portion and applying ldd silicide and other logic circuit processes application_number US 39749703 A description a detailed description of embodiments of the present invention is provided with reference to the figures in which fig1 a and 1b illustrate a basic flow for the manufacturing process the structures at various steps in the manufacturing process are shown in fig2 10 for mask rom based embedded memory devices fig1 illustrates application of the process to sonos based embedded memory devices a first step in the manufacturing process is to form isolation structures that define an array portion 110 and a non array portion 111 of the substrate block 10 fig2 provides a view of a resulting structure in the example shown in fig2 the array portion 110 is isolated from the non array portion by dielectric region 112 the dielectric region 112 is formed by depositing oxide or other dielectric within a trench by locos oxidation or otherwise as known in the.