0 and supplying wl 0 vcw 3 6 v will be described in this case the controller 18 outputs slct u201c h u201d hvxpb 0 0 0 v xpb 0 u201c l u201d hvxpb n 1 vcw 3 6 v and xpb n 1 u201c h u201d to each circuit note that n is a positive integer and hvxpb n 0 and xpb n 0 correspond to n 1 lines of word lines wl next an operation of the level shift circuit 30 will be described the level shift circuit 30 operates as a level shift circuit which shifts the signal from vcc 3 0 v to vcw 3 6 v based on hvx u201c l u201d and hvxb u201c h u201d accordingly the level shift circuit 30 shifts slct u201c h u201d vcc to lv_slct vcw 3 6 v and outputs the shifted signal to the level shift circuit 22 at the rear stage thereof the same description of the other operations as those of the first exemplary embodiment will be omitted in fig8 the voltage states at the portions are shown when a word line is selected in the high voltage operation in fig9 the voltage states at the portions are shown when no word line is selected in the high voltage operation the row decoder 14 according to the second exemplary embodiment includes the level shift circuit 22 that shifts the voltage range so that the voltage applied to the electrodes of the pmos transistor p 30 and the like of the word line selection circuit 24 is in the range from 0 0 v to vcc in the normal operation and is not in the range from 0 0 v to vpp but in the range from vcc to vpp in the high voltage operation.