p pillar structure of the jfet region according to another aspect of the present invention in general the method comprises providing a bulk p u2212 silicon layer 300 producing a buried nwell layer 301 making a p u2212 layer 320 in layer 301 and growing an n u2212 epitaxial layer p u2212 epitaxial layer is an option 302 on layer 301 fig1 a etching spaced parallel trenches 304 in layer 2 301 and 302 the width of the trenches 304 being equal or less than the width of the regions 306 between trenches 304 the width of the trenches 304 being equal or larger than the width of the regions 306 between trenches 304 for p epitaxial option fig1 b filling trenches 304 by segment epitaxial refill with p material 308 n material corresponding to p u2212 epitaxial as an option fig1 c resulting in alternating n pillars 310 and p pillars 312 fig1 d a top layer 322 of p type is then produced segment epitaxial refill is carried out by intrinsic epitaxial refill and in situ doped epitaxial refill or different level in situ doped epitaxial refills the in situ doped epitaxial layer with needed doping concentration is provided for p n pillars charge balance the intrinsic epitaxial layer with un doped material is provided for process adjustment and also to support some doped layer lateral diffusion for higher breakdown voltage trenches 304 can also be filled with oxide si refill in which a trench side wall thermal oxide layer has a si refill the sidewall oxide is used to prevent lateral diffusion between p pillars and n pillars in the device fabrication in this case there is an electric field through the trench side wall oxide by.