regions is minimized etching the region between the source drain to form a gate area and growing a prescribed gate insulation thickness for a metal gate whereby the gate insulation overlap of the diffused region and the thickness of the gate insulation overlap of the diffused region reduce the parasitic capacitance and increase the switching speed of the resulting metal gate transistor relative to prior art transistors application_number US 76980177 A description the prior art devices will be described in conjunction with fig1 a through 1e and fig2 fig1 a shows a beginning step in the process of fabricating an insulated metal gate transistor a semiconductor substrate 1 typically silicon is covered by an insulating layer 2 of silicon dioxide the oxide is formed by a dry wet dry process step 20 conducted at a temperature of 1000 u00b0 c to achieve a thickness of 540nm openings 3 are formed in the oxide by well known photolithographic etching processes in an operation 22 to form source and drain areas fig1 b shows the device after the diffusion of source drain regions 7 and the regrowth of the oxide layer 5 beneath the original layer 2 and the regrowth layer 6 over the diffusion openings the phosphorus deposition is made.