making a decision that the phase of the frequency multiplied clock signal disagrees with that of the divide by 2 clock signal supplies the counter 22 with the up signal or down signal to update the counter value at step st4 receiving the up signal from the phase comparator 21 the counter 22 increments the counter value by one whereas receiving the down signal it decrements the counter value by one then the decoder 23 decodes the upper seven bits of the counter value and outputs the 96 bit control signal to cause the phase of the frequency multiplied clock signal to coarsely approach that of the divide by 2 clock signal on the other hand the decoder 24 decodes the lower three bit of the counter value and outputs the 8 bit control signal to reduce the phase difference to a least possible value thus in response to the 8 bit control signal output from the decoder 24 the digital delay line 26 finely delays the frequency multiplied clock signal at step st5 as shown in fig5 the digital delay line 26 consists of eight delay elements that provide slightly different delay times and are connected in parallel and hence can achieve fine adjustment of the delay time on the other hand in response to the 96.