illustrated embodiment the controller 7 may be implemented as a single special purpose integrated circuit e g asic having a main or central processor section for overall system level control and separate sections dedicated to performing various different specific computations functions and other processes under control of the central processor section those skilled in the art will appreciate that the controller can also be implemented using a plurality of separate dedicated or programmable integrated or other electronic circuits or devices e g hardwired electronic or logic circuits such as discrete element circuits or programmable logic devices such as plds plas pals or the like the controller can also be implemented using a suitably programmed general purpose computer e g a microprocessor microcontroller or other processor device cpu or mpu either alone or in conjunction with one or more peripheral e g integrated circuit data and signal processing devices in general any device or assembly of devices on which a finite state machine capable of implementing the flowcharts shown in fig7 11 13 and 15 can be used as the controller as shown a distributed processing architecture is preferred for maximum data signal processing capability and speed fig7 is the main flowchart describing the operation of the present invention in step s101 the memories and flags including e g the previously detected defocus amount the accumulation midpoint time the movement flag and the focus flag are initialized in step s102 a test is conducted to determine whether the half depressed switch is on if the half depressed switch is not on the controller 7 returns to step s101 if the half depressed switch is on the controller 7 advances to step s103 in step s103.