with one embodiment of the present invention in fig5 a portion of trigger circuitry 32 namely trigger units 100 and 104 are used to generate hardware breakpoint triggers when there is a match between a predetermined trigger value and a value on a portion of bus 20 e g address or data from cpu 12 alternate embodiments of the present invention may have any number of triggers 100 104 the hardware breakpoint triggers 100 104 are sent to a portion of the combining logic 36 by way of conductors 102 and 106 respectively where they are combined with other trigger sources such as inputs 56 from cpu 12 outputs 62 u2032 from other portions of action select and control logic 38 u2032 or outputs from multi function debug counters 34 all trigger sources can then be combined in the portion of combining logic 36 in a manner selected by the user e g by way of control bits in registers 30 examples of how these can be combined are anding oring as well as sequencing the trigger sources e g detecting the arrival of one trigger source before another arrives conductor 56 is used as an input to combining logic 36 to accept events from cpu 12 in the generation of final triggers in one embodiment combining logic 36 uses the execution of the debugev instruction in trigger generation in a first example using the circuitry illustrated in fig5 it is possible to generate a final trigger 119 only after finding a first trigger trigger 100 followed by finding a second trigger trigger 104 followed by the execution of a debugev instruction by cpu 12 only upon finding this precise sequence is a debug action performed by the action select and control logic 38 see.