formed on the stress relaxation film this structure provides a good wiring pattern and the antireflection film can be left unetched in the above embodiment only the process of forming the p channel device elements of the cmos transistor has been described during the cmos fabrication processes n channel device elements are also formed the p and n channel device elements are alternately formed by repeating similar processes such as ion implantation by covering an unnecessary region with a resist mask in forming the n channel p or other ions such as as are doped fig8 shows an example of the structure of a cmos semiconductor device on the surface of a p type si substrate 1 a p type well region 2p and an n type well region 2n are formed being separated by a field oxide film 3 gate oxide films 4 are formed on the surface of the p and n type well regions 2p and 2n over the channel regions thereof common gate electrodes are formed on the gate oxide films 4 source drain regions are disposed on opposite sides of the channel regions in the direction perpendicular to the drawing sheet the gate electrode is formed by a polycrystalline si layer 5 a refractory metal silicide layer 6 and an amorphous si stress relaxation layer 11 a tin antireflection film 10 is formed on the surface of the stress relaxation layer 11 the surface of the gate electrode inclusive of the tin film is covered with an interlayer insulating film 14 made of psg bpsg or the like via holes are formed in the interlayer insulating film 14 at predetermined areas to expose the gate electrode a first wiring layer is formed on the interlayer insulating.