that is clocked with every machine cycle whenever a transition of chosen polarity occurs on the data input pin the capture trigger pin the count in timer 1 is saved and the processor is interrupted at the beginning of the phase lock search the capture trigger data is set for triggering on the negative transition the waveform on the system bus having been inverted before arriving at the data pin this means that the first chip in the string of 32 phase lock chips will be ignored that chip is subject to distortion since it must establish the quiescent conditions in the filters for the subsequent waveform when the negative edge occurs the count in timer 1 is stored in the first of four sixteen bit registers when the next transition occurs the timer 1 count is stored in the second of the four sixteen bit registers the process is repeated for the next two samples after four samples have been stored the next sample overwrites the first one so that the registers act as a circular buffer containing the time of occurrence of the last four positive transitions after the processor stores each sample it examines the contents of the cycle time registers looking for a 19 2 khz pattern the cycle time for 19 2 khz is 256 of the microcontroller 39 s machine cycles the criterion used in the search is that four contiguous cycles need to be found in which the overall time.