of fig2 which includes an input filter 1 a second low pass filter 2 a first multiplier 3 interposed between the two filters a second multiplier 4 which is cascade connected to the low pass filter 2 and receives as an input a second carrier and a low pass filter 5 which is cascade connected to the second multiplier 4 therefore the block designated by 20 in fig7 substantially corresponds to the block designated by the reference numeral 20 in fig2 with the differences presented hereinafter an exception is that the block designated by the reference numeral 15 of fig7 corresponds to the block designated by the reference numeral 15 in fig6 this is in addition to the two carriers both of which are not phase correlated with respect to the phase u03c6 of the signal received by the tuner 11 and two multipliers 3 and 4 arranged in a cascade configuration the particularity of the circuit of fig7 is the fact that the frequency u03c9 b from the second carrier generated in block 7 is set equal to the sampling frequency 4 and is correlated to the local carrier u03c9 o t but is not correlated with respect to the phase of the input signal the choice made for the frequency u03c9 b simplifies the hardware complexity of the.