the potential energy within the silicon regions is controlled by these gates via six phase timing that was detailed in fig3 a and fig3 b pixel pair 400 further includes window regions 405 and 406 through which a wide band of photons can be sensed by the photosensitive silicon beneath it thus providing very high qe within the window regions 405 and 406 channel potential gradient regions are created via implant doping that may be but not limited to for example boron in case of a p channel ccd pmos or for example phosphorus in case of an n channel ccd nmos the channel potential gradient regions 405 and 406 provide a permanent gradient from high to low potential levels that facilitate high efficiency charge transfer i e high cte from cell 409 to cell 410 the charge transfer is controlled by changing voltage levels in each of the gates 401 404 following the six phase scheme as depicted in fig3 a and fig3 b cycling through the voltage levels accordingly changes the potential in each region beneath gates 401 404 from a high enough level to block charge from reaching the window region 405 or 406 respectively during the off phase to a sufficiently low level to allow charge to transfer from region 405 to 406 during the on phase in accordance with another.