to the address signal 159 and the write request signal 154 the main memory control circuit 21 performs the same operation as the case of reading data except that it controls the main memory unit 22 in such a way that the data signal 152 is written into the corresponding address location of the main memory unit 22 that is it turns the ack signal 158 on when the write operation of data is completed therefore the ack signal 128 is turned on and the completion signal 112 is provided to cpu 10 via the or gate 15 the rma signal 127 remains turned off even at the time of writing the data the cache 11 checks to see whether or not the data of the logical address on the line 116 has been stored and if the check result is affirmative a valid bit signal is produced on the valid bit signal line 121 as the ack signal 128 is turned on the rma signal line 127 is off and the write request signal 110 is on the cache control circuit 13 turns the write enable signal 118 on irrespective of the presence of the valid bit signal on the line 121 when the valid bit signal 121 is turned on the cache control circuit 13 turns the.