the previous value and the counter 171 is cleared to 0 next the count no on the counter 12 is held in the register 131 with the timing of the fall of the control signal cs0 no tc k is calculated by the adder circuit 132 and no tc k sc is calculated by the adder circuit 133 then sb is held in the register 14 and no tc k is held in the register 151 with the timing of the fall of the control signal cs4 a decision is made as to whether or not the absolute value of the difference between the current value and the previous value of no tc k equal to the absolute value of the difference between the current value and the previous value of the control input value s or the count no is equal to or less than 7 for instance by comparator circuit 162 and if the value is equal to or less than 7 the output from the comparator circuit 162 is set to low and otherwise it is set to high no tc k tc k no is calculated by the adder circuit 152 and max no is calculated by the subtractor circuit 153 next the output of the comparator circuit 162 is held in the d flip flop 163 with the timing of the fall of the control signal cs6 and is output as the frequency control complete signal eq next the control signal cs8 is provided to the or gate 18 and only when the frequency control.