the fifth lines of the diagram in the first mode of operation modem reception is activated during the a1 portion of each word the dpll 46 fig3 need not be synchronized with a synchronization bit but can achieve bit synchronization from either synchronization bits or data bits the receiver timing unit 48 fig3 which is driven by the output clock signal on line 56 from the dpll detects the word sync pattern and maintains frame sync in normal receiving mode before changing to extended standby mode the occasions of operation of the fast clock oscillator 100 fig5 correspond to the a1 portions of each word with activation of the fast clock oscillator 100 beginning prior to the a1 portion comparison of the alternative mode in lines 2 and 3 with the first mode in lines 4 and 5 of the diagram shows that the alternative mode has the advantage of reading two repeats a5 and a1 or b5 and b1 of two consecutive words including the synchronization data of the bs and the ws fields this providing for only half the number of wake up procedures for the fast oscillator 100 of the sleep clock 100 as occurs with the first mode of operation thus in the alternative mode of operation there is a consequent reduction in power wastage during wake ups with respect to.