the variation in dielectric constant k among different portions of the device fig3 a e illustrate many of the same process steps shown in fig2 a 2 d but with some variation fig3 a and 3 b are the same as fig2 a and 2 b although after the trenches 202 are formed in fig3 b a step of etching may be performed to remove the cap insulator layer 201 from areas of the ild 100 that are designated as high density this etching may be accomplished for example by using masking and photoresist techniques to remove the appropriate portion of the cap insulator layer 201 as shown in fig3 c the cap insulator layer 201 is completely removed from the surface of the ild 100 at the high density area 101 a but remains on the surface at the low density area 101 b then as shown in fig3 d and 3 e the liner 203 and conductive material e g metal 204 may be deposited and polished down using cmp as described above with respect to fig2 c and 2 d respectively in this example the amount of cmp used in the process between fig3 d and 3 e may be the same as between the high and low density regions avoiding the need for adjusting different polishing rates in the different regions other variations.