the lead 15 the simultaneous presence of these two signals produces an output from and gate 21 which in turn sets a d type flip flop 22 and strobes an i o address register 23 to store data being transmitted simultaneously on the bus 14 in the present embodiment this data is the 8 of 10 most significant bits of the i o operating address which ranges from hexadecimal 000 to 3ff thereafter the and gate 21 is disabled by the q output of the d type flip flop 22 which is connected to the gate 39 s inverted input via a switch 24 the register 23 is then latched with this address this q output also enables an i o match detector 25 which has one input connected to the output of the i o address register 23 and the other input to the address bus 13 thus when the system is initially powered up the peripheral unit 10 does not respond to any i o address until after data defining the 8 most significant bits of the 10 bit i o address has been transmitted via the data bus 14 to the register 23 thereafter any transmission of this i o address on the bus 13 will result in a match being detected in the address match detector 25 which generates a gating signal that in conjunction with control signals on either i o read or write strobes 27 or 28 transfers data to or from an i o unit 26 on the data bus 14 since the entire address range for the ibm pc is from hexadecimal 00000 to fffff while that of all the i o.