to the position of the ram the second averaging component 58 then performs a time average of the second sinusoidal signal 54 related to the position of the ram over an interval of time equal to an integer multiple of one period of the second sinusoidal signal 54 related to the position of the ram after calibration is complete the second averaging component 58 sets the value of the second digital error signal 62 by subtracting the average value of the second sinusoidal signal 54 related to the position of the ram from the value of the dc offset required by the second a d converter 50 second digital error signal required dc offset u2212 average of second signal related to position 12 the second digital error signal 62 is then converted into the corresponding second analog error signal 70 by the second d a converter 66 and the second subtractor 42 removes the error component from subsequent analog values of the second combined signal 38 hereafter the second calibrated signal 46 will have a precise dc offset equal to the dc offset required by the second a d converter 50 as already disclosed in an embodiment of this invention the first a d converter 48 and the second a d converter 50 are included on the msp430 mixed signal processor the a d converters on the msp430 mixed signal processor convert analog signals within the range of 0 v 3 v to 12.