through the two conductive vias 514 a 514 b and capacitive coupling via the other floating electrodes 506 a 2 506 b 2 506 a 3 506 b 3 this rf bias is then coupled to the entire wafer through the top electrodes 506 a 1 and 506 b 1 again such distributed rf coupling through multiple layered electrodes can minimize local thermal stress that may otherwise arise from excessive heating when only a single electrode is used it is understood that the embodiment shown in fig5 b may be fabricated using different combinations of the same process steps stacking material layers drilling and filling conductive vias and sintering previously described for example this embodiment may be fabricated by stacking the respective ceramic layers 504 i i 2 to 7 and the electrode layers 506 a i and 506 b i i 2 to 4 in proper sequence forming the conductive vias 514 a 514 b followed by the silk screening of electrodes 506 a 1 506 b 1 stacking the ceramic layer 504 1 on top of the electrodes 506 a 1 506 b 1 and sintering the entire structure another alternative embodiment is shown in fig6 where a pin 608 is shown to intersect a.