and descrambler implemented in a physical layer of a networking device is shown for clarity sake the representative polynomial for the self synchronous scrambler and descrambler is x n 1 thus at any given time the state of the scrambler descrambler is the contents of the respective n bit shift register referring to fig6 a scrambler 600 includes an n bit shift register 610 clocked by a clocking signal clk 1 at each clk 1 cycle a most significant bit of the shift register 610 is loaded into a first input of a logic gate 620 e g exclusive or u201c xor u201d concurrently a bit of a descrambled bit stream 630 is loaded into a second input of the logic gate 620 which produces a bit of a scrambled bit stream 640 this bit is also fed back as a least significant bit of the shift register 610 for subsequent scrambling operations it is noted that the scrambler 600 can be initially set to any arbitrary value for security purposes the initial state of the scrambler 600 is usually set to a random value the initial descrambler state is irrelevant because it will acquire the correct state from the scrambled data stream the first n descrambled bits e g for an x n 1 descrambler will be wrong because the descrambler is still collecting the correct state referring now to fig7 a descrambler 700 corresponding to x n 1 scrambler 600 includes an n bit shift.