17 that receives an m bit signal in any one clock cycle and transmits on bus 15 two n bit signals at the two clock edges of the next clock cycle i e m 2n similarly a second circuit 18 includes a decoder 19 that receives from bus 15 the two n bit signals at the two clock edges and generates a single m bit signal in the next clock cycle note that encoder 17 is clocked by a signal clock_ 1 that is different from signal clock_ 2 used to clock decoder 19 although both signals have the same frequency e g 125 mhz in the implementation illustrated in fig4 test signal generator 20 included in circuit 16 is similar to the above described test signal generator 9 except for the following differences specifically test signal generator 20 is coupled to a storage element also called u201c pattern register u201d 21 to receive therefrom a predetermined pattern that is used to generate test signals test signal generator 20 generates and supplies to encoder 17 two test signals in each cycle thereby to test the use of successive clock edges i e positive edge and negative edge on bus 15 moreover in the implementation illustrated in fig4 a test signal checker 22 included in circuit 18 is similar to the above described combination of test signal generator 10 and comparator 11 fig2 except for the differences related to ddr described above in reference to test signal generator 20 for example test signal checker 22 simultaneously compares in each cycle two.