in fig4 the data storage apparatus 1 includes an interface 20 coupled to a data read write device not shown for data buffering and transmitting therebetween a non volatile memory 21 a flash memory 22 for storing data an encryption unit 23 and a decryption unit 24 which would be expatiated in the follow up descriptions the non volatile memory 21 is stored with an encryption key and a decryption key each of the keys is a field of bits used to encrypt and decrypt data using techniques known to those of skill in the art by adoption of cryptograph algorithms the above identified keys are generated on the basis of a user supplied password usually a combination of number digits by applying the bit values of the keys to those of the data and conducting logical operations associated with selected encryption algorithms inclusive of advanced encryption standard aes data encryption standard des triple des and rsa rivest shamir adleman the encryption unit 23 and the decryption unit 24 are operable to perform encryption and decryption of the data in accordance with the encryption key and decryption key certainly both keys can be revised by the read write device in this embodiment both keys are u2018 symmetrical u2019 both encryption and decryption use the same key yet in alternate embodiments both keys can be u2018 asymmetrical u2019 encryption and decryption keys are different each of the key is encrypted and decrypted at the 128 bit level in this embodiment while the 64 bit 196 bit or 256 bit key is acceptable to implement the present invention in addition the flash memory 22 includes a header portion 221 containing a bios parameter block bpb the bpb is used.