of fig1 the circuit of fig4 has the complicated arrangement wherein four two input nand circuits are required for each of the exclusive or circuits 24 1 24 2 a simplified alternative arrangement is shown in fig6 waveforms derived at points a b c d e f and g in the alternative circuit of fig6 are shown in fig7 a to 7g respectively the circuit of fig6 has depletion type mos fet 42 enhancement type mos fet 44 and capacitor 46 to form an inverter 48 capable of producing an output signal of a waveform having slow rise and rapid fall an address signal ad 1 shown in fig7 a is converted by means of the inverter 48 into a signal as shown in fig7 b of a waveform having rapid fall and slow rise depletion type mos fet 50 and enhancement type mos fet 39 s 54 and 56 are connected to form a nor circuit 58 and the signal of fig7 b from the inverter 48 is fed to the gate of mos fet 54 in the nor circuit 58 the address signal ad 1 of fig7 a is fed on the other hand to an inverter 64 of depletion type mos fet 60 and enhancement type mos fet 62 in which the same is inverted into a signal shown in fig7 c the latter is converted to a waveform shown in fig7 d by means of an inverter 72 which is formed by depletion and enhancement type mos fet 39 s 66 and 68 and capacitor 70 to permit production of an output pulse of a waveform having slow rise and rapid fall the output signal of fig7 d from inverter 72 is fed to the.