data during synchronization in an embodiment of the present invention the pll front end 52 is a state machine which filters any noise close to the edges and calculates the midpoints between the edges a back end 54 of the pll 42 receives not only the data edges 308 40 but also u03b4 and on the basis of u03b4 the back end 54 calculates a reference position for the rising edges and another reference position for the falling edges as a result of calculating these reference positions the pll 42 will not advance or retard for each symbol change because the active rising and falling edges are close to the respective calculated reference positions fig6 illustrates a vector diagram of a substantially jitter free pll the rising reference points u03b4 2 56 and the falling reference points u2212 u03b4 2 58 are disposed in the right hand half of the diagram and the recovered clock 50 is disposed in the left hand half of the diagram symmetrically of the reference points 56 58 having regard to fig5 the pll 42 will advance only when an edge occurs after its reference position and will retard when an edge occurs before its reference position the circuit arrangement shown in fig5 enables jitter due to different symbol length to be greatly reduced without decreasing the bandwidth of the pll the lock time can be maintained fast not to miss synchronisation finally.