38b and 39a 39b fig3 illustrates schematically a control circuit for using the capacitance measurements made with the capacitor plate pairs 38a 38b and 39a 39b to position the measuring head over the surface of the test wafer 8 a bias voltage is applied to some group of the capacitor plates in the array 32 for example 38a 38b and 39a 39b to drive the semiconductor wafer surface below these plates into what is known as the accumulation mode in this mode capacitance measurements made using the biased group of capacitor plates are insensitive to the properties of the wafer and are predominantly dependent on the thickness of the air gap the capacitor plate pairs are individually connected to a standard capacitance measuring circuit 50 this circuit 50 may have four or more channels for producing capacitance measurements simultaneously from each electrode on the head or may multiplex inputs for sequentially making capacitance measurements the four outputs 50a 50b 50c and 50d are combined in two comparator circuits 51 52 and an adder circuit 53 the difference between the capacitance measurements made with capacitor plate pair 38a 38b is detected by comparator circuit 51 the difference is scaled by circuit 54 to produce a longitudinal adjustment signal the difference between the capacitance measurements made with capacitor plate pair 39a 39b is detected by comparator circuit 52 the difference is scaled.