control signal is active high in this embodiment the feed forwarded signal wd passes through the passing gate 25 activating a wordline signal wln a circuit 27 preferably provided by a n type metal oxide semiconductor nmos transistor is further used for enabling a few of bitline passing gates 28 and a few of sense amplifiers 29 by pulling down the bitline passing gate control signal bli enb and the sense amplifier control signal samp enb if no write operations have occurred since the last reset on the rows controlled by latch 21 then no valid data has be written to rows of the memory cells normally accessed by signal wd moreover because no write operations have occurred since the last reset the signal wd and the write signal we have not become active simultaneously and thus latch circuit 21 remains in its initial state until a write operation occurs with latch 21 in its initial state the access signal wd is inhibited from passing through passing gate 25 if a read or refresh is attempted thus the rows of memory cells which are normally accessed by signal wd are not read or refreshed if they do not contain valid data thus the object of saving electrical power by not performing a refresh operation on those rows of memory cells containing no valid data is thus achieved fig3 shows another embodiment of the present invention comparing with the diagram of fig2 the combination of gates g1 g2 and t9 in fig3 act as the latch circuit 21 in fig2 the transistors t1 t2 and t3 of fig3 together act as gate 23 in fig2 transistors t4 through t8 in fig3 together perform the function of passing gate 25 in fig2 further transistor t10 in fig3 behaves the same.