on the other hand when the seventh nmos transistor t 7 is turned on the output line 14 i is connected to the fifth node p 5 at which no voltage is applied consequently the second capacitor cp 2 maintains a low voltage and the ninth nmos transistor t 9 turns off thus the seventh and eighth nmos transistors t 7 and t 8 act as control circuitry controlling the output circuitry in the first exemplary embodiment the clock signals c 1 to c 4 have a swing width of about 0 to 10v in this case the high voltage v high is set to have a value of about 15 to 25v in other words in the first embodiment a low voltage of less than 10v can be applied to the stages 12 1 to 12 n alternatively the transistors in the first embodiment may be replaced by other switching element types that include an input terminal an output terminal and a control terminal such as a pmos transistor in the case of a pmos transistor clock signals c 1 to c 4 may have a swing width of about 0 to 10v for example the high voltage v high may be set to about u2212 8v while the ground voltage vss is set to about 10v 0048 fig7 is a detailed circuit diagram of a stage and a level shifter according to a second embodiment of the present invention in fig7 the i th stage 12 i includes second and fourth nmos transistors t 2 and t 4 connected to a ground voltage vss a third nmos transistor t 3 connected to a supply voltage vcc fifth and sixth nmos transistors t 5 and.