a resulting phase and frequency correction u03b4 u03b8 and f the microprocessor 12 outputs a digital code which represents the number of clock cycles of a clocking signal will occur before an output pulse will be produced by the programmable divider 22 phase shifter 24 then phase shift the output from the divider 22 to produce the output frequency u03b8 out the phase shifter 24 is also under control of the microprocessor 12 as to the amount of phase shift that will be applied referring now to fig3 a block diagram of the present invention is shown the digital phase locked loop according to the invention consists of a phase sensitive detector 26 a microprocessor 12 a binary rate multiplier 26 and crystal controlled oscillator 28 phase detector 26 is shown responding to the input frequency signal u03b8 in the output frequency signal u03b8 out and a clocking frequency 256f where f is the frequency of the output signal u03b8 out in other words the binary rate multiplier is operated at a frequency 256 times the operating frequency of the phase locked loop microprocessor 12 may be any standard microprocessor having sufficient execution speeds to execute a program according to the flow.