
{"publication_number": "US-2004041592-A1", "abstract": "an integrated circuit logic topology or architecture suitable for low voltage differential logic operating at radio frequencies is disclosed . the topology , referred to as enhanced pseudo common mode logic , is similar to and compatible with traditional cml , and provides the additional advantage of eliminating the need for level conversion between consecutive logic gates , thereby increasing the potential maximum operating frequency of subsystems implemented using the invention . the invention retains most of the advantages of traditional cml , and in addition permits the independent selection of output logic high level and output logic low level so that they may be matched with the succeeding circuit input levels .", "application_number": "US-22966002-A", "description": "the invention will now be described in terms of examples of fundamental logic gates . note that , for the sake of clarity , in the figures and their associated descriptions , any supplementary , subsidiary , and parasitic components which are not concerned with the fundamental operation of the invention are omitted and their effects are not discussed here . [ 0029 ] fig2 presents an exemplary two - input \u2018 and \u2019 gate in a preferred embodiment of the invention , shown symbolically 200 , and schematically 201 . here , the complementary logic gate is conveniently considered as two separate circuits ( half gates ), although in practice , some subsidiary or parasitic common elements may also be present . in the circuit of fig2 the complementary input signals a and { overscore ( a )