the data out loads and the clock out loads are matched at three each namely the data out of dram 314 corresponding to one of lines 321 for example sees its own load the load of the corresponding input output pin of dram 306 and the load of the corresponding input output pin of ic chipset 304 connected via data out line 321 the first clock out of dram 314 sees its own load the corresponding load of dram 306 and the corresponding input load of ic chipset 304 and the second clock sees its own load the corresponding clock output load of dram 307 and the input load of ic chipset 304 further the clock output of dram 307 for example also sees three loads thus each clock output and each data output sees three capacitive loads as such the data and clock signals output from dimms 300 and 302 have the same delay thereby eliminating the skew encountered by the prior art memory systems thus the ratio of the number of clock outs to dqs of dimm 300 i e 1 8 equals the ratio of clock outs to dq of dimm 302 also 1 8 accordingly as noted above the capacitive loads seen by each dq is the same as that seen by each clock out although the preferred embodiment was described with two dimms using x8 drams and x16 drams the invention is not limited to this configuration in.