of the present invention the phase interpolation circuit shown in fig3 includes five inverters and two controlled switches the input end 311 of the first inverter 31 receives a phase leading double level clock signal ck 1 and the input end 321 of the second inverter 32 receives a phase following double level clock signal ck 2 and the output end 322 of the second inverter 32 is connected to the output end 312 of the first inverter 31 to form a common output end 30 the input end 331 of the third inverter 33 connects to the common output end 30 electrically the output ends of the fourth inverter 36 and the fifth inverter 37 are connected to the input ends of the first inverter 31 and the second inverter 32 respectively the circuit further includes the first controlled switch 34 and the second controlled switch 35 to avoid short circuit current in the present invention the first controlled switch 34 connects between the first inverter 31 and the second inverter 32 and the electrical power source vdd the switch 34 is off when the double level clock signal ck 1 is in the high level state the switch 34 will be turn on when the double level clock signal ck 1 is in the low level state the second controlled switch 35 connects between the first inverter 31 and the second inverter 32 and the ground gnd electrically the second controlled switch.