bit b u201c busy u201d 9 which is set from zero to one if that interleave 3 at that time step 5 is reserved by an operation of a cache request in the example shown the cache requests starts with interleave 2 which is why at the time offset x 0 interleave i 2 is marked busy in the next cycle which is time offset x 1 the request busies the next interleave which is i 3 with only four interleaves the next interleave the request targets in the next cycle is interleave 0 that way a request 39 s reservations in the interleave model proceed diagonally down from left to right fig2 is a schematic drawing comprising an interleave model of a cache processed by a processing pipe with prior art in pipe checking drawing a shows a situation without an interleave conflict and drawing b illustrates a situation with such a conflict the component of a multiprocessor system essential for the current invention is a shared cache 11 under the control of a processing pipe 21 as an example fig2 shows a level 2 cache l2 cache 11 shared by several processing units pus 13 each equipped with a level 1 cache l1 cache pus 13 issue fetch and store requests towards the l2 cache 11 the requests are stored in request registers 17 19 ie address registers normally separately for fetches and stores called fars 17 and sars 19 the request registers 17 19 compete for l2 cache access the access itself.