description one method to enhance the q factor of a chip inductor is reducing the power consumption of the chip inductor due to its parasitical resistor the present invention adopts a negative resistance generator which provides negative resistance to compensate for the parasitical resistor of the chip inductor please refer to fig1 fig1 is the circuit configuration of the present invention illustrating a negative resistance generator 120 compensating for the parasitical resistors of inductors 112 and 114 the inductors 112 and 114 together with an operation circuit 116 construct an application circuit 110 the negative resistance generator 120 is coupled to the application circuit 110 to compensate for the parasitical resistors of the inductors 112 and 114 the negative resistance generator 120 comprises a pair of transistors 122 and 124 which couple to each other in this embodiment p mosfet 39 s serve as exemplary devices for the transistors 122 and 124 for the sake of illustrating the configuration but are not meant to be a limitation of the present invention the gates of the transistors 122 and 124 are coupled to each other and then further coupled to the drain of the transistor 122 through a capacitor 126 and to the drain of the transistor 124 through a capacitor 128 the capacitors 126 and 128 are ac coupled capacitors utilized for separating dc components and ac components moreover a voltage level vc is coupled.