that two addresses are decoded in each block where the address strobe is generated by the system clock clk delayed by the two inverters or more as required consisting of fets 201 204 the output clk of the inverter comprising fets 201 and 202 is also connected to transistors 205 and 206 which precharge nodes 207 and 208 respectively to vdd vt in order to reduce the effect of charge sharing on nodes 209 and 210 respectively fets 205 and 206 may not be required in different technologies or with different transistor sizes the address decoder is designed such that the select node 211 is precharged high when the clock clk is low thus turning on transistors 212 and 213 the delayed clock strobe turns off fets 214 and 215 and turns on fets 216 and 217 precharging nodes 209 and 210 to vdd which causes outputs decout lt 1 gt and decout lt 0 gt to go low typically data address bits a3 through a0 will be active before the clock goes high via a transparent latch notice that the select node 211 is high until any or all of high order addresses a3 through a1 go high which prevents the corresponding decoutn from going active thus the default is that all select signals are high until they are not selected by any of the inputs a3 through a1 going high only one decoded.