logic type gate having a first input terminal connected to v in and a second input terminal connected to an output line 64 of microprocessor 34 or line 33b produced by modem dotting pattern detector 32 may be connected directly to this input of gate 60 the output terminal of gate 60 is connected to one end of resistor 56 the other end of resistor 56 is connected to the comparator inverting input the resistance of resistor 56 is much lower than that of resistor 58 when microprocessor 34 applies a logic level 1 signal via line 64 to the input of gate 60 the gate turns on to effectively place resistor 56 in parallel with resistor 58 decreasing the time constant of rc network 24 in the preferred embodiment the lowest frequency component in the dotting pattern preceding each incoming message is 4 8 khz while the lowest frequency component in received digital data e g word sync pattern following the dotting pattern is about 10 hz in the preferred embodiment rc network 24 has a time constant of 0 33 milliseconds during the time a dotting pattern is expected to be received this time constant corresponding to a cut off frequency of about 3.