22 is deposited at a preferred temperature that is about 50 u00b0 c lower than the deposition temperature of the seed layer 20 to minimize the boron dopant profile of the base the portion 22 a of layer 22 over the device areas 2 forms a good quality si u2014 ge layer for the base while the portion 22 b over the sti regions 12 has reduced grain size because of the reduced grain size of the underlying portion 20 b of the seed layer 20 the reduced grain size of the si u2014 ge portion 22 b also results in fewer discontinuities voids thereby improving the electrical conductivity between the base 22 a and the contact region 22 c stile referring to fig4 a silicon cap layer 24 is epitaxially formed on the si u2014 ge layer 22 the cap layer 24 is deposited at the same lower temperature as the si u2014 ge layer 22 so prevent excessive boron diffusion layer 24 is deposited to a preferred thickness of between about 50 and 200 angstroms and more specifically to a thickness of about 100 angstroms referring to fig5 the silicon cap layer 24 the si u2014 ge layer 22 the seed layer 20 and the polysilicon layer 18 are patterned to the insulating layer 16 to form the si u2014 ge base 6 for the bipolar transistor over the device areas 2 and leaving portions of the patterned layers extending over the sti regions 12 and over the polysilicon layer 18 to provide electrical contact regions 8 for the base 6 layers 24.