subjected to an ion implantation of phosphorous at an energy between about 50 to 100 kev at a dose between about 5e14 to 1e16 atoms cm 2 conventional photolithographic and rie procedures using cl 2 as an etchant are used to create the polysilicon gate structure 4 schematically shown in fig1 after photoresist removal via plasma oxygen ashing followed by careful wet cleans a silicon oxide layer is deposited using either lpcvd or plasma enhanced chemical vapor deposition pecvd processing the silicon oxide layer is grown at a temperature between about 500 u00b0 to 800 u00b0 c to a thickness between about 1000 to 4000 angstroms using tetraethylorthosilicate teos as a source a selective anisotropic rie procedure using chf 3 as an etchant is used to create insulator sidewall spacer 5 an ion implantation of arsenic at an energy between about 50 to 100 kev at a dose between about 5e13 to 5e14 atoms cm 2 is used to create source and drain regions 6 schematically shown in fig1 the process continues with the deposition of silicon oxide layer 7 obtained via either lpcvd or pecvd processing at a temperature between about 500 u00b0 to 800 u00b0 c to a thickness between about 5000 to 8000 angstroms a contact hole 8 is created in silicon oxide layer 7 to expose polysilicon gate structure 4 the contact hole 8 is formed via conventional photolithographic and rie procedures using chf 3 to etch silicon oxide layer 7 photoresist removal is accomplished via plasma oxygen ashing followed by careful wet cleans a deposition of aluminum containing between about 1 to 3 copper and between about 1 to 2 silicon is performed.