including a reset power down signal rp a chip enable signal ce a write enable signal we and an output enable signal oe where the u201c u201d denotes a signal as being low true an external processor not shown applies command codes on a data bus dq 0 dq 15 and these command codes are applied through a data input buffer 416 to the csm 404 a command being applied to the flash memory 400 includes the control signals rp ce we and oe in combination with the command codes applied on the data bus dq 0 dq 15 the csm 404 decodes the commands and acts as an interface between the external processor and an internal write state machine wsm 408 when a specific command is issued to the csm 404 internal command signals are provided to the wsm 408 which in turn executes the appropriate process to generate the necessary timing signals to control the memory device 400 internally and accomplish the requested operation in response to the rp and or ce signals the csm 404 develops applies signals to the delay circuit 312 and switch 314 see fig3 a to control the mode of operation of the bandgap switching circuit 300 in one embodiment when the ce signal goes active low the csm 404 drives the cei signal low placing the bandgap switching circuit 300 in the active mode of operation when the ce signal.