output terminal c o0 of the full adder 10 is connected to a carry input terminal c i 1 of the upper full adder 11 a carry output terminal c o1 of which as connected to a carry input terminal c i2 of the upper full adder 12 the same state of connection as the above described state of connection between the carry output terminal of the lower full adder and the carry input terminal of the upper full adder is maintained between the similar terminals of the full adders 12 13 and 14 however a carry output terminal c o4 of the full adder 14 is open circuited whereas a carry input terminal c i0 of the full adder 10 is grounded and is perpetually at a low l level within the latch section 25 clock terminals ck 0 ck 1 ck 2 and ck 3 of the d flipflops 20 21 22 and 23 are connected in common and fed with clocks u03c6 the as for connection between the full adder 10 d flipflop 20 and a data input terminal 70 the data input terminal 70 is connected to input terminal a 0 of full adder 10 an addition output terminal s 0 of which is connected to a data input terminal d 0 of d flipflop 20 and an affirmation output terminal q 0 of which is connected to an input terminal b 0 of the full adder 10 as for connection between the full adder.