receive an enable signal to enable first phase lock loop 92 and second phase lock loop 94 and a second line 141 is provided to receive an enable signal to enable third phase lock loop 96 coupled between the line 143 which receives the clock in signal and the second phase locked loop 94 is a first delay circuit 108 for providing a delay in enabling second phase locked loop 94 after first phase locked loop 92 is enabled for proper timed operation of phase locked loop circuits 92 and 94 delay 108 is activated simultaneous with first phase locked loop 92 by the low speed enable signal ls pll enable the low speed enable signal is also forwarded to one input of gate 110 to delay activate second phase locked loop circuit 94 activation of the third phase locked loop circuit 96 is delayed in a similar manner by second delay circuit 112 for a period after which second phase locked loop circuit 94 is enabled i e if the corresponding enable signal at line 141 is also asserted thus two of the enable signals sent from pmu 24 are used to enable first second and third phase locked loop circuits 92 96 in accordance with ls pll and hs pll enable signals if phase locked loop 94 is enabled a low speed clock ls clk of for example 36 864 mhz is provided to various parallel connected dividers denoted as third divider 114 fourth divider 116 fifth divider 118 sixth divider 120 and seventh divider 122 each divider can have a dissimilar division factor from that of the other dividers such that for example third divider 114 is.