logic 300 and hence the calibration method of the invention it should also be noted in connection with fig3 that a command bus cmdbus and a command clock xclk and its inverse xclk are driven by controller 360 into command decoder 397 an address bus addbus is fed into load mode register 395 when the control logic 300 is enabled by the load mode register 395 command e g upon power up or reset the memory controller 360 drives a continuous known repeating data pattern e g u201c 1100 u201d to each write data input path dq the data pattern is fed through to buffer 305 adjustable delay 310 and data latch 317 as described above however since the calibration system 390 is enabled e g through the enabling of the control logic 300 the data is next fed into control logic 300 turning to fig4 a data latch 317 sequentially latches the data at four different clock edges the data are then stored in four different registers bits 1 4 of data register 320 at the output of the data register 320 the data is fed into phase detector 330 with a 4 bit bus 325 phase detector 330 receives the initial data captured by the data register 320 here four bits and passes it through a logic circuit which determines whether the data captured by the data register 320 is the known 4 bit pattern u201c 1100 u201d being sent by the controller 360 to each data path dq as will be explained below.