is completed in the ipu 10 by loading the ipu 39 s copy of the csar from the opbr 45 register and then loading bits 12 17 of the opbr 45 register from the opbr lsac 53 register cycle 3 is occupied by two main activities and represents the end of the opbr process the first activity occurs in the csu 30 where the contents of the csar 39 are used to access the cs array 35 the microinstruction stored at the accessed location is assembled from bit sliced portions across 6 cs chips and is sent to the ipu 10 the second activity consists of a concurrent operation in the ipu 10 where the ipu 10 sends the opbr lsac 53 contents latched in the opbr register 45 to the csu 30 over the csoa 103 bus this operation ends the opbr process and the ipu card 10 is now in normal micromode in normal micromode the csu 30 can perform one of two possible operations the first may consist of accessing and driving a microinstruction while latching the incremented csar 39 that points to the next sequential microinstruction the second operation may be a response to one of the interface commands such as 34 hold 34 34 branch 34 or 34 return 34 the ipu remains in micromode until an endop microinstruction is encountered cycle 4 begins the decode of the first microword in the microprogram since the micro architecture is a reduced instruction set ris type the execution of each microword resembles either rr type load type or store type instructions of the s 370 architecture each of these microwords.