the connector element p1 encoded or uncoded form the test signals emitted by the memory psp are decoded with the assistance of the decoder cd and supplied for example to a logic circuit ts the output of the logic circuit ts can be fed to a transmitter sg which forwards the test signals to the connector element p1 or respectively can be connected to a receiver which receives the output signals from the unit under test over the connector element and analyzes the same by way of comparison in the exemplary embodiment of fig1 only the transmitter sg is illustrated and not the receiver only this case shall therefore be explained below an address control is provided in order to be able to emit the coded test signals contained in the memory psp to the assigned connector element in a proper sequence in the exemplary embodiment of fig1 a single central address control is provided for all test signal generators sch the central address control comprises a sequencer se and a changeable or alterable microprogram memory mps the addresses for the memories psp of the test signal generators are stored in the microprogram memory mps the microprogram memory mps is in turn addressed by the sequencer se in order to accelerate the generation of the addresses an intermediate register pr1 can be located between the sequencer se and the microprogram memory mps and a second intermediate register pr2 can be disposed at the output of the microprogram memory mps by so doing the sequencer se already generate the address of the next microprogram word in the microprogram memory mps while the preceding microprogram word is just being read from the microprogram memory sps or respectively the preceding microprogram word can still be stored in the second intermediate register pr2 while.