and a particular matrix represented by parameter register 52 is selected similarly the number of and gates 62 which are connected to parameter register 53 and 54 is found by multiplying n3 times n4 the number of and gates 63 is found by multiplying n 5 times n 6 which corresponds to the number of d matrices multiplied by number of outlets when the proper clock signal gates 61 62 and 63 are selected which represent the particular a horizontal bc link and d outlet respectively these gates are enabled at the appropriate time this is accomplished by and gate 70 which gates the network clock with a signal transmitted via i o port 40 by processor 10 as a result of processor 10 transmitting the enabling signal and the coincidence of this enabling signal with the network clock the appropriate ones of and gate 61 62 and 63 are enabled to operate the corresponding d type latches of the network a similar operation exists for deriving the data control signals by data signal gates 80 as did for deriving the clock control signals by clock signal gates 60 the number of and gates represented by and gate 81 is equal to n 2 the number a matrices multiplied by n 3 the number b matrices this is the number of ab links for example if the number of a matrices is 16 and the number of b matrices is 4 there would be 64 and gates 81 which is the number of ab links parameter registers 51 and 52 are connected to data signal gates 81 in a matrix fashion so that one gate is selected for the concurrence of the parameter registers 52 and 53 similarly and gates 82 are connected to parameter registers 54 and.