from the leftmost output terminal thus if the input terminal 12 has a logic 1 and input terminals 13 and 18 have logic 0 signals the output signal generated by the circuit represented in fig1 is 10000000 if the input terminals 12 13 and 18 receive only logic 1 39 s then the output terminal generates a 11111110 output signal the rightmost terminal is always logic 0 since decoder circuit represents eight values 0 to 7 in decimal likewise if only logic 0 39 s are sent to the input terminals 12 13 and 18 then the output signals are 0000000 thus a mask decoder circuit is simply a circuit which translates the binary number at the input terminals to a corresponding number of masking bits at the output terminals as mentioned above the example here has the masking bits starting from the leftmost output terminal note that the masking circuit of fig1 is composed of one or more masking circuits of lesser complexity in the mask decoder circuit of fig1 which has three input terminals n 3 a mask decoder circuit 10 of lesser complexity n 2 forms a part of the n 3 mask decoder circuit in the n 2 mask decoding circuit 10 the three.