data line rx d 11 and control line rx_error 12 the figure shows that the filtering circuit has a temporary memory or register 4 filter memory 6 an interface to an external circuit 20 for instance a cpu the filtering circuit or unit also has a control unit or control logic 8 an error detecting interface in the mii preferably a reception error bus or line rx_error 9 is connected to a signal line to the mac 2 the media independent interface mii may be a reduced media independent interface rmii or another variation of a media independent interface such as a gigabit media independent interface gmii reduced gigabit media independent interface rgmii or other bus with separate control and data lines in fig2 the phy 1 is connected directly to the mac 2 and the circuit 3 is also connected to the same bus rx_error is connected through the circuit 3 between phy and mac the circuit has a list of traffic rules or an access control list preferably stored in filter memory storage device 6 used for comparison to detect unwanted or wanted network traffic and this list may be a constructed based on traffic analysis or b a list updated by the embedded system of the electronic device or c a list of unwanted traffic blacklist or d a.