and generally provides the instructions directing the on board processors and error correction circuitry chip 100 additionally communicates with a host processor 108 via an atapi bus interface 109 and atapi bus 110 in the case of a pc based system the host performs the actual processing of the audio video information or data retrieved from the disk after error correction and buffering by chip 100 among other things the host performs audio and video mpeg decoding and generates the corresponding user interface buffers dram 111 support error correction functions and the streaming of data from chip 100 to host 108 referring to fig2 which is a detailed functional block diagram of data path 200 attenuators 201 are used in the preferred embodiment to protect the inputs to following vgas from damage from any over voltages produced by the pickup offset controls 203 a and 203 b allow the digital offset control loop discussed below to respond to dc and low frequency baseline offsets in attenuators 201 and vgas 202 data channel summation and variable gain amplifier vga circuitry 202 add one or more signals from the transimpedance amplifiers on pickup 101 to form a composite data signal e g a b c d alternatively the signal addition may be done right on pickup.