the circuit is the equivalent of fig1 b it is understood that in an alternative embodiment an opposite polarity for the multiplexor control signal 245 may be used it is the function of the control circuit to determine from the phase relationship between clock_a and clock_b which configuration may be used reliably and to select multiplexor 240 accordingly it is understood that the multiplexor select signal 245 is common to all bits in the n bit wide data path it is understand that in an alternative embodiment the first flip flop device 210 in the first clock domain may be an integral part of the logic of the first clock domain and not exclusively used by the data path circuit the control circuit 300 for determining the state of the multiplexor control based on the phase relationship between clock_a and clock_b is now described in greater detail with respect to fig3 as shown in fig3 the clock_a input to control circuit 300 is delayed by approximately a u00bc clock cycle by a delay line element 310 and then is inverted by inverter device 320 resulting in the equivalent of a u00be clock cycle delay fig4 illustrates in greater detail the timing relation between the clock_a signal.