or u2014 nc to the non controlling input 214 of the nor gate 211 in fig3 b b i or u2014 nc o or u2014 nc and output 216 characteristics are shown as illustrated both i or u2014 nc and o or u2014 nc signals have a substantially simultaneous fall as these signals fall see e g the right half of fig3 b b the output 216 will rise after an output rising delay 320 see also fig2 a b once i or u2014 nc rises the output 216 will fall after an output falling delay 318 see also fig2 a a accordingly the system 300 of fig3 b a can determine both the rising and falling output delays for the nor gate 211 also indicated is a non controlling rise input delay 316 between the time i or u2014 nc rises and when o or u2014 nc falls see e g the left half of fig3 a b it is envisioned that the rise delay 316 be selected such that it is sufficiently longer than the output falling delay 318 otherwise if the o or u2014 nc signal rises prior to the output 216 falling the falling output delay for the output 216 may not be accurately determined it is envisioned that no logic gate be used in design of the and_nc and or_nc devices in part because logic gates generally have a finite delay through them based on the i o characteristics of these devices as illustrated in fig3 a b and 3 b b it is desirable that the output signal be substantially similar to the input signal for at least one of the edges i e without any finite delay for example fig3 a b illustrates that i and.