transistors q 1 and q 4 respectively and the outputs of muxs 24 and 26 are coupled to the diagonally opposed bridge transistors q 3 and q 2 respectively a first modulo n counter 28 clocked by the ul signal on line 12 controls the logic level at the select input sel of mux 22 inverter 30 applies a signal of the opposite logic level to the select input sel of mux 20 a second modulo n counter 32 clocked by the ur signal on line 16 controls the logic level at the select input sel of mux 26 inverter 34 applies a signal of the opposite logic level to the select input sel of mux 24 the modulo n counters 28 and 32 both count the number of switching cycles of the bridge converter but with a one half cycle phase shift each counter operates at a 50 duty cycle as illustrated producing a logic one output for n switching cycles followed by a logic zero output for n switching cycles and so on in the logic one case the gate signals ul lr ur and ll control the transistors q 1 q 4 q 3 and q 2 respectively to carry out the switching sequence of fig2 a in the logic zero case the gate drive signals lr ul ll and ur control the transistors q 1 q 4 q 3 and q 2 respectively to carry out the switching sequence of.