these points it will be appreciated that the precharge speed is not predominant over the balance speed thus there is no problem even when a slight resistance is added to the precharge level signal 103 next a reduction in balance speed due to the use of stacked polysilicon is considered even when the sheet resistance of stacked polysilicon is high the pair of bit lines can be connected having a resistance value of tens of ohms because a wiring length to connect between the precharge transistor and the pair of bit lines is short the resistance value is sufficiently small compared with the on resistance value of the transistor thus the reduction in balance speed due to the use of stacked polysilicon is not so significant accordingly by disposing pdl in the dummy word line region the layout size can be reduced by the pdl area in the conventional layout for example when applied to a 16 mbit product manufactured by the assignee of this application the chip size can be reduced by about 2 to 3 meanwhile a reduction in balance speed may be also concerned because a transistor that corresponds to the transistor a in fig2 for bit line balancing is not provided in the semiconductor storage of this embodiment however by disposing pdl which was disposed only on one side of the bit line on both sides of the bit line a delay due to bit line resistance and capacitance can be reduced as a result a same performance as the conventional semiconductor storage can be obtained a semiconductor storage in the second.