of the number of nodes with the timing analysis shown in fig8 the fast static timing analysis is first made to divide object paths into conformable paths nonconformable paths and undecided paths after that the precise dynamic timing analysis is made to allow the undecided paths fall into either conformable paths or nonconformable paths thereby the time required for timing analysis can be reduced and precise analysis can be made such timing analysis for semiconductor integrated circuits allows the effect of coupling capacitance to be reflected precisely and a margin requirement is also eliminated further if the timing analysis shows that the constraint is satisfied then it is guaranteed that it will be satisfied even on actual chips according to the first embodiment as described above the time required for timing analysis can be reduced and precision analysis can be made by using the dynamic timing analysis only for paths that cannot be distinguished by the static timing analysis that is the first embodiment allows precision timing analysis to be made in a short period of time next a timing analysis method for semiconductor integrated circuits according to a second embodiment of the present invention will be described the second embodiment is directed to a timing analysis method for a hold constraint fig1 is a flowchart for the timing analysis procedure of the second embodiment as with the first embodiment timing analysis is made of the circuit shown in fig9 in accordance with the following procedure first the sum cc i of the coupling capacitances of the node n i which is an.