below may be included in radio circuitry 330 in other embodiments the jitter buffer implementation may be distributed over multiple components within ue 106 for example processor 302 radio circuitry 330 memory 306 rom 350 and or mmu 340 may execute all or portions of various tasks associated with the jitter buffer implementation generally processor 302 of the ue device 106 may implement part or all of the methods described herein e g by executing program instructions stored on a memory medium e g a non transitory computer readable memory medium in other embodiments processor 302 may be a programmable hardware element such as an fpga field programmable gate array or as an asic application specific integrated circuit fig4 illustrates an exemplary block diagram of a base station 102 it is noted that the base station of fig4 is merely one example of a possible base station as shown the base station 102 may include processor s 404 which may execute program instructions for the base station 102 the processor s 404 may also be coupled to memory management unit mmu 440 which may receive addresses from the processor s 404 and translate those addresses to locations in memory e g memory 460 and read only memory rom 450 or to other circuits or devices the base station 102 may include at least one network port 470 the network port 470 may couple to a telephone network and provide a plurality of devices such as ue devices 106 access to the telephone network as described above in fig1 and 2 the network port 470 or an additional network port may also or alternatively couple to a cellular network e g a core.