for proper operation of the main circuits 16 as is well known the design and operation of the main circuits 16 are well known in the art and are not further described herein referring now to fig2 there is shown an embodiment partly in schematic circuit form and partly in block form of the power on detection circuitry 12 of fig1 circuity 12 comprises p channel field effect transistors fets 32 and 38 n channel field effect transistors fets 30 and 40 a resistor 34 a capacitor 36 typically a parasitic capacitor associated with resistor 34 and the transistors 30 32 38 and 40 a wave shaper unit 42 shown in block diagram a pulse delay unit 44 shown in block diagram and a buffer inverter unit 46 shown in block diagram transistors 30 32 38 and 40 are typically of the metal oxide silicon mos type and may denoted as mosfets each transistor has a gate and first and second output terminals the combination of transistors 32 38 and 40 and resistor 34 may be denoted as voltage pulse generating means transistor 30 may be denoted as voltage lowering means resistor 34 may be denoted a resistive means and capacitor 36 may be denoted as capacitance means in a p channel transistor current flows from the source to the drain thus the source is the first output terminal and the drain is the second output terminal in an n channel transistor the current flows from the drain to the source and thus the first output terminal is the drain and the second output terminal is the source the wave shaper unit 42 pulse delay unit 44.