base memory controller 19 for staging jobs to be scheduled and for high speed input output buffering of jobs in execution and the coordinator 21 used to synchronize the processor array 11 and coordinate data flow through the connection network 15 in operation all data and program for a run is first loaded into the base memory 17 prior to the beginning of the run this loading is initiated by a support processor system not shown which functions as a user and input output interface to transfer under control of a user data and programs from a secondary storage file memory not shown the use of such a support processor system is detailed in the above cited u s pat nos 3 537 074 and 4 101 960 as the run is initiated the data base memory controller 19 transfers code files from the data base memory 17 to the extended memory module array 13 then the data base memory controller 19 transfers the processor array 11 code files thereto and the necessary job data to the extended memory module array 13 once initiated the present invention is capable of parallel execution in a manner similar to the lock step array machines disclosed in u s pat nos 3 537 074 and 4 101 960 simple programs having a copy thereof resident in each processor of the processor array 11 with no data dependent branching can be so executed however the present invention is not limited to parallel mode.