built on the same semiconductor of a multi core x86 processor for direct drop in in the cpu socket of a standard x86 computer board in this embodiment the heterogeneous computer system 300 is itself a standard x86 architecture which by itself constitutes a complete x86 computer with its x86 cpu 344 and the supporting x86 chipset 362 the x86 cpu 344 is a variant to its conventional counterpart it consists essentially on the same semiconductor die of an x86 performance processor for example the latest multi core x86 320 a hypervising arm or low end x86 core 310 and the bridge logic 340 to bridge the hypervisor to the performance core via the front side bus 334 fig4 schematically outlines the block diagram of another implementation of the heterogeneous computer system of the present invention that has a reduced power x86 core serving as the hypervisor processor on the same semiconductor of a multi core x86 processor for direct drop in in the cpu socket of a standard x86 computer board in this embodiment the heterogeneous computer system 400 is itself a standard x86 architecture that constitutes a complete x86 computer with its x86 cpu 446 and the supporting x86 chipset 462 the x86 cpu 446 is another variant to the conventional counterpart it consists essentially on the same semiconductor die of x86 performance processor cores 421 and 422 and a hypervising reduced power x86 core 410 no bridge logic is necessary as the hypervisor core 410 implements a reduced instruction set of the performance cores 421 and 422 and shares the same internal bus the hypervisor equipped performance processor.