cycle time and results in improved processor efficiency application_number US 83654101 A description the present invention is described in the environment of a processor that maps instructions of a first instruction set to a predetermined instruction width format u201c piwf u201d that is sufficiently wide to and does accommodate two or more instruction sets in a first embodiment the piwf is wider than the instruction width formats of the plurality of instructions sets supported by the host computer system the extra width may be used to support functionality that is unique and exclusive to each respective instruction set that is a first instruction set may have unique functionality not available in one or more other instruction sets further a second instruction set may have unique functionality that is not available in the first instruction set in a second embodiment the piwf is the same width as at least one of the instruction width formats of the instruction sets supported by the computer system in this embodiment the piwf could be identical to one of the supported instruction sets for example if one of the supported instruction sets has an instruction width of 32 bits the piwf would be identical to such set if the piwf also had a width of 32 bits and had the same encoding with no additions or deletions as the supported instruction set the piwf is a format.