of the pll with the and 36 permits the pll to continue operation and therefore provides a way to restart the chip clock waiting to wait for the pll to regain lock reprogramming the frequency divider circuits in the pll to reduce the output frequency will reduce the power consumption in the chip logic the chip logic will then function at lowered performance levels the chip logic can also signal that it needs a higher frequency in this case the power management circuit can dynamically reprogram the frequency divider circuits in the pll to increase the frequency provided the power dissipation as measured by the temperature sensor is in an acceptable range the chip logic will then function but at raised performance levels refer now to fig3 which is a flow diagram of a method of dynamically maintaining chip temperatures in accordance with the present invention a temperature threshold level t is chosen for normal operation of the chip logic 52 the chip temperature is sensed 54 if the chip temperature t is greater than the threshold t the flow proceeds to decision block 58 the chip logic generates a chip status signal to the power management circuit that indicates that the chip is or is not in stop clock mode if in stop clock.