are to be located in accordance with the invention this step also defines part of the voltage distributing region for the transistor the thickness of the oxide is normally between 4000 and 15000 a u 0024 fig6 is a top view of the substrate 1 after it has been oxidized i e the same step as illustrated in fig5 the little square 13 to the left indicates where a contact to the n well is to be defined 0025 fig7 illustrates the step where gate regions 8 9 and 10 have been defined for the high voltage mos transistor the low voltage nmos transistor and the low voltage pmos transistor respectively to define the gate regions the portions 6 of the protective film as illustrated in fig5 have been removed and a thin gate oxide not shown has been produced on the substrate 1 on the gate oxide not shown a layer of polycrystalline silicon poly si has been deposited and patterned to define the gate regions 8 9 and 10 as apparent from fig7 the gate region 8 for the high voltage mos transistor extends partly on the oxide 7 above the n well 4 a normal thickness for the poly si layer is between 200 and 600 nm in accordance with the invention the same gate structure i e gate material and underlying gate oxide that is used for the low voltage pmos transistor is used also for the high voltage mos transistor further the doping concentration within the region where the channel for the high voltage mos transistor is to be located looks identical to the channel.