view along the line 4 of fig3 fig5 illustrates a side view of the resultant structure following the deposition of a sacrificial layer 502 over the semiconductor fins 302 and exposed portions of the substrate 202 the sacrificial layer 502 may include for example a flowable oxide or similar material that is deposited over the semiconductor fins 302 and exposed portions of the substrate 202 and subsequently planarized using for example a chemical mechanical polishing cmp method that removes portions of the sacrificial layer 502 to expose portions of the hardmask layer 206 the planarization process may be controlled such that the planarization process ceases when the hardmask layer 206 material is exposed fig6 illustrates a top view following the patterning of a photolithographic resist resist 602 over portions of the hardmask layer 206 and the sacrificial layer 502 the resist 602 defines the semiconductor fins 302 a that will be removed to isolate multi fet devices that will be formed in subsequent processes described below in the illustrated embodiment the semiconductor fins 302 have distal ends 601 that connect adjacent semiconductor fins 302 in the illustrated embodiment the distal ends 601 remain exposed such that portions of the distal ends 601 may be removed to isolate each semiconductor fin 302 from adjacent semiconductor fins 302 fig7 illustrates a cut away view along the.