to improve modulation efficiency for chip to chip interconnects modulation objects that are integer multiples of a fundamental time unit are used to populate a symbol period that is also an integer multiple of the ftu a possible symbol set is established as the set in which the modulation object occupies every possible combination of slots within the symbol period by permitting the modulation object to overlap positions in different symbols of the set greater modulation efficiency is achieved application_number US 81314304 A description one embodiment of the invention provides an improved modulation technique premised on multiples of a fundamental unit of time ftu selection of the ftu size may be based on the minimum phase slot size for the system in equalized channels jitter and other noise factors over manufacturing variations become the limiting factor on slot size that can be resolved for a given bit error rate ber in this scheme data is encoded in symbols in relation to the timing relationship of modulation objects within the symbol in an embodiment a symbol period u201c s u201d is an integer u201c n u201d multiple of the ftu the symbol period may be selected in accordance with latency complexity and timing resolution possible with the timing constraints in the system employed the delay lock loops dll phase lock loops pll delay elements process employed design of rf channel manufacturing variations and feature size all effect the desired symbol period in this description a phase slot for phase modulation within the.