forms the emitter of transistor t 1 u03c0 trough 30 is connected to external emitter terminal e over one or more terminals three in this example designed as p regions there is a good ohmic connection over the p regions fig2 b shows a schematic sectional diagram through monolithically integrated output stage 10 according to another embodiment of the present invention the same parts as in fig2 a are labeled with the same notation and will not be explained again here in this embodiment external terminal k and resistor r 6 are omitted output transistor t 11 transistors t 10 and t 12 as well as resistor r 11 are integrated here into a common u03c0 trough 30 switching stage t 1 is located in a separate u03c0 trough 31 transistor t 12 is defined by an n region forming the collector a u03bd region surrounding the n region and forming the emitter and the base being formed by u03c0 trough 30 provision is also made for a u03bd region that forms resistor r 11 u03c0 trough 30 is in turn connected to external emitter terminal e across one or more terminals two in this example designed as p regions transistor t 1 here is part of a triple darlington with transistors t 1 t 2 and t 3 the u03bd region here is connected to the base of transistor t 2 not shown across an n region emitter t 1 u03c0 trough 31 forms the base of transistor t 1 which is connected to control logic 18 across a p region fig2 a and 2 b also show switching stage t 3 of power switching transistor 12 which is located in a separate u03c0 trough 32 u03c0 trough 32 forms the.