and 354b are electrically connected to the bit line cbl1 39 in the state that the access transistor 311b and the reference cell access transistors 351b and 353b are turned on when the bit line equalizer enable signal req1 is activated by a 34 high 34 level an nmos transistor 316b is turned on to electrically connect the bit lines cbl1 and cbl2 34 here the bit lines cbl1 and cbl2 34 act as inversion data lines which in combination have approximately twice the capacitance as the bit line bl1 the bit line cbl2 39 also acts as a plate line also the other bit line equalizer enable signal req0 is maintained at a low level so that bit line cbl0 is disconnected from bit line cbl1 a plate voltage is then applied to the bit lines bl2 and cbl2 39 determined as the plate lines so that a voltage level corresponding to the data stored in the ferroelectric capacitor 312b appears on the bit line bl1 because of the plate voltage an intermediate level voltage appears on the inversion data line cbl1 subsequently the voltage applied to the bit lines bl2 and cbl2 39 decreases to a ground level then a bit line equalizer enable signal.