logic 34 1 34 trigger signal 32a n each of the remaining decoders outputs a trigger signal having a logic level that disables the corresponding timer circuit when a timer circuit is disabled the node corresponding to that timer circuit is coupled through the timer circuit to electrical ground each timer circuit 24a n has a trigger input 34a n discharge terminal 36a n external capacitor terminal 38a n and output 40a n respectively in a preferred embodiment each timer circuit is a cmos type timer each discharge terminal and external capacitor terminal are coupled to a corresponding node for example discharge terminal 36a and external capacitor terminal 38a are coupled to node 1 each resistor 28a n is coupled between the supply voltage v cc and a node in a preferred embodiment v cc is about 15 volts d c and each resistor has a resistance between about 100 k u03c9 and 2m u03c9 ohms the actual resistance of each resistor 28a n depends on the size of the circuit board being tested and the number of nodes and probes utilized in system 10 each resistor 28a n is coupled to net1 n respectively through probes p 1 n respectively the capacitance of each net c net1 n and resistors 28a n respectively form a plurality of r c resistor capacitor timing circuits since each discharge terminal 36a n and external capacitor terminal 38a n of each timer 24a n respectively is coupled to a node 1 n respectively each r c timing circuit becomes the r c timing circuit for a corresponding timer circuit 24a when each trigger input 34a n of timer circuits 24a n respectively receives a trigger signal 32a n respectively a pulse 27.