to be read is continually outputted until the rise of the next subsequent u03c61 pulse at which time the next address in the program sequence will be outputted by the mpu each time an address is sent to the memory or peripheral circuit the addressed unit will transmit the data back to the mpu after a predetermined access time which is dependent on the speed of the memory used in the addressed unit until the mpu transmits another address the master clock cycle however must be long enough such that the memory access time plus the mpu set up time is of sufficient length to permit the mpu to latch the data at the end or the fall of the u03c62 pulse more particularly to permit the mpu to latch the data at the end of the u03c62 pulse the data must be available to the mpu a predetermined period of time before latching is to occur which predetermined time period is dependent on the make and model of mpu used for example for the motorola m6800 the predetermined time period is approximately 100 nanoseconds fig2 illustrates the timing of a write cycle which has the same basic procedure as for the read cycle of fig1 except that during the u03c62 pulse the mpu is instructed to.