metal conductors 186 and contacts 187 is basically the same as in fig3 c of the parent application however using this technique as i did on the chip of the parent application on the chip 100 of the present invention would have resulted in a much wider sum of minterm region 116b than i actually achieved because of the much higher number of sum of minterm transfer signals that are required for the sixteen bit microprocessor chip of the present invention furthermore i was able to arrive at a reasonably optimum layout of the sum of minterm region in the parent application only after three very laborious trial layouts in which i followed the approach described in the above referenced parent application to positioning the minterm summing horizontal metal lines 186 in such a way as to provide gaps through which diffused and or polycrystalline silicon conductors could be 34 dropped 34 down into the register transfer logic where the resulting sum of minterm transfer signals were needed to avoid utilization of an excessive amount of chip surface area for routing such signals however the method of arranging the relative positions of the horizontal metal sum of minterm lines 186 is different than in the above referenced parent application of course the relative placement of the horizontal metal lines 186 determines the placement of all n channel mosfets connected to a particular horizontal line and hence determines how far down into sum of minterm region 116b the vertical poly polycrystalline silicon lines.