sd and variable resistor vr connected in series the anode of the diode sd is connected to a bit line bl and the cathode is connected to a word line wl through the variable resistor vr an end of each bit line bl is connected to the column control circuit 2 while an end of each word line wl is connected to the row control circuit 3 the memory cell mc may be selected individually or may be of a type in which data of a plurality of memory cells mc leading to a selected word line wl 1 is read out collectively the memory cell array 1 may be so constructed that the polarity of the diode sd is reversed so that a current flows from the word line wl side to a bit line bl side next an operation of the nonvolatile semiconductor memory having such a structure will be described the resistance values of the variable resistor vr which constitutes the memory cell mc are distributed in a high resistance range of 100 k u03c9 to 1 m u03c9 in an erase state and in a low resistance range of 1 k u03c9 to 10 k u03c9 in a write program state erase of data is carried out by reset operation of feeding a current of 1 u03bca to 10 u03bca for only 200 ns to 1 u03bcs by applying an erase voltage vera of for example about 0 7 v to the variable resistor vr data write program to the variable resistor vr is a procedure of shifting the resistance value of the variable.