circuit 80 the node n10 is at the high level the node n11 is at the low level the nmos transistor 81 is in the off state the nmos transistor 82 is in the on state and the node n13 becomes the low level as shown in fig7 when the node n12 becomes high and the node 13 becomes low the nmos transistor 121 1 is turned on and the nmos transistor 122 1 is turned off the drain of the nmos transistor 121 is being supplied with the high level 5 v predecode signal pr11 so that the selected word line 51 1 begins being driven to the high level by the nmos transistor 121 1 when the node n12 is driven to 4 6 v the word line 51 1 is driven to 3 6 v the difference is the threshold 1 0 v of the nmos transistor 121 1 with the back bias effect next in the delay circuit 90 when the node n12 rises to the high level and the nmos transistor 92 is turned on the node n14 that has been driven to 0 v by the nmos transistor 91 when unselected rises to a higher voltage the speed at which the voltage rises is dependent on the capacitance of the capacitor 98 and the conductance of the nmos transistor 95 when the voltage rising speed is set low the voltage on the node n14 gradually rises to.