resulting in the structure shown in fig6 c and 7c nitride layer 215 and pad oxide layer 225 are then stripped away a gate oxide layer 235 typically silicon dioxide is thermally grown along the upper surface of p well region 214 in active region 220 until gate oxide layer 235 has a thickness of approximately 80 200 u00e5 a layer of gate electrode material is deposited over gate oxide layer 235 the gate electrode material is conductive material such as n type polysilicon having a sheet resistance of 35 ohms square and a thickness of approximately 3000 4000 u00e5 a second photoresist mask 217 is then formed over the layer of gate electrode material an etch is performed to remove the portions of the layer of gate electrode material not covered by mask 217 in this manner the second photoresist mask 217 defines gate electrode 210 as illustrated in fig6 d and 7d the portions of gate oxide layer 235 not covered by gate electrode 210 are typically left substantially intact as shown in fig6 d in a typical embodiment the portion gate oxide layer 235 covered by gate electrode 210 is approximately 50 u00e5 thicker than the portions of gate oxide layer 235 which are not covered by gate electrode 210 gate electrode 210 is situated over the upper surface of active region 220 such that gate electrode 210 is laterally separately from sides 221a 221d of boundary 221 which defines active region 220 referring now to fig6 e and 7e photoresist mask 217 is stripped and source drain photoresist mask 290 is formed on.