approximately 1 part in 256 or about 0 4 to insure both adequate resolution and dynamic range the clock frequency i e sampling rate must be properly chosen if too fast it will not span the full range of times needed for a sense amplifier to flip for all possible stored memory cell data values before hitting the maximum count while if too slow the result will be poor resolution and the risk of inability to discrinate between neighboring states in order to provide some relationship with the memory cells 39 drive characteristics in one embodiment the frequency of clock 205 is governed by a memory cell or group of memory cells set at an appropriate drive level in this way clock 205 tracks process variation and operating conditions e g voltage and temperature setting up the optimum clocking rate to span the cell 39 s dynamic range and associated memory states although this embodiment is relatively simple and effective it does have limitations by nature of its being dynamic time constants associated with word line and or bit line delays and their variations contribute both relative and absolute error for example if word line rc time constants are long relative to ramp or step interval times.