of control gate mask pr2 leaving the control gate electrodes cg exposed then again referring to fig1 l and 2l a spacer glass layer 34 is formed over the entire device 10 covering the drain regions d the exposed sidewalls of the ono layer 30 and the control gates cg a conventional teos process can be employed to form the glass spacer layer finally the spacer layer 34 is etched back to form the spacers 34 adjacent to the sidewalls of the ono layer 20 and the control gate electrodes cg in the conventional manner fig3 shows a plan sectional view of the device 10 of fig1 l and 2l as well as fig4 and 5 taken along line 3 3 39 in fig4 two horizontal rows r1 and r2 of three fet devices each are shown in three vertical columns c1 c2 and c3 with drain regions d located between the trenches indicated by the nested squares in the center square of which are the sections of the control gates cg surrounded by the ono regions 30 extending vertically are the portions of the control gates cg which are shown in phantom as they have been cut away by the section which looks below the surface of the device 10 with the tops of the control gates cut away to shown the ono layers etc the spacers 34 are shown on the sidewalls of the control gates cg fig4 shows a sectional view of the device 10 of fig3 taken along line 4 4 39 in fig3 showing the flow f through the channel region ch between the source region s and the drain regions d it can be seen that there is a single buried source.