the same principle as described above as a result u201c 1 u201d is stored in the memory corresponding to the state s 0 u201c 1 u201d is stored in the memory corresponding to the memory state s 1 u201c 0 u201d is stored in the memory corresponding to the state s 2 and u201c 1 u201d is stored in the memory corresponding to the state s 3 as shown in fig7 e fourth column the data at the time point t 3 are shifted in accordance with the data at the time point t 5 as shown in the third column in fig7 e u201c 2 u201d is stored in all the memories corresponding to the states s 0 to s 3 when the data at the time point t 2 are shifted in accordance with the data at the time point t 5 u201c 3 u201d is stored in all the memories corresponding to the states s 0 to s 3 as shown in the second column in fig7 e when the data at the time point t 1 are shifted in accordance with the data at the time point t 5 u201c 1 u201d is stored in all the memories corresponding to the states s 0 to s 3 as shown in the first column in fig7 e in this manner the control circuit 6 controls the data in the memory 5 in accordance with the state transition as is apparent from fig7 e at the time point t 5 the contents of data stored in the memory before the time point t 3 match in the memories corresponding to all the states more specifically at the time point.