is connected to the gate of the pmos element 54 the nmos side gate of the transfer gate 44 the nmos side gate of the transfer gate 45 and the pmos side gate of the transfer gate 48 in the above operational explanations referring to fig2 while fuse 33 is disconnected and the input of input terminal 30 has a high level it is necessary to maintain the level of the data input of flip flop circuit 35 to be 34 high 34 during a fixed time by keeping capacity from the output of inverter 52 to the input of flip flop circuit 35 however if a long fixed time is necessary it may be difficult to maintain the high level because of leakage or the like and in the worst case the voltage may be lowered to the intermediate level if such an input signal is applied to an inverter as the input stage of a flip flop circuit a great deal of current passes through the line therefore in the second embodiment the inverter at the input stage and the transfer gate shown in fig1 are replaced with clocked inverter 39 shown in fig3 which operates in synchronism with the clock in this way a through current generated when input terminal 30 maintains the high level for a long time is prevented next the third embodiment of the present invention will be explained fig4 is a circuit diagram showing the structure of a semiconductor integrated circuit of the third embodiment according to the present invention in which a.