and robust against any activity on the data lines the read path reverses the conventional usage of the multiplexer and uses one of the nominal inputs of a multiplexer as the output of the memory cell and similarly drives the ram cell onto the nominal output of the multiplexer in order to reduce the loading on the read bit line and eliminate wasted power due to unnecessary activity inside the memory cell similarly the write path uses full cmos muxes to ensure a robust write an alternative embodiment of an hle 10 u2032 is shown in fig8 a single hle 10 u2032 is mask programmable to provide one ram cell hle 10 u2032 includes first and second multiplexers 560 a and 560 b first and second inverters 570 a and 570 b and two input nand gate 580 each of multiplexers 560 has two selectable inputs 562 and 564 and a selection control input 566 for controlling which of the selectable inputs is connected to an output 568 of the multiplexer nand gate 580 can be operated as a third inverter e g by mask programmably connecting one of its inputs to a source of fixed logic 1 it will be appreciated that any circuit element that provides logic signal buffering including both inverters and logic gates can be used to provide a buffering function that is required in the core of the memory cell and the read line driver these will be referred to simply as u201c inverters u201d because current technology will provide logical inversion as well as the signal buffering aspect thus.