will be appreciated that such equalisation may additionally compensate for non ideal frequency dependent characteristics of the various electronic and opto electronic components of the transmitter 102 and receiver 104 the resulting equalised symbol values are output along parallel signal lines 138 to demapping units 140 which correspond with mapping units 110 the demapping units 140 receive the equalised symbol values and generate corresponding bits of the digital information the resulting decoded information is output along parallel signal lines 142 and if the levels of noise and or distortion within the system 100 are not excessively high then the output digital information bits on signal lines 142 will generally match the original digital information bits input at signal lines 108 it will of course be appreciated by those skilled in the art that errors may be introduced due to noise and or distortion in any communications system and accordingly that a zero error rate in the transmitted information bits may not be achievable however it will also be understood that additional means may be employed including error detection and error correction codes inserted within the digital information in order to detect and or correct such bit errors it will be appreciated from the foregoing discussion that adc 128 serial to parallel converter 130 dft 132 and equaliser bank 136 in combination provide means for performing a frequency domain equalisation of the received signal in order.