on the transmit chip 10 the receiver 32 on the receive chip 14 receives through its floating input nodes 26 a 26 b the signals corresponding to datap datan and outputs the corresponding signal rxdata the rxdata signal is coupled back to the analyzer 40 which determines if the received signal rxdata is the same as the data datap datan it transmitted the data are usually compared bit by bit any bit received as the wrong polarity is counted as an error over a long data stream the analyzer determines a bit error rate ber communication systems are typically designed to accommodate a maximum bit error rate if the ber is too high the system is not working acceptably and must be redesigned or adjusted the communication system analyzer or auxiliary equipment of this embodiment of the invention also provides the capability of controlling the biasing voltages produced by two dc power supplies 42 a 42 b producing the bias supply voltages biasp biasn of fig2 according to an embodiment of the invention the bit error rate is measured for different values of the bias supply voltages biasp biasn to determine the voltage margin beyond which the ber exceeds a predetermined limit during voltage margin testing a differential voltage may be introduced by shifting biasp and biasn in opposite directions from their design values or by a mixed common mode and differential voltage biasing in which only one of biasp or biasn is shifted shifting only one bias voltage is simpler to.