or with different numerals referring to fig2 a semiconductor wafer fragment 10 a is illustrated at a preliminary step of a process of the present invention wafer fragment 10 a comprises a semiconductive material 12 a field oxide regions 14 a and a thin gate oxide layer 16 a over gate oxide layer 16 a is formed polysilicon layer 18 a silicide layer 20 a and silicon oxide layer 22 a silicide layer 20 a comprises a refractory metal silicide such as tungsten silicide and polysilicon layer 18 a typically comprises polysilicon doped with a conductivity enhancing dopant layers 16 a 18 a 20 a and 22 a can be formed by conventional methods referring next to fig3 polysilicon layer 18 a silicide layer 20 a and silicon oxide layer 22 a are etched to form wordlines 24 a and 26 a such etching can be accomplished by conventional methods between wordlines 24 a and 26 a are defined electrical node locations 25 a 27 a and 29 a with wordlines 26 a comprising transistor gates which electrically connect node locations 25 a 27 a and 29 a node locations 25 a 27 a and 29 a are diffusion regions formed within semiconductive material 12 a referring to fig4 and 5.