given as to how the sub array 5 having this configuration operates let us assume that the sub array 5 is in the inactive state i e the state where the pre charge is inactive and the word lines are not activated in this state the sub array 5 must reliably keep local bit line lbl at high level since the pre charge is inactive and the word lines are not activated local bit lines lbl and lbl are in the floating high state since in this case current leaks from local bit lines lbl and lbl to memory cells mc the potential levels of local bit lines lbl and lbl gradually decrease to prevent the sram 1 from malfunctioning local bit line lbl i e the local bit line connected to the read circuit 8 has only to maintain high level where leak current flows from local bit line lbl to memory cell mc in which case local bit line lbl is in the floating high state and the storage node n 1 is at low level leak current also flows from local bit line lbl to memory cell mc by way of nmos transistor 30 in other words leak current flows from local bit line lbl not only when storage nodes n 2 of memory cells mc are at low level but also when storage nodes n 1 of memory cells mc are at low level since memory cell mc includes nmos transistor 30 as described above local bit line lbl becomes low in potential level before local bit line lbl does because of the cross.