bit serial representation and are converted to parallel representation in a shift register which in a known manner acts as a series to parallel converter the information in parallel representation in code 1 is then used to address a read only memory rom in the rom the identically weighted words to correspond to the extent of code 1 are held ready in code 2 that is as shown from a word in code 1 of bits i1 i4 the rom produces an output word with bits i1 i8 where in the sum of the 34 0 34 and 34 1 34 values is the same according to fig5 which is a basic block circuit diagram for a code converter of another second type after the series to parallel conversion of the data d in the shift register the data bits are code converted into code 2 by formation of their complement in the illustrated example the outputs i1 i4 of the shift register are supplemented via respective exclusive or circuits to form the work i1 i1 i2 i2 i3 i3 i4 i4 in this way the number of zeros and the number of ones is again balanced fig6 8 show the principle and operation of code converters according to the invention of still another type in addition to coding the words as in the two previously described code converter embodiments or types the type or embodiment of the code converter.