1 and q 2 and to an output of the over current detection device 22 fig3 6 are schematic diagrams showing different embodiments of the fault protection device 20 a in each of the embodiments the configuration and operation of the gate control device 24 absent the influence of the output of the over current detection device 22 is identical the gate control device 24 includes an oring controller 26 such as the max8535 controller from maxim integrated products of sunnyvale calif the gate output of the controller 26 is coupled to the gate terminals of the mosfets q 1 and q 2 through gate resistor rg for providing a gate voltage v g thereto the gate output is also coupled to ground through capacitor cg the input current pin cs of the controller 26 is connected to the common power bus v 1 and the vcc input is connected to the v 1 a power supply line under voltage protection pin uvp is coupled to the v 1 a power supply line through a voltage divider including resistors rx and ry and the timer pin is coupled to ground through resistor rt in operation the gate control device 24 determines when mosfets q 1 and q 2.