generating an error signal between a memorized speed and the actual speed receives the output of the circuit 1 for generating the speed responsive voltage through the resistor 21 when memorizing the vehicle speed as the set switch 33 closes the input of nand gate 29 which has been at 34 h 34 through the resistors 34 35 32 turns to 34 l 34 level as a result the output of nand gate 29 turns to 34 h 34 so that the gate of fet 25 will turn to 34 h 34 through the resistor 28 thus fet 25 becomes conductive so that a source voltage which is the voltage of bus 10 divided by the resistors 26 27 is applied to the capacitor 22 and the gate of fet 22 if this source voltage is defined as a reference voltage 34 c 34 a voltage 34 a c 34 determined by substracting the reference voltage 34 c 34 from a speed responsive voltage 34 a 34 is held by the memory capacitor 22 the gate voltage of fet 23 is held at 34 c 34 and this voltage is impedance converted and picked up as the source voltage of fet 23 connected with a source follower when the switch 33 is open the input of nand gate 29 becomes 34 h 34 and the output becomes 34 l 34 and thus the gate of.