the resolution of each stage of the delay line in addition the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line resulting in an overall decrease in the size of the ddll circuit application_number US 11017998 A description the present invention will be described as set forth in the preferred embodiments illustrated in fig4 8 other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention fig4 illustrates in schematic diagram form a delay line circuit 400 in accordance with the present invention a clik in signal is input at node 410 the delay circuit 400 of fig4 consists of a series of n delay stages each stage consisting of two nand gates and one inverter each stage is either an odd stage or an even stage depending upon its position in the line thus the first stage 401 is an even stage the second stage 411 is an odd stage a third stage not shown would be an even stage etc even stage 401 consists of nand gates 405 406 and inverter 407 nand gate 405 acts as a switch connecting together upper delay line 402 and lower delay line 403 the transistor gates of nand switch 405 become the load for the upper delay line 402 shift register 415 provides a signal to open or close nand switch 405 the delay of the lower delay line 403 slightly exceeds that of the upper delay line 402 this delay difference becomes the unit delay time of the delay line circuit 400 by reducing the.