leakage to chip vss is in the write circuitry advantageously either the vss write circuitry can be raised along with wl vss or sufficient isolation between bl and write vss is ensured as a further precaution the range of the bl voltage can be limited e g by diode connections the probability of upset will also be increased if there is a significant voltage difference between bit and bit bar to a cell with the bit lines floating a voltage differential between bit and bit bar will occur if the data stored is predominately 1 39 s or predominately 0 39 s in the associated column advantageously to avoid the possibility of a significant voltage differential on the bit lines bit and bit bar are connected to float together when in standby the connection of bit and bit bar in standby also decreases the possibility of either going below wl another possibility for cell upset occurs in the transition from standby to active the bit lines must be restored to precharge high before wl is enabled simulations show that bit line will float to near the array vss so as an alternative preferred embodiment to floating the bit lines switching the bit lines to.