the memory device use a greater or lesser number of dram die the dram die 20 22 24 26 are stacked with e g on top of a logic die 30 which serves as the interface with the processor 12 the logic die 30 can implement a variety of functions in the memory device 10 such as to limit the number of functions that are be implemented in the dram die 20 22 24 26 for example the logic die 30 may perform memory management functions such as power management and refresh of memory cells in the dram die 20 22 24 26 in some embodiments the logic die 30 may implement test and or repair capabilities and it may perform error checking and correcting u201c ecc u201d functions the dram die 20 22 24 26 are connected to each other and to the logic die 30 by a relatively wide bus 34 the bus 34 may be implemented with through silicon vias u201c tsvs u201d which comprise a large number of conductors extending through the dram die 20 22 24 26 at the same locations on the dram die and connect to respective conductors formed on the die 20 22 24 26 in one embodiment each of the dram die 20 22 24 26 are divided into 16 autonomous partitions each of which may contain 2 or 4 independent memory banks in such case the partitions of each die 20 22 24 26 that are stacked on top of each other may be independently accessed for read and write operations each set of 16 stacked partitions may be referred to as a u201c vault u201d thus the memory device.