the clock signal clk is input to both address decoders 4 and 6 and the register 8 further control signals of a not illustrated command etc are input to the two address decoders 4 and 6 the activation operation stop is controlled by this in the present embodiment as an example of the delay unit of the present invention for delaying the address designation by the address decoder 6 used only for data writing by a predetermined time a first in first out semiconductor memory 14 hereinafter referred to as fifo memory is connected to the input side of the address decoder 6 used only for writing the write decode unit of the present invention is constituted by this fifo memory 14 and the write only address decoder 6 the fifo memory 14 is configured with a predetermined number of unit memory stages of a predetermined number of bits to which at least address signals add can be connected together usually this unit memory stage is constituted by a shift register further the number of stages thereof is set to an extent that the expected maximum delay time is obtained in accordance with the operation method of the rmw read modify write in which the semiconductor memory device is used this fifo memory 14 is provided with a not illustrated pointer terminal a starting point write pointer p w of the unit memory stage for storing the address signal add and an ending point read pointer pr for outputting the address signal add to the write only address decoder 6 side can be freely set in accordance with the pointer signal input to this note that it is also possible to set one of either write pointer p w or the read pointer pr in the.