the two terminals of the third switch 1640 receives the third reference voltage vref particularly a first terminal 1641 of the third switch 1640 is electrically connected to the second terminal 1612 of the data switch 1610 a second terminal 1642 of the third switch 1640 receives the third reference voltage vref and a control terminal 1643 of the third switch 1640 receives an enabling signal ven accordingly the electrical connection between the first terminal 1641 and second terminal 1642 of the third switch 1640 is enabled according to the enabling signal ven fig2 is a time sequence diagram of the pixel circuit in fig1 according to an embodiment in the disclosure during the first time period p 1 in a working period pw the enabling signal ven is at a high voltage level vh and during the second time period p 2 in the working period pw the enabling signal ven is at a low voltage level vl thus the enabling switch 1300 and the third switch 1640 are off during the first time period p 1 in the working period pw but are on during the second time period p 2 following the first time period p 1 during the fifth time period p 5 the data reading signal sdata is at the low voltage level vl but during the working period pw except the fifth time period p 5 is at the.