formed in the first cap layer 310 and the first dielectric layer 308 by procedures such as the photolithograph process and the etching process as shown in fig1 the first base layer 306 is exposed at the bottom of the metal interconnection pattern 320 please refer to fig1 when the integrated circuit device 300 has failed an after etching inspection aei a reworking method provided by the present invention is performed first a protecting layer 322 is formed on the first cap layer 310 the protecting layer 322 can be a photoresist and is to be formed on the first cap layer 310 by a spin on coating method then an etching back process is performed to etch back the protecting layer 322 to be below an opening of the metal interconnection pattern 320 please refer to fig1 13 when a dry etching process 350 is performed to remove the first cap layer 310 the dry etching process 350 is performed having a high selectivity between the first cap layer 310 and the protecting layer 322 for example oxygen fluoroform ch 3 f and nitrogen with a preferred ratio of 1 12 24 can be introduced into the dry etching process 350 for serving as the reaction gases the dry etching process utilizing the above mentioned reaction gases has an etching rate for the first cap layer 310 which comprises sion of 45 a sec and an etching rate for the protecting layer.