such an apm solution is preferred because of its selectivity for titanium nitride against cobalt silicide and teos it is contemplated that the process of the present invention may be utilized for production of dram chips wherein the contact interfaces are used in the mos structures within a memory array of a dram chip such a mos structure 200 is illustrated in fig9 as a portion of a memory array in a dram chip the mos structure 200 comprises a semiconductor substrate 202 such as a lightly doped p type crystal silicon substrate which has been oxidized to form thick field oxide areas 204 and exposed to implantation processes to form drain regions 206 and source regions 208 transistor gate members 212 including a wordline 214 bounded by insulative material 216 are formed on the surface of the semiconductor substrate 202 and thick field oxide areas 204 a barrier layer 218 is disposed over the semiconductor substrate 202 the thick field oxide areas 204 and the transistor gate members 212 the barrier layer 218 has bitline contacts 222 contacting the source regions 208 for electrical communication with a bitline 224 and further has capacitor contacts 226 contacting the drain regions 206 for electrical communication with memory cell capacitors.