of the eighteenth inverter iv 18 and a fourteenth nand gate nd 14 which executes a logic operation for the output signal of the twelfth nand gate nd 12 and the output signal of the thirteenth nand gate nd 13 and outputs the third verification signal hit2 the fourth rupture address comparing section 540 includes a nineteenth inverter iv 19 which inverts the fourth rupture address signal ra lt 3 gt an twentieth inverter iv 20 which inverts the fourth failure address signal fa lt 3 gt a fifteenth nand gate nd 15 which executes a logic operation for the fourth rupture address signal ra lt 3 gt and the fourth failure address signal fa lt 3 gt a sixteenth nand gate nd 16 which executes a logic operation for the output signal of the nineteenth inverter iv 19 and the output signal of the twentieth inverter iv 20 and a seventeenth nand gate nd 17 which executes a logic operation for the output signal of the fifteenth nand gate nd 15 and the output signal of the sixteenth nand gate nd 16 and outputs the fourth verification signal hit3 the rupture verification unit 500 compares the failure address signals fa which indicate the address of the memory cell in which a bit failure occurred and rupture address signals ra which indicate a result of performing the fuse rupture operation for the memory cell in which the bit failure occurred and verifies whether the fuse rupture operation is properly performed the first rupture address comparing section 510 compares the first rupture address signal ra lt 0 gt with the first failure address signal fa lt 0 gt when the first rupture address signal ra lt 0 gt is inputted and verifies whether.