levels of a hierarchical memory arrangement the example shown in fig4 differs from the example shown in fig3 insofar as two decompression units 42 a and 42 b and two compression units 44 a and 44 b are provided the decompression unit 42 a and the compression unit 44 b are provided on chip while the compression unit 44 a and the decompression unit 42 b can be provided off chip this arrangement allows data to be compressed in either direction of data flow as appropriate for example it is envisaged that data may be held in the on chip caches 40 in compressed form and decompressed before storage in the main memory fig5 shows a further arrangement in this example a processor chip 30 includes a number of processor cores 32 as described above in relation to fig3 and 4 the hierarchical memory in this example includes two cache levels thus there are provided a plurality of l1 caches 40 a and an l2 cache 40 b these two cache levels are connected by a series of data buses shown in fig5 in the form of arrows in between the two memory levels are provided a decompression unit 42 and a compression unit 44 it is noted that this embodiment is implemented on a processor chip 30 there being no.