is accomplished as follows the pipe latches 56 allow data to be stored in the event of fast data or a slow clock generally the number of latches needed is equivalent to the number of latency stages to be supported each time a read is performed a count signal one of these is shown in fig5 is delayed asynchronously by the count delay element 66 and clocked by the control signal for the last stage in this case iodb_read into a clock synchronizing latch 68 this time delayed count signal generates latch_en which determines which of the latches 56 the data from rdbamp 54 is to be stored in furthermore the count signal is also delayed by the appropriate number of clock cycles as determined by the current cas latency to which the chip is programmed this clock delayed count signal shown as qen_rise in fig5 controls which of the latches 56 has its output enabled to output data to the output buffer 58 once count has been set after the delay through count delay circuitry 66 a cnt_del signal is generated which is combined in the clock synchronizing latch 68 with the iodb_readx signal to generate the latch_enx signal after the predetermined clock delay in the pipe delay circuit to qen_risex is asserted allowing output form the latch containing the data for the appropriate clock cycle the latches 56 work as a fifo register with the first data input to one of the set of latches 56 being the first data to be output from the set of latches thus from the above description it may be seen that the latches in the read path segment the path into latency stages of.