the section shown in fig1 d first the structure shown in fig6 a to 63 d is obtained by the manufacturing method described with reference to fig3 a to 7 d and fig1 a to 25 d next as shown in fig6 a to 64 d an extra metal layer 21 is etched to form a slit 33 in the extra metal layer 21 the slit 33 is similar to the slit 33 shown in fig5 a to 52 d the slit 33 extends in the same direction as that of e g a bit line 13 1 and serves as an isolation region for sequentially isolating the intracell local interconnection 21 1 to be formed later along the direction in which e g a read word line 4 extends as shown in fig6 a to 65 d an insulating material e g sio 2 is deposited on the structure shown in fig6 a to 64 d to form a sixth dielectric interlayer 22 an opening that reaches an intra peripheral circuit via 13 3 is formed in the sixth dielectric interlayer 22 and fifth dielectric interlayer 19 the opening is filled with a conductive material e g a metal such as tungsten to form a third metal layer second metal layer contact 23 as shown in fig6 a to 66 d a conductive material e g alcu or cu is deposited on the structure shown in fig6 a to 65 d to form a third metal layer 24 next a conductive yoke material is deposited on the third metal layer 24 to form a conductive yoke layer 27 as.