parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored application_number US 43086706 A description several embodiments of the invention will now be described with reference to the accompanying drawings however the present invention is not limited to only the illustrated embodiments rather the embodiments are presented as teaching examples a nand flash memory device according to one embodiment of the invention is adapted to generate an error detection code edc during a copy back program operation and is further adapted to perform an error detecting operation additionally the nand flash memory device performs a data reloading operation during a copy back program operation the error detecting operation and the data reloading operation will be described with reference to the exemplary block diagrams shown in fig1 and 2 fig1 is a block diagram illustrating an exemplary execution of an error detecting operation adapted for use in a nand flash memory device according to an embodiment of the invention referring to fig1 the exemplary nand flash memory device includes a cell array 110 a page buffer 120.