low level output is obtained when the biased signal biasa is greater than the threshold value vth the output is supplied to the mismatch detecting circuit 22 as an individual reception signal rx 1 incidentally the threshold values vth of the comparators 20 21 are the same to each other in this embodiment however the values may be different the mismatch detecting circuit 22 reads in phase with a sampling clock each of the reception signals rx 0 rx 1 of the comparators 19 20 the mismatch detecting circuit 22 provides a low level output when the levels of the read reception signals rx 0 rx 1 coincide with each other on the other hand when the levels of the reception signals rx 0 rx 1 do not coincide with each other the mismatch detecting circuit 22 provides a high level output that shows abnormality the sampling clock is generated in accordance with the reception signal rx 0 for example the sampling clock is generated after a delay of a predetermined time from the rising edge of the reception signal rx 0 the predetermined time is shorter than the time from the rising edge to the falling edge of the reception signal rx 0 the counter 31 counts the rising edge of the high level outputs from the mismatch detecting circuit 22 when a predetermined count value has been reached for example 5 the counter 31 generates a fault detection signal to indicate that a fault has occurred on the transmission line 1 likewise the comparator 21 compares the biased signal biasb with the threshold value vth a low level output is obtained when the biased signal biasb is equal to or less than the threshold value vth whereas a.