o devices 17 or to processors if the interconnect is at the root of the interconnection tree the memory port 6 may be used to attach an optional cache 8 or to connect memory 9 when the interconnect is the root of the interconnection tree fig6 shows a multi level hierarchical tree topology where shared buses 16 are used to connect the different levels of interconnects when shared buses 16 are used between the levels of the interconnects the tree can support more processors for a given number of interconnection levels fig6 also shows the use of shared caches where pairs of processors are attached to each set of caches c1 and c2 fig7 shows a ring of trees topology where point to point links are used in the tree to connect interconnects 1 13 1 14 and 1 15 with a single ring trees can exist above each of these interconnects 1 13 1 14 and 1 15 that are in the ring system memory 9 may either be attached to multiple interconnects in the ring as shown here or may all be attached to a single interconnect in the ring fig8 shows a two dimensional mesh network where longitudinal links and latitudinal links are used to connect the set of interconnects 1 for the two dimensional mesh network.