52 high density p type source and drain impurity regions on each side of the pmos gate structure 44b and with a portion thereof formed under the second sidewalls 50 of the pmos gate structure 44b referring to fig3 f a metal layer including e g ti or co is deposited over the semiconductor substrate 41 subsequently a rapid thermal annealing rta process is performed on the semiconductor device the rta is performed preferably at temperatures ranging from about 950 u00b0 c to 1050 u00b0 c the rta process causes the boron b in the first sidewalls 47 which include a boron silicate glass bsg of the nmos gate structure 44a and the pmos gate structure 44b to diffuse into the semiconductor substrate 41 the diffused b forms p halo impurity regions 54 low density p type halo impurity regions in the nmos region and p low density ld regions 55 low density p type impurity regions in the pmos region the p halo impurity regions 54 are formed adjacent to each of the n ld regions 46 formed under the nmos gate structure 44a the p ld regions 55 are formed adjacent to each of the p s d regions 52 with a portion thereof formed under the first sidewalls 47 of the pmos gate structure 44b the rta process also causes the deposited metal layer to form a silicide film 53 on the nmos gate structure 44a the pmos gate structure 44b the n s d regions 49 and the p s d regions 52 as a result of the above fabricating according to the second embodiment a channel length for the nmos device is less than the channel length for the pmos device that is the channel length between the p halo impurity regions 54 of the.