microprocessor 100 as a sequence of 64 bit wide locations by packing two 32 bit words into one 64 bit word for i860 reads from transceivers 104 and 106 and by unpacking one 64 bit word into two 32 bit words of transceivers 104 and 106 for i860 writes the interface apparatus of fig2 saves clock cycles during address latching in accordance with the invention as follows during i860 read and write cycles controller 108 controls access to data bus xdata of the upper and lower transceivers as described above with respect to fig1 an i860 generated address is latched to an address latch 200 for each read and write operation in accordance with the invention the controller 108 controls the address latch 200 during relatching of the address to the memory device 102 such control is exerted after comparing a current address to a previous address to determine whether the i860 asserts an i860 34 same page 34 signal when row address bits 20 through 12 of a current address are the same as those of a previous address where the row address corresponds to a memory page address in the memory device the same memory page comparator 202 receives the i860 same row address signal and i860 iaddr 11 signal in a preferred embodiment the dram uses address bits 19 through 2 with its row address portion being bits 19 through 11 because the i860 typically uses address bits 20 through 3 with its row address.