output q from the flip flop 25 to thereby close the and gate 26 and hence stop the down timer 27 1 when the process at step s12 ends 2 when the cpu determines at step s8 that the start fag sf is not 1 or 3 when the cpu determines at step s9 that it has not yet received a time out signal to control returns to step s1 where the cpu iterates the operations at steps s1 s8 s9 mentioned above fig5 is a flowchart indicative of the details of the timepiece mode process of fig4 at step s2 of fig4 fig6 is a flowchart indicative of the details of the timer mode process at step s3 fig7 is a flowchart indicative of the details of the alarm mode process at step s4 referring to those flowcharts the operations of the timepiece will be described below in detail for example assume now that the timepiece is in a state a of fig8 in the timepiece mode in this case so long as no switch is operated the cpu determines that the value of the mode register m is 0 at step s1 of fig4 and that the timepiece mode process has been employed at step s2 thus control passes to step s2 involving the timepiece mode process shown by the flowchart of fig5 the cpu then determines that.