16 and to enable or inhibit certain features the data input multiplexer unit 14 selects between two 32 bit data input ports depending on the gate array mode one input port is from the array of memory devices and provides a minimum load to the memory devices the other data input port is for the source data when the memory is in the 34 write 34 mode the data input register unit 18 is a 32 bit register that holds the input data while parity bits are being generated the check bit register unit 20 holds the check bits from the selected random access memory sram while the gate array logic checks for errors in the data the check bit parity trees unit 22 generate the parity bits needed based on the truth table for a modified hamming 39 32 code see table i the syndrome generator logic input multiplexer unit 24 sgli mux outputs zeros in the generate mode outputs the check bits in the detect correct mode or diagnostic check bits in certain diagnostic modes the syndrome generator logic unit 26 is a set of seven 7 exclusive nor gates which operate on the output of the check bit parity trees and the output of the syndrome generator logic input multiplexer table i__________________________________________________________________________modified hamming 39 32 code used for theerror detection.