or 1 outputted from the phase detector 310 is inputted to one of input terminals of the first xor gate 321 a z signal outputted from one of output terminals of the d flip flop 322 is inputted to the other of the input terminals of the first xor gate 321 an x signal outputted from an output terminal of the first xor gate 321 and a trigger signal are inputted to input terminals of the d flip flop 322 and a y signal outputted from one of output terminals of the d flip flop 322 is inputted to one of input terminals of the second xor gate 323 the second xor gate 323 receiving an enable signal from the not gate 324 and the y signal from the d flip flop 322 outputs the control signal lc tank turning on off to the first lc tank 110 and or the second lc tank 120 through its output terminal the controller 320 illustrated in fig5 may be implemented by properly combining other logic gates well known in the art for example three not gates coupled in series may be embodied to perform the function of one not gate or an not gate and a nor gate coupled in series may be embodied to perform the function of one or gate now the input output signal relationship in each of the phase detector 310 illustrated in fig4 and the controller 320 illustrated in fig5 will be described with reference to fig6 and 7 fig6 and 7 are waveform diagrams showing.