the method described approximates this effect and alters the estimated voltage droop accordingly our techniques when compared to prior techniques allow for more accurate assessments of the effectiveness of the capacitors in a given area the resolution of this method is much higher and works on an entire chip as opposed to individual blocks on a chip it also takes block to block effects into account which previous methods which we have considered don 39 t handle turning now to the invention in more detail it will be understood that our method examines a vlsi design to create a data structure that represents all of the decoupling capacitors and all of the latches in the design keeping track of their chip level coordinates and capacitance values the capacitance values of decoupling capacitors is proportional to the charge stored by the capacitor the capacitance values of the latches is proportional to the worst case charge used by the latch when the latch loads a new value the values are stored such that the stored charge values and needed charge values reduce in magnitude when combined for example the capacitor values could have a positive number while latches could have a negative number the data structure organizes the capacitance values in a two dimensional array the indices of the array can be decoded to a specific location on the chip and the value in the array represents the capacitance found in an area around that location the size of this area can be adjusted to trade off accuracy for performance if the granularity is fine enough each capacitor and latch.