compensate for variations in memory cell characteristics from one memory cell 73 to another as is described in u201c verify key to the stable single electron memory operation u201d by t ishii et al 1997 iedm pp 171 174 with reference now to fig5 the write process 140 begins in a step 142 by activating one of the column address lines 75 and one of the row address lines 77 of fig3 a c to address one of the memory cells 73 in a step 144 a write pulse which may be either a current i w or a voltage v w pulse is applied to the addressed memory cell 73 in some embodiments the step 144 is used to write a binary value to the memory cell 73 in other embodiments the step 144 is used to write one of a plurality of possible values or data entries to the memory cell 73 by injecting a controlled number of electrons 32 into the islands 26 of the memory cell 73 in a step 146 an index variable n corresponding to a number of write cycles applied to this memory cell during this write process 140 is incremented in a step 148 the memory cell 73 is read by sampling a voltage or current associated with the.