array 130 are comprised of series strings of memory cells as is well known in the art the connections of the cells to the bit lines determines whether the array is a nand architecture an and architecture or a nor architecture address buffer circuitry 140 is provided to latch address signals provided through the i o circuitry 160 address signals are received and decoded by a row decoder 144 and a column decoder 146 to access the memory array 130 it will be appreciated by those skilled in the art with the benefit of the present description that the number of address input connections depends on the density and architecture of the memory array 130 that is the number of addresses increases with both increased memory cell counts and increased bank and block counts the memory device 100 reads data in the memory array 130 by sensing voltage or current changes in the memory array columns using sense amplifier circuitry 150 the sense amplifier circuitry 150 in one embodiment is coupled to read and latch a row of data from the memory array 130 data input and output buffer circuitry 160 is included for bidirectional data communication as well as address communication over a plurality of data connections 162 with the controller 110 write circuitry 155 is provided to write data to the memory array memory control circuitry 170 decodes signals provided on control connections 172 from the processor.