lines sl 1 to sl 4 in the related art a maximum of four peripheral elements 101 through 104 can be selected or addressed by the processor module with a direct connection over four select lines sl 1 through sl 4 shown here or corresponding select interfaces sp 1 through sp 4 then in addition to peripheral elements 101 through 104 peripheral elements 105 through 107 can also be selected by the processor module in particular selected individually due to the expansion with a selection identifier referred to in short as sbe select bit expansion to be explained in greater detail below in addition in the case of bus system 108 an spi bus in particular is assumed as an example other bus systems of comparable possibilities and applications may also be used according to the present invention spi communication usually takes place as follows controller or processor module 100 activates the select signal responsible for the spi module to be addressed i e the peripheral element over corresponding select interface sp 1 through sp 4 and then sends a command or instruction and optionally data over spi bus 108 the command or instruction which is sent one byte in the example is composed of command bits i e individual binary signals additional information may also be present in the scope of the information sent e g for correction of errors in such a traditional command structure six instruction bits or command bits instr 0 through instr 5 are then filed under bit 2 through bit 7 of the instruction sent plus one bit for error checking e g.