and outputs xy addresses corresponding to a top left pixel in a preferred embodiment of the present invention split adjust block 510 contains two incrementors to perform the split adjust the top left pixel is then coupled to an xy to linear converter 515 a top right pixel which is then coupled to an xy to linear converter 520 a bottom left pixel which is then coupled to an xy to linear converter 525 and a bottom right pixel which is then coupled to an xy to linear converter 530 each of the xy to linear converters 515 520 525 530 rearrange bits to generate linear addresses from the input xy address xy to linear converters 515 520 525 and 530 are coupled to a address chip enable generator 535 address chip enable generator 535 takes linear addresses as input and outputs corresponding physical memory addresses 545 and a plurality of chip enable signals 550 for the corresponding plurality of memory modules 310 in a preferred embodiment of the present invention address chip enable generator 535 and address chip enable generator 540 determine physical memory addresses by rearranging the bits of the output of xy to linear converters 515 520 525 520 it should be noted that one of skill in the art will recognize that although split adjust block 510 outputs four xy address for a given input xy address any number of xy addresses could be determined relative to a given xy address without departing from the spirit and scope of the present invention it is also noted that the output xy addresses of split adjust block 510 can be non contiguous without.