according to the invention the conventional dynamic latch circuits briefly described before will be explained in conjunction with fig1 a 1b and 2 to 5 in fig1 a and 1b a first conventional dynamic latch circuit includes a semiconductor substrate 10 having a diffused layer 14 formed thereon first to third interconnection layers 16 18 and 20 formed on the semiconductor substrate 10 and insulating layers 22 24 26 and 28 by which the interconnection layers 16 18 and 20 are insulated respectively the first to third interconnection layers 16 18 and 20 are connected with a plurality of contact regions 12 respectively the first interconnection layer 16 includes a first interconnection line 30 which is an input line of an inverter an input line 32 of the dynamic latch circuit and clock lines u03c6 and u03c6 each supplying a clock pulse to a clocked inverter the second interconnection layer 18 includes a second interconnection line 34 which is an output line of the clocked inverter the second interconnection line 34 is designed to be as short as possible to decrease a coupling capacity with other interconnection lines the third interconnection layer 20 includes an output line 36 of the latch circuit fig2 shows an equivalent circuit of the dynamic latch circuit shown in fig1 a and 1b the dynamic latch circuit includes a clocked inverter composed of two p channel transistors.