50 comprises a phase detector 100 a low pass filter 102 an oscillator 104 which functions in the same manner as does the oscillator 64 a digital inverter 105 and two edge triggered type d flip flops 106 and 108 the oscillator 104 produces a square wave signal which triggers the flip flops 106 and 108 the flip flop being triggered by the positive going leading edge of the square wave while the flip flop 106 which has its clock input complemented by the inverter 105 is triggered by the negative going leading edge of the square wave the respective output signals of the flip flops 106 and 108 change state with each triggering of the respective flip flops 106 and 108 toggle operation of the flip flop 108 wherein the output signal is complemented with each triggering by the input signal at terminal c is accomplished by coupling the complemented output terminal q to the d input terminal the output signal of the flip flop 106 is forced to follow that of the flip flop 108 by coupling the output terminal q of the flip flop 108 to the d input terminal of the flip flop 106 thus there appears at terminal b of the loop 50 a square wave having a frequency equal to one half the frequency of the square wave produced by the oscillator 104 at terminal c of the loop 50 there appears a square wave having the same frequency.