the memory device 5 the tri state buffers are omitted and the input data di is directly connected to the input of each memory cell 50 in fig7 a fig8 is a circuit diagram showing still another embodiment of a circuit of a memory cell comprised in the memory device 5 shown in fig3 in accordance with the present invention referring to fig8 the memory cell comprises an inverter 81 including a p type mos transistor 83 and an n type mos transistor 84 connected in series an inverter 82 including a p type transistor 85 and an n type mos transistor 86 connected in series between the power supply vcc and the ground vss n type mos transistors 87 and 89 for receiving the input data di and the inverted signal di respectively and n type mos transistors 88 and 90 for providing the output data do and the inverted signal do to outside in setting the driving capability as used in fig6 b and 7b no particular condition is necessary for the inverters 81 and 82 an operation is briefly described since the operation of the circuit of the memory cell shown in fig8 is the same as that of a well known static.