converter 14 may be as indicated above a simple comparator if the output voltage v o exceeds the nominal value v ref controller 42 activates timer 28 via run signal and enters into a sleep mode according to the clock used by timer 28 if timer 28 works with the system clock ckhf controller 42 goes into a wait loop but continues to activate clock manager 30 so that it maintains the high frequency system clock ckhf active otherwise controller 42 informs clock manager 30 of the possibility to disable the system clock ckhf provided that the other controller 42 u2032 does not grant an opposite query controller 42 may choose the switching topology and this information top is transmitted to both controller 40 and digital circuit 32 to determine the durations of phases of charge and discharge according to one embodiment the control circuit of controller 40 is made by a finite state machine fsm the fsm works in a loop waiting for a service request req from one of controllers 42 and 42 u2032 upon receipt of a service request the input is measured and adc converter 20 is activated by an activation signal adc i the measured value is applied to digital circuit 32 which determines the duration of t p and t s more precisely t p t s1 and t s2 as a multiple of the period t c of the clock ckhf the values calculated by the digital circuit 32 are used via multiplexer 34 and counter 36 to implement the various switches described above according to the calculated durations and the selected converter topology as mentioned above digital circuit 32 determines the various durations t p t s1 and t s2 either from a table of correspondence or by directly calculating these values.