present invention which is related to the sbd portion device structure 1 as shown in fig5 since the impurity is ion implanted into the entire surface to control the threshold vth of the intermediate breakdown voltage mos fet portion the impurity is also automatically implanted into the surface of this portion implantation region will not be particularly shown for the avoidance of intricacy in the same manner as in the subsequent drawings next the sbd portion device structure 3 will be described fig6 is a device cross sectional view process step f illustrating the process flow in the method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention which is related to the sbd portion device structure 3 as shown in fig6 since the impurity is ion implanted into the entire surface to control the threshold vth of the intermediate breakdown voltage mos fet portion the impurity is also automatically implanted into the surface of this portion the same also holds true for the sbd portion device structure 2 fig2 is a device cross sectional view process step g illustrating the process flow in the method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention which is related to the low breakdown voltage portion and the intermediate breakdown voltage portion as shown in fig2 the n well nw and the p well pw are formed in the respective regions of the pmos fet and the nmos fet and using resist patterns for ion implantation for the respective wells impurities for controlling the thresholds.