1 during the previous frame is read from data buffer location 262 and placed on data read bus 268 during the same clock cycle the value of the most recent data sample is copied to data buffer location 262 and this location then holds x 0 simultaneously with the copy of the most recent data sample to data buffer location 262 mac 1 220 generates the update term for h n u2212 1 by multiplying in mpy 226 x n and the error term in temporary register 270 which as stated above is preferably 2 u03b2e the dashed arrow from temporary register 270 to mpy 226 indicates that the contents of temporary register 270 are u201c automatically u201d provided to mpy 226 possibly as a hard wired connection between the register and mpy 226 this contrasts with the solid arrows which generally indicate connection via a bus the product x n 2 u03b2e is fed through adder 228 and temporarily stored in acx 246 during the second clock cycle the first lms iteration is performed but the value written to memory is ignored while the architecture is being set up for repetitive cycling data sample x u2212 1 is read from data buffer location 264 and placed on data read bus 268 coefficient h n u2212 1 is simultaneously read from coefficient buffer location 252 and placed on coefficient read bus 258 mac 2 230 performs one calculation of the fir filter output by multiplying x n u2212 1 and h n u2212 1 in mpy 236 the product is added in adder 238 to the contents of acy 244 which is null because acy 244 was just cleared out this operation is u201c automatic u201d as indicated by the dashed arrow the result of the sum.