in other words conductivity regions 32 84 and 66 are described as being n type regions but in a pmos device such regions would correspond to p type regions further region 72 is described as being a p type halo region in the shown nmos construction but in a pmos construction would correspond to an n type region referring to fig8 a dram construction 100 is formed utilizing the transistor devices of fig7 specifically an insulative material 110 is formed over substrate 12 and conductive interconnects 112 114 and 116 extend through the insulative material 110 to the source drain regions 93 95 and 97 insulative material 110 can comprise for example borophosphosilicate glass bpsg and conductive interconnects 112 can comprise for example one or more of conductively doped silicon metal silicide and elemental metal conductive interconnect 114 is electrically connected with a bitline 118 which results in an electrical connection between shared source drain region 95 and the bitline 118 electrical connections 112 and 116 are incorporated into capacitor constructions 120 and 122 respectively specifically a dielectric material 124 is formed over electrical connections 112 and 116 and a capacitor plate 126 is subsequently formed over the dielectric material 124 accordingly conductive interconnects 112 and 116 are incorporated into capacitor constructions 120 and 122 as storage nodes dielectric material 124 can comprise for example one or more of silicon dioxide silicon nitride or so called high k dielectric materials such as tantalum pentoxide capacitor plates 126 can.