increased accordingly and this essentially because of the increase of the number of input output pins and connecting lines between the elements of integrated circuits used it is suggested here that these drawbacks may be overcome by means of the device shown in fig3 this figure illustrates the matrices am and om which are similar to those shown in fig1 but here matrix om is provided with an address zone ad which supplies an output which carries the so called address information this output is used to address the different word positions which are arranged in rows in the chosen example of a storage means which in this embodiment is a random access memory matrix with a plurality of word positions mem through a decoding circuit decode mem this programmable logic device therefore has as many parallel mounted registers similar to rg as there are rows in memory mem this number of rows will be a function of the number of the intermediate storage operations involved in the carrying out of the complex logic function for which the programmable logic array pla has been conceived the input e of the device will receive the data bits and or the status control bits which will be defined further on it should be noted that the diagram shown in fig3 is very much schematic and that what has been referred to as a complex logic function may actually result from the combination of a plurality of functions either simple or complex as further illustrated with the help of an example in order to make the invention more clear it will now be illustrated as applied to a specific application say a digital timer this timer comprises a modulo.