reducing the leakage current a significant issue with run time power gating is having adequate time to transition the gates from sleeping to fully powered i e having enough time to wake that is when power gate 201 is turned on the power gated gates take time to fully charge to their fully powered state in response to power gate 201 and or 202 turning on one approach is to include sufficient timing margin in the design e g a guard band in the timing design to ensure the gates are fully powered however such a timing penalty is generally unacceptable in high performance integrated circuits such as microprocessors control logic 205 monitors the clock gate enables 221 and 223 of the source flip flops 207 to determine when to wake and when to sleep the power gated gates the number of clock gate enables shown is illustrative and other numbers of enables may be utilized based on design requirements note that the and gate 208 may also be considered part of control logic 205 and helps control the clocking of the destination flip flops as described further herein note that while flip flops are shown in fig2 any source and destination storage elements such as latches may be used instead of or in addition to the flip flops shown in fig2 fig2 illustrates the basic operation and construction of an exemplary embodiment a chosen set of destination flip flops 209 determines the set of gates 203 that can be power gated that is a gate can be power gated if all of its output.