the flip flop 6 in the main board 1 is set and the outputs q and q become high and low respectively therefore the output of the nand gate 7 becomes low and the halt request signal hreq a is input to the flip flop 16 in the cpu board 2 thereby the outputs q and q of the flip flop 16 become low and high respectively and the processor 15 halts by itself when the processor 15 halts i e enters into a stop condition the status signal thereof becomes high and the output of the nand gate 17 becomes low so that the halt acknowledge signal hack a is sent back to the main board 1 as a result the output of the and gate 9 becomes high and the halt request signal hreq b applied to the cpu board 3 also becomes high so that the output of the flip flop 19 becomes high and the halt condition of the processor 18 is released thereby the processor 18 enters into the operating condition and the address signal the data signal and the above mentioned control signals eb qb rwb and so on are transmitted from the processor 19 to the main board 1 internal clock signals cka and ckb applied to the flip flops 16 and 19 of the cpu boards 2 and 3 respectively are used for setting or resetting the flip flops 16 and 19 respectively in accordance with the internal timings in the corresponding cpu boards thus for example when a halt request signal is.