or atomic layer deposition ald oxygen scavenging layer 400 may include but is not limited to lanthanide metal rare earth metal tin u2014 particularly ti rich tin group 2 elements or group 3 elements oxygen vacancies within the high k dielectric layer 300 created by the deposition of the oxygen scavenging layer 400 consume the top surface of the underlying oxide nitride oxynitride or nitrided oxide interfacial layer 200 an anneal is then performed an o2 or n2 ambient or sequence of each may be performed the anneal temperature may be above 900 u00b0 c optionally the process can include gate formation before the anneal optionally a first anneal can occur before gate formation and a second anneal occurs after gate formation referring to fig2 in an alternate embodiment of the invention a base oxide layer 110 may be formed on substrate 100 prior to the plasma or thermal nitridation base oxide layer 110 may have a thickness of approximately 3 u00e5 to 20 u00e5 base oxide layer 110 may be deposited or grown by any known or later developed processes the remaining steps are the same as described in the first embodiment the method as described above is used in the fabrication of integrated circuit chips the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form that is.