format such rounding can be implemented as part of the final adder within the multiplier structure not shown or in programmable logic outside the dsp block 100 when the output of the multiplier 101 is outputted directly from the dsp block 100 the floating point multiplier 101 can feed the floating point adder 102 directly in a multiplier add madd mode as depicted in fig1 alternatively as depicted in fig1 a the multiplier 101 output can be routed around the adder 102 directly to the output of the dsp block with a multiplexer 103 provided to select between the output of the multiplier 101 or the output of the adder 102 although the bypass 104 and multiplexer 103 are omitted from the other drawings to avoid cluttering those drawings they should be considered to be present in all of the multiplier adder dsp blocks shown including that of fig1 fig2 shows a more detailed diagram of an exemplary dsp block 200 according to an embodiment of this invention optionally bypassable pipelining not shown may be provided between the floating point multiplier 101 and the floating point adder 102 optionally bypassable pipelining not shown can also be provided within either or both of the floating point multiplier 101 and the floating point adder 102 inputs can be routed to the adder 102 from multiple sources including an output of the multiplier 101 one of the inputs 201 to the dsp block 200 or a direct connection 202 from an adjacent similar dsp block 200 in addition the output of multiplier 101 and or one of the inputs 201 to the.