channel long l device 24 having a source coupled to a potential node 26 the potential node 26 is configured to accept a voltage source the p channel long l device 24 also has a drain coupled to a signal node 28 the gate of the long l device 24 is bled to ground thereby allowing signal node 28 to constantly receive a voltage signal from the potential node 26 the signal node 28 carries the voltage signal through a pathway leading to ground but that pathway is interrupted by a fuse 30 moreover the signal node 28 is coupled to a first inverter 32 the output of the first inverter 32 connects to the gate of an n channel transistor q 1 which is a component of a multiplexer 80 electrically interposed between the redundant contact pad 20 and the logic circuit 18 in addition the output of the first inverter 32 serves as the input for a second inverter 34 this second inverter 34 connects to the gate of a p channel transistor q 2 which is another component of the multiplexer 80 in operation the potential node 26 the p channel long l device 24 the signal node 28 and the fuse 30 cooperate to determine the drive state of the multiplexer 80 the fuse 30 is initially intact and provides grounding communication for the signal node 28 because the signal node 28 is grounded a low voltage signal or u201c logic 0 u201d is generated and carried to the first inverter 32 accordingly the first inverter outputs a high voltage signal or u201c logic 1 u201d the high signal drives the n channel transistor q 1 the high signal also serves as input to the second inverter 34 and the resulting low signal.