of a flag sequence constituted by n successive 34 1 34 bits preceding the start of a data bit train a decade counter 8 has its clear input connected to the incoming electrical signal line b for being reset at each incoming 34 0 34 bit and has its clock input connected to the output d of counter 17 to thus count successive incoming 34 1 34 bits output e of the counter 8 is connected by an inverter 9 to the preset input of a d type flipflop 12 for setting the flipflop 12 when a flag sequence or n incoming high bits are received the output of nor gate 7 is connected by inverter 10 to the clock input of the flipflop 12 which has its d input held low to reset flipflop 12 upon the fall or leading edge of the incoming low bit following the flag sequence a nand gate 11 has inputs connected to the output of nor gate 7 and the noninverted output of flipflop 12 with its output connected to the load input of a 4 bit decade counter 13 which has its preset inputs set for a selected number for example 0000 the clock signal clk is applied by inverter 14 to the clock input of counter 13 the third most significant bit output qc of couner 13 which goes high at the count of 4 and returns low at the count of 8 is connected to the clock input of a d type flipflop 15 which has its data input connected to the incoming signal line b so that the level.