synchronized with this phase comparison period although v mod varies it always returns to its starting point when phase comparison occurs thus v mod and v ctl are equal at the beginning of the slow modulation cycle when phase comparison occurs after phase comparison occurs v mod changes as it cycles through a modulation cycle returning to its initial voltage just as the next frequency modulation occurs fig5 is a timing diagram showing that the phase comparison for frequency lock occurs at the start of every modulation sweep cycle the control voltage v ctl from the master pll is generated by a phase and frequency comparison that is performed during times 100 even though the clock output from the master pll varies in frequency the clock output always has the same frequency at times 100 since the modulation cycle begins and ends at times 100 the modulated voltage v mod generated by the slave voltage locked loop varies from v ctl during a modulation cycle however the modulation cycle begins and ends at times 100 since the modulation is exactly synchronized to the frequency lock period of the master pll loop since the control voltage v ctl from the master pll is always equal to the modulated voltage v mod from the slave voltage locked loop at times 100 the.