upper bit of the transmission data signal is inputted through the inverting circuit 20 that is when the upper bit of the transmission data signal is equal to 34 1 34 34 01 34 is supplied to the 2 bit adder 21 when the upper bit of the transmission data signal is equal to 34 0 34 34 11 34 is supplied to the 2 bit adder 21 in order to calculate a phase rotation quantity the output bits of the 2 bit adder 21 are held in the latch circuits 22a and 22b as a phase state in a previous clock in synchronous with the transmission clock signal when the next transmission data signal is inputted to the 2 bit adder 21 in synchronous with the transmission clock signal the phase state of the transmission data signal in a current clock is added to the phase state of the transmission data signal in the previous clock thus a phase change can be determined however if the addition is simply performing when the upper bit sequence of the transmission data signal is for example 34 1 1 1 34 output values i e i data q data of the latch circuits 22a and 22b become 0 1 1 0 and 1 1 when the values are changes from 0 1 to 1 0 both of the i data and the q data are simultaneously changed during a single clock this situation means that the phase changes by an amount of u03c0 in the gmsk modulation however.