2 e alternatively restoration may occur from the slave stage itself as will be described in greater detail below the circuit elements shown in fig3 may represent a portion of an integrated digital circuit containing several circuit elements four flip flops 120 1 121 1 120 2 and 121 2 have been represented in the fig although it is contemplated that any number of flip flops may be used depending upon the application as with fig1 described above flip flops 120 and flip flops 121 are all substantially identical each of flip flops 120 121 is part of the normal logic of circuitry 110 which is to be tested generally along with other normal logic not shown which generates the data signals 16 1 through 16 n normally applied to the data input terminals of flip flops 120 121 and or which uses the registered output signals 30 1 through 30 n of those flip flops as in fig1 described above each flip flop contains a master stage 122 123 followed by a slave stage 124 input pass gate 126 is provided at the input to each master stage 122 123 from data signals 16 n interstage pass gate 128 is provided at the input to each slave stage 124 from the output of each master stage 122 123 feedback pass gate 127 is provided on signal path 129 which extends from the output of slave stage 124 to the input of master stage 122 123 in the preferred embodiment pass gates 126 and 128.