data simd reduced instruction set computing risc device consistent with the simd characteristic the pes 20 execute the same instruction at the same time externally generated microinstructions control primitive logic and arithmetic functions during each clock cycle an svp device may include an instruction generator not shown in the same device and the instruction generator may also have a program memory implemented with ram or mask rom the basic components of svp 10 are described briefly herein reference to the above referenced patent will provide further description especially with regard to instructions and timing referring to fig1 and 2 the svp 10 has a three layer structure a data input register dir 11 pes 20 and a data output register dor 16 dir 11 can be thought of as the 34 input layer 34 the pe 39 s 20 are the 34 computational layer 34 dor 16 is the 34 output layer 34 the input to dir 11 is word serial in the sense that words of an incoming line of data are received into dir 11 word by word similarly the output from dor 16 is word serial in effect each word of dir 11 and dor 16 has a corresponding pe 20 although input and output are word serial the pe 39 s 20 perform their processing on each line of data values in parallel also because of the 34 layered 34 approach to processing data input computation and data output may be concurrent operations with each being independently clocked each pe 20 is a 34 pipeline 34 that enables different data values to undergo operations.