with respect to serial data stream signal sds and symbol clock signal sc as received by modem 102 in order to accomplish this in the example from experimental practice a full wave rectifier within modem 102 is employed as rectifier 104 to avoid advancing or retarding the phase of timing signal ts bandpass filter 105 has a center frequency at 400 hz and exhibits a substantially flat amplitude response characteristic with a low quality factor approximately unity to avoid introducing any phase shift into signal ts in experimental practice filter 105 comprises a low pass filter having a cutoff frequency above 400 hz combined with a high pass filter having a cutoff frequency below 400 hz phase demodulator 110 coherently detects the phase differences between the received ts an locally generated lts1 through lts4 timing signals to indicate and control the phase of the frame clock signal which properly synchronizes signal frclk with the frames in serial data stream signal sds control signals x and y generated by phase demodulator 110 are employed to control the phase of frame clock signal frclk phase demodulator 110 comprises a phase detection circuit and a waveshaping circuit the phase detection circuit includes phase inverter 111 and transmission gates 112 113 114 and 115 the waveshaping circuit includes low pass filters 116 and 117 and clamp circuits 118 and 119 the following description of phase demodulator 110 is focused on those phase detection and waveshaping circuit elements which generate signals x and x at the output of phase demodulator 110 when appropriate changes are made to the signal names and element reference numerals the following description also applies to the phase detection and waveshaping.