shapers 12 at its clock input to set the q output of flip flop 21 to high level the period during which q output of flip flop 21 is high is defined as the logic window this window is established by clock circuit 30 which includes a potentiometer 31 to permit adjustment of the repetition rate of the circuit preferably control potentiometer 31 is selected to permit adjustment of the spacing between block pulses in the range of 30 milliseconds to 660 milliseconds the clock output at b is connected to the clock input of binary counter 40 thus each occurrance of a clock pulse at point b will cause counter 40 to advance one count the window is established by clock circuit 30 which advances binary counter 40 via lead 34 and enables the reset input of counter 40 via lead 33 through nand gates 25 and 27 when the q output of flip flop 21 is high gate 25 is disabled and no reset will occur when q output of flip flop 21 is low and q of flip flop 22 is high the clock pulse will reset counter 40 as will now be understood a detected uv pulse during a window interval will set the q output high inhibiting coutner 40 from resetting however.