not shown next to describe the detailed arrangement of the semiconductor memory apparatus which is the first preferred embodiment of the present invention with reference to fig5 peripheral circuits 15 and 16 both corresponding to a memory cell forming region 17 involving the k 1 th bit line pairs bla k 1 and blb k 1 respectively adjoining the kth bit line pairs bla k and blb k in fig2 are arranged outside the memory cell forming region 17 along edges 12 and 11 respectively of the region 17 further said peripheral circuits 15 and 16 are formed in a symmetric arrangement with respect to the intersection point g of centerlines 18 and 19 respectively connecting the middle points of the edges 11 and 12 and those of edges 13 and 14 the bit line pairs bla k and blb k are connected to the peripheral circuit 15 via connecting points p1 and p2 on a side of the peripheral circuit 15 opposite to said memory cell forming region 17 similarly the bit line pairs bla k 1 and blb k 1 are connected to the peripheral circuit 16 via connecting points q1 and q2 on a side of the peripheral circuit 16 opposite to said memory cell forming region 17 with the arrangement direction of the peripheral circuit 15 being represented by f that of the peripheral circuit is represented by see fig5 fig6 is a plan illustrating a part of the arrangement pattern corresponding to fig4 of a case in which the peripheral circuits 15 and 16 of fig5 involve sense amplifiers 31 of fig3 the same constituent parts as in fig5 are assigned respectively the same reference numerals or codes the metallic wiring patterns 61.