lifting pipeline 301 and a flip flop ff 9 302 the lp 4 output buffer 36 and the lp 5 output buffer 43 are enabled at odd numbered clock edges the hp 4 output buffer 38 the hp 5 output buffer 42 and flip flops ff 9 302 are all enabled at even numbered clock edges in word serial and bit parallel format the lp 4 output data flows into the fifth lifting pipeline 301 during odd numbered clock phases in the same data format the output from the fifth lifting pipeline 301 is stored in the lp 5 output buffer 43 two consecutive data words flowing out from the hp 4 output buffer 38 are input to the fifth lifting pipeline 301 during even numbered clock phases the two consecutive data words are output from the hp 4 output buffer 38 and the output from flip flop ff 9 302 the data from the hp 4 output buffer 38 after passing through flip flop ff 9 302 is input to the hp 5 output buffer 42 during even numbered clock phases referring to fig4 c the lp 4 output buffer 36 and the parallel adder 5 41 are operating in odd numbered clock phases the ff 9 output buffer 310 the read only memory rom 5 315 the hp 4 output buffer 38 and the pipeline multiplier and adder unit 5 pma 5 312 are all operating in even.