is deasserted a condition that halts the counting by the host clock counter 66 however when the bpri signal is asserted a condition that indicates that the north bridge 34 is gaining ownership of the local bus 33 the host clock counter 66 counts on each cycle of the bclk signal in this manner if the host clock counter 66 indicates the predetermined threshold before the expiration of the bpri timer 60 then the duration of the window 100 is shortened therefore the above described arrangement ensures that there are x number of clock cycles for the processor 32 in y number of clock cycles otherwise the bpri signal is deasserted and the host timer 62 begins measuring the window 110 to give additional bandwidth to the processor 32 an ads timer 68 of the arbitration control circuit 42 works in a similar manner to control the duration of the window 110 more particularly the ads timer 68 monitors a signal of the local bus 33 called ads that indicates when the processor 32 is beginning a cycle on the local bus 33 in some embodiments the ads timer 68 counts the number of cycles of the bclk signal that elapse between the processor 39 s assertion of the ads signal in this manner the ads timer 68 counts up to a predetermined threshold established by a value that is stored in a configuration register 63 that indicates that a predetermined number of cycles of the bclk signal has elapsed between cycles that are run by the processor 32 in other words the ads timer 68 only counts when the ads signal is deasserted and thus indicates the collective duration of the time segments 108 if the ads timer 68 reaches the predetermined number of clock cycles before the host.