pat no 5 987 601 for the purpose of the following descriptions tasks consist of register data and control information which are all considered data common to all figures a set of registers 4 7 and 10 respectively is connected to input mux 39 s 3 6 and 9 registers y 7 and c 10 have outputs connected to mux 8 that is in turn coupled to task memory 1 register x 4 is the u201c working register u201d in that the next task to run is always loaded through this register directly to the alu 11 it has no output mux a task control circuit 5 is coupled to the task memory 1 via a control bus task control 5 is connected to the u201c select u201d pins of all mux 39 s including mux 2 which has an output coupled to mux 3 the task control circuit 5 is also coupled to the u201c enable u201d pins of registers 4 7 and 10 and a system clock is connected to the clock inputs of all registers and the task memory 1 the alu 11 is chosen as an example of a processor function for use with the system a cpu or other task execution unit could also be used in fig1 the task to execute in the next execution cycle is the same task currently executing therefore data initiating in working register x 4 is sent through the alu 11 for possible processing routed through mux 3 and back to register x 4 completing the execution cycle the data route of this task is illustrated as.