exclusive or operation carried out by error corrector 50 leaves data bits d i intact alternatively correction inhibit signals can operate directly on the output from decoder 92 to provide a set of zero corrector bits e 1 to corrector 50 in preferred embodiments of the present invention the signal to set the syndrome to an all zero value is derived from on chip control logic 60 in this way on chip means are provided for disabling the on chip error correction circuitry the disablement of the on chip error correcting circuitry actually enables the double complement algorithm to be carried out at the system level and furthermore allows diagnostic mapping of the memory to be done this functionality is very desirable during memory test operations when it is desirable to be able to determine the presence of faulty memory locations more importantly this provides the ability to reproduce hard errors a property which is necessary for the proper operation of the complement recomplement method employed for error correction of hard hard errors at the system level in this way when the memory unit modifications shown in fig2 is employed in a fault tolerant memory system greater system reliability is achievable without the memory unit modification whenever there is a double error at the system level the data is not recoverable with the memory unit modification all hard hard and hard soft errors at the system level are correctable from the above it should be appreciated that the present invention provides a mechanism for enhanced fault tolerant capabilities in memory.