no branch step 304 the processor enters into an external microcode execution error state to be subsequently tagged as a secondary processor chip i e processor 106 and 108 and the initialization of the secondary processor chip is placed in a standby mode responsive to determining the external microcode instruction was received yes branch step 304 the processor enters into an external microcode execution running state and tags itself as a primary processor chip i e processor 104 step 306 and processor 104 executes the external microcode instruction step 308 processor 104 determines if all external microcode instructions have been performed step 310 responsive to determining there is another external microcode instruction to be executed no branch step 310 processor 104 fetches an external microcode instruction as previously discussed in step 302 responsive to determining all external microcode instructions have been executed yes branch step 310 processor 104 ceases fetching instructions from external boot microcode 300 fig4 is a flowchart depicting operational steps for synchronizing the primary microprocessor with the secondary microprocessors synchronizing the primary microprocessor with the secondary microprocessor ensures the operability of the smp system synchronization allows for the primary processor to determine the performance capabilities of each secondary processor during operations and distribute application requests among the secondary microprocessors accordingly the primary processor.