processor bus 14 and a cache 16 which is used to stage data to and from the processor 12 at reduced access latency is also connected to the processor bus 14 in non limiting embodiments the processor 12 can access data from the cache 16 or from a system solid state memory 18 by way of a memory controller function 20 also the memory controller 20 is connected to a memory mapped graphics adapter 22 by way of a graphic bus controller 24 and the graphics adapter 22 provides a connection for a monitor 26 on which the user interface of software executed within data processing system 10 is displayed the non limiting memory controller 20 may also be connected to a personal computer interface pci bus bridge 28 which provides an interface to a pci bus 30 connected to the pci bus 30 may be an input output i o controller 32 for controlling various i o devices including e g a keyboard mouse adapter 34 which provides connection to a keyboard 36 and to a pointing device 38 which may be implemented by a mouse trackball or the like additionally a hard disk drive 40 is connected to the i o controller 32 if desired an optical disk drive 42 such as a dvd or cd drive can be connected to the i o controller 32 in some implementations a.