generator of fig1 in fig2 there are shown shift registers 201 and 205 to which data signals to be written are applied a delay look up table 210 a delay offset store 215 summing units 220 1 220 2 220 3 and 220 4 and a delay unit sequencer 225 the shift register 201 receives incoming data and has a delayed output coupled to the write driver 220 of fig1 the shift register 205 receives the data to be written and is coupled to the delay look up table 210 which in turn is coupled to the combining units 220 1 220 2 220 3 and 220 4 delay offset store 215 receives offset values from the calibration unit 110 and is coupled to the combining units 220 1 220 2 220 3 and 220 4 which are in turn coupled to the clock delay units 103 1 103 2 103 3 and 103 4 of fig1 respectively the delay unit sequencer 225 receives timing control signals from the control 100 in fig1 and is coupled to the combining units 220 1 220 2 220 3 and 220 4 in the precompensation arrangement having four clock delay units a pattern of adjacent data signals consists of the current data signal data m and the 2 preceding data signals data m u2212 1 and data m u2212 2 may be used to determine the recording time of the data m data signal the shift register 201 receives the data signal data m to be written and provides.