layer 22 using a dry etching process the trenches 23 extend into the n doped substrate 21 they have a depth of for example 0 4 u03bcm the trenches 23 are arranged in a cell field 24 in the substrate 21 they run as parallel arranged strips over the cell field 24 the width of the trenches 23 and their separation are in each case implemented with a minimum structure size f of for example 0 6 u03bcm the length of the trenches 23 at right angles to the plane of the drawing shown in fig6 is for example 250 u03bcm the area of the cell field 24 parallel to the surface of the substrate 21 is for example 250 u00d7 250 u03bcm 2 in addition to the cell field 24 the substrate 21 comprises a periphery 240 in which a read out circuit and the like are implemented an insulating layer 25 made of for example sio 2 and having a thickness of for example 100 nm is produced over the entire area on the surface of the p doped layer 22 and of the trenches 23 the insulating layer 25 is deposited using for example a teos method a photoresist mask 26 is subsequently produced which covers those areas of the insulating layer 25 in which mos transistors having a higher operating voltage are intended to be formed in the cell field 24 an area with a size of 1 f u00d7 1 f f minimum structure size for example 0 6 u03bcm is in this case covered per mos transistor the structures of the photoresist mask 26 are shifted laterally by 1 2f with respect to the arrangement of the trenches 23 so that the structures of the photoresist mask 26 cover a part of the.