since flip flop f2 had been reset when power was applied to the circuit a logic level 0 signal appears at its q output consequently flip flop f1 provides a logic level 1 signal to exclusive or gate g2 and flip flop f2 applies a logic level 0 signal to this gate exclusive or gate g2 then provides a logic level 1 signal which is inverted to a logic level 0 new data enable new den signal this logic level 0 signal is then applied to the enable enb input of tri state gate g3 thereby causing that gate to transfer the data appearing on its data in lead g3a to its data out lead g3b the data on lead g3b then appears at the j input of flip flop f3 thus tri state gate g3 responds to the logic level 0 den signal in the same manner as the prior art circuit and causes data to appear at the j input of flip flop f3 subsequently when the data is stable at the data out lead the cpu removes both the data enable and read signals by simultaneously applying logic level 1 signals to leads i1a and i2a with the prior art arrangement if the gate delays of inverters i1 and i3 and tri state gate g3 were short and.