in a number of ways for example logic cell delay 35 is the time difference between when the voltage on input signal 31 reaches u00bd vdd u2212 vss and the time when the voltage on output signal 33 reaches u00bd vdd u2212 vss for logic not gate 12 shown in fig2 there is only one input and one output however other logic gates may have plural inputs or outputs for example a logic nor gate 22 shown in fig4 has an input 20 and an input 21 both a signal on input 20 and a signal on input 21 are used by logic nor gate 22 to produce an output signal on an output 23 a capacitor 24 represents the capacitive load driven by logic nor gate 22 the capacitive load driven by logic nor gate 22 generally includes both the input capacitance of logic gates which utilize the output signal on output 23 as well as the capacitance of the wiring which connect these logic gates to logic nor gate 22 when placing performance information in a logic cell library one methodology is to place this information in tables there may be more than one table stored for each logic cell a logic cell for example implements a logic gate such as a logic not gate 12 shown in fig2 or logic nor gate 22 shown in fig4 for example if a logic cell has more than one input and one output a different table or set of tables is stored for each input output pair also generally there are separate tables for the output ramp and the logic cell delay depending upon the implementation the input ramp indices and the output load indices may or may not be shared by the.