the rise of the reset signal rst r therefore the data of the 0 address of the memory cell array 1 is read by the selecting portion and is stored in the register 12 and accordingly the data 0 is read from the register 12 to the latch read amplifier 10 by the next read clock signal r 0 that is the selecting portion is operated by the read reset signal rst r to replace the unnecessary data m 1 with the data 0 next the case where the read reset signal rst r is not input to the selecting portion 3 r 5 r 6 will be considered even when the read reset signal rst r is input to the read pointer 9 the selecting portion is not operated and therefore the previously written data m 1 remains at the register 12 in this state when the read clock r 0 is input the data m 1 is read from the register 12 to the latch read amplifier 10 this means that indefinite data is transmitted as the output d out such a disadvantage is avoided by operating the selecting portion by the fall of the read reset signal rst r thus in the second embodiment as illustrated in fig6 in addition to the fact that the read speed can be increased the read of indefinite data immediately after a read reset operation can be avoided in fig8 which illustrates a third embodiment of the present.