decoder 166 electrically connected to the rows 172 through the row sel 194 and the row desel 162 in operation for example a physical address of a memory cell 154 to be accessed may be specified by a memory cell address which may be included in a memory access command the memory cell address can include a column address and or a row address corresponding to the column and the row corresponding to a target memory cell on which an access operation is to be performed upon receiving the memory cell address the column decoder 164 is configured to decode a column address and select or deselect the column by activating either or both the col sel 196 or and the col desel 160 similarly upon receiving the memory cell address the row decoder is configured to decode a row address and select or deselect the row by activating either or both the row sel 194 or and the row desel 162 still referring to fig4 in some embodiments the memory apparatus 150 further includes a memory controller 168 which may be configured to control the various access operations performed on the memory array 154 including reset set and read access operations in operation the memory controller 168 can be configured to receive signals from a processor to access one or more memory cells 152 in the memory array 152 the memory controller 168 is in turn configured to transmit control signals to the memory array 154 through the column decoder 164 and the row decoder 166.