in the signal delay stage 31 by a time lag which nearly corresponds to the signal duration of the signal u 28 in this manner the signal u 30 which corresponds to the signal end range of the signal u 28 is generated at the output of the and gate 30 given correct polarity and as a result of the phase shift this signal u 30 must appear during the signal duration of a signal u 29 which corresponds to the differential signal u a u k therefore given correct polarity signals u 32 which correspond to the signals u 30 are produced at the output of the and gate 32 these signals u 32 trigger the retriggerable timing element 33 so that the test lamp 21 is lit and indicates a correct polarity the case of an incorrect polarity is depicted in the three lowest signal lines i e the test probe 15 is connected to the anode and the test probe 16 to the cathode of the electrolytic capacitor 11 accordingly the signal u 28 now results at the output of the signal conditioner stage 28 from the measuring signal u a in a corresponding manner the signal u 29 results from the differential signal u k u a in this case the signal u 30 occurs not simultaneously with a signal u 29 so that no signals occur at the output of the and gate 32 the retriggerable timing element 33 is.