of leads in the bus this notation is used throughout the disclosure an input read address bus a out extending from the window manager 500 to display memory 504 however is only 9 bits wide whereas 18 address bits are required to address 256k 64 bit words therefore two operations are required to specify the required 18 address bits a signal on lead ras row address signal signals the first operation and a signal on lead cas column address signal signals the second operation a 64 bit word from display memory 504 illustratively comprises data for four 16 bit contiguous cells on the display screen the entire word is inputted into a latch 510 and the data for the individual cells metered out at appropriate times under control of a multiplexer select circuit 512 circuit 512 is in turn controlled by signals on an address enable lead aen and two address select leads a0 and a1 which identify the particular 16 bit word to be selected from the 64 bit word the cell data from latch 510 is routed into a stipple circuit 514 on bus data0 this circuit is controlled by stipple signals on bus 516 and by a horizontal border detection signal h bord on lead 518 from the window manager 500 to add desired selective background textures onto the screen to individual.