
{"publication_number": "US-5166895-A", "abstract": "tap arithmetic units and first delay circuits are arranged alternately . each of the tap arithmetic units has a full - adder array for multiplying an input signal which has been sampled at regular intervals and coefficients , a second pipeline delay circuit for delaying outputs of the full - adder array by a predetermined time and an adder circuit for adding outputs of the second delay circuits . the first and second delay circuits are timed to the preceding tap arithmetic unit for arithmetic operations . the use of the second delay circuit for the timing of arithmetic operations permits the arrangement of the first delay circuit to be simplified .", "application_number": "US-72341691-A", "description": "an embodiment of the present invention will be described with reference to the drawings hereinafter . fig3 illustrates a transversal filter in which the number of taps is six and the number of time - division multiplexed coefficients is two . an input terminal in1 of the filter is connected to receive a time - series input signal a ={ x ( i )