the circuit must be able to tolerate any number of idle symbols of course with some lower bound between packets in one implementation the phy device is able to automatically detect whether the incoming data stream is in a first or conventional serial gigabit interface mode or the second serial gigabit interface mode described herein the switch side indicates the first serial gigabit interface mode or the second serial gigabit interface mode but does not auto detect in 1000base x the idle order set normally runs with the disparity negative prior to transmitting a first idle order set such as the k28 5 d16 2 idle order set if a packet ends in a positive disparity then a second idle order set such as the k28 5 d5 6 idle order set is sent to make the disparity negative again afterwards k28 5 d16 2 is sent as long as there is idle on the line to keep the ending disparity negative on the switch side the k28 5 d16 2 idle order set is replaced by the k28 5 d1 2 idle order set when in the second serial gigabit interface mode if the phy device sees the k28 5 d1 2 idle order set three times in a row the phy.