the floating gate in order to reduce the resistive value which otherwise might be too large even for floating gates applying this structure to the leaky floating gate circuit will make the resulting circuit simpler since now only a single resistive connection is required to the floating gate as shown in fig7 the architectures described above are usable in both analogue and digital circuits in digital circuits an important use would be to allow the tuning of threshold voltages of the transistors assuming all devices are made with leaky gate structures the thresholds of the devices may be tuned to close to 0v allowing for much lower supply voltages supply voltages between 0 5 u2013 1 v have been demonstrated in standard high threshold cmos with more complicated uv based floating gate tuning techniques many different kinds of gates may be designed and it is anticipated that the area penalty for using these devices is small device count is usually reduced whilst stacked transistors may be replaced with a single transistor having dual control gates in conventional digital logic multiple input logic gates are formed typically by vertically stacking a number of n and p type transistors the minimum supply voltage is thus limited by the need to provide sufficient voltage headroom for these stacked devices however by using multiple input floating gate transistors we may reduce the stacking to only two stacked transistors one pmos on top of one nmos the multiple input logic gate functionality can then be implemented through exploiting the multiple input functionality of the floating gate transistors.