clock timer 238 outputs a pulse the next pulse will be triggered by the timer 238 upon the input of the fourth positive transition of the sixteen times clock signal the sixteen times clock signal is also provided as an input to the sample clock timer 244 the sample clock timer 244 receives four bits from the lower nibble of the eight bit timer latch 242 which controls the sample clock 244 pulse rate the value received from the timer latch 242 determines how many positive transitions of the sixteen times clock signal are required at the input to the sample clock 244 to trigger an output pulse from the sample clock timer 244 in the manner described above the output of the sample clock is provided to the microprocessor 210 for use during decoding of the frame information 45 and the interleaved information blocks the sample clock signal allows the microprocessor 210 to decode the demodulated data at 1200 bits per second regardless of whether the demodulated signal is 1200 baud 2400 baud or 4800 baud the sample clock signal is also provided to a sample register 250 of a sync2 correlator 246 the sync2 correlator comprises the sample register 250 which receives the demodulated signal as data and a reference register 248 which receives data from the eight bit data bus 211 the reference register 248 and sample register 250 feed error counting logic 252 the output of which is coupled to one input of a five bit magnitude comparator 254 the error counting logic 252 compares on a bit by bit basis the corresponding bits of the sample register and the reference register and generates a.