4 va x lt 47 12 gt in some examples the computing system 39 s virtual memory system may change its mappings between virtual memory addresses and physical memory addresses in such cases translation lookaside buffer invalidation instructions tlbis for the virtual memory addresses are issued e g by an operating system or by a hardware entity to the tlbs in the computing system i e the tlb 230 and instruction tlb 232 of each processing element 202 in general a tlbi instruction includes a virtual memory address and causes invalidation of any tlb entries associated with the virtual memory address that is when a tlb receives a tlbi for a given virtual memory address any entries in the tlb storing mappings between the given virtual memory address and a physical memory address are invalidated in some examples when a tlbi instruction is issued for a virtual memory address the tlbi instruction also causes entries in the walker cache that are associated with the virtual memory address to be invalidated referring to fig6 to do so when a tlbi is issued for a virtual memory address va tlbi a portion of va tlbi corresponding to the highest page table level i e l 3 being cached by the walker cache 232 is identified in this example the portion of va tlbi corresponding to l 3 is va tlbi lt 47 21 gt then for each entry in the walker cache 232 having a table level value 462 matching the highest table level value l 3 va tlbi lt 47 21 gt is compared to the cached virtual memory address portion 464 of the entry if va tlbi lt 47 21 gt matches the cached virtual memory address portion 464 of an entry the entry is invalidated e g by.