primary of temporary pipeline register before reading the data from the register file 180 mapping logic 120 also specifies write indices to register file 180 when temporary and final results are provided by the pipelines to write ports of register file 180 each write index of the write indices specified by mapping logic 120 indicates the primary register of the primary registers 130 or the temporary pipeline register of the temporary pipeline registers 140 to which a final or temporary result is to be written write indices are determined at the same time when read indices are generated by mapping logic 120 these write indices may be maintained in mapping logic 120 or sent along with the instruction to the execution pipeline for the instruction the addition of temporary pipeline registers 140 to register file 180 provides several advantages over the prior art in the first place the selector circuitry between the read ports of register file 180 and the execution stages of the pipelines are eliminated thus no matter how many pipelines there are in the processor or how many stages there are within a given pipeline temporary data will always be provided through the read ports of register 180 as though they were provided by primary registers 130 this technique in effect.