skilled in the art for an exemplary cell with 1255 ports it was found that the final size of the closure graph was 3140 but that the peak number of constraints was 7523 compared to the much longer original number of approximately 200 000 this method greatly reduces the amount of memory required the reduction of the temporary peak requires appropriate ordering of the ports during the iteration the order used is the reverse topological order relative to the floor vertex in the cell graph where only the arcs of positive weight are present the term reverse topological order is well known to those skilled in the art and need not be further discussed after the cells which include transistors contacts interconnections etc have been arranged in the desired tiled module the structure in the module is transferred into a mask suitable for pattern replication the finished mask usually comprises a patterned metal such as chromium on a glass substrate suitable and well known techniques are used to transfer the structure into the mask for example the entire glass substrate is coated with a metal and a resist is deposited on the metal portions of the resist are then selectively exposed to radiation such as an electron beam to form the desired pattern in the resist the pattern is then transferred from the resist to the metal by appropriate resist development and metal etching techniques fabrication of exemplary integrated circuits will typically require a plurality of such masks with different patterns integrated circuit fabrication techniques are well known to those skilled in the art and need not be described in detail each mask pattern is replicated on the wafer with a technique generally similar to that described for mask fabrication i e the wafer is.