e g al si 1 4 with a thickness of between 0 8 to 2 microns is deposited on the oxide layer 80 the metal layer 82 is deposited at a temperature of about 400 u00b0 c or thermally treated at about 400 u00b0 c to form silicon precipitates in the layer 82 5 the layer 82 is reactively ion etched to leave silicon nodules 84 on the oxide layer 80 with a size between 0 05 to 0 2 microns as shown in fig7 b 6 using the silicon nodules 84 as a mask the oxide layer 80 is reactively ion etched to form oxide islands 86 with a size between 0 05 and 0 2 microns as shown in fig7 c 7 the polysilicon layer 40 is then etched to a depth of about 4000 8000 angstroms using the oxide islands as a mask to form polysilicon pillars the oxide mask is then removed using hf content solution the resulting pillars 43 are shown in fig7 d in this manner the layer 40 forms an electrode of the most capacitor 8 the capacitor dielectric layer 42 see fig6 is formed on the modulated surface i e modulated with the pillars of polysilicon layer 40 the dielectric layer may be.