gate nand1 to an input of a second nand gate nand2 and to an input of a nor gate nor in addition to its input the delay device 4 has a non inverting output and an inverting output the non inverting output is connected to a further input of the nor gate nor and the inverting output is connected to a further input of the second nand gate nand2 an output of the nor gate nor corresponds to the output of the activation circuit 1 one input of the first nand gate nand1 is connected to an input of the activation circuit 1 which corresponds to the input 10 of the circuit configuration a further input of the first nand gate nand1 is connected to an output of the second nand gate nand2 the input signal es can be fed to the input of the activation circuit 1 the activation signal aks is present at the output of the activation circuit 1 the delay device 4 is connected to the logic gates nand1 nand2 and nor in such a way that in the event of a rising edge of the input signal es the activation signal aks follows the input signal es immediately but in the event of a falling edge of the input signal es the activation signal aks follows the input signal es with a delay by the delay time dt v a signal change at the input of the activation circuit 1 has no influence on the activation signal aks for the duration of the holding time dt h it is only a falling edge of the input signal.