volt for instance as shown in fig2 reset signal s r thereupon goes from a high level inactive state to a low level ov i e into an active reset state the computer to be reset will then be in a so called unconfigured reset original state ro original state ro is a rest state during which computer 110 neither reconfigures itself nor executes user programs this original state lasts for as long as reset signal s r is active the reset signal reassumes the inactive high level state once supply voltage u has reached the predefined voltage level again or exceeds it this change in the voltage level of reset signal s r will subsequently be denoted as reset start command this start command ends the reset original state of the computer and triggers the actual reset process r during which the computer configures itself with a predefined reset configuration in the following the method of the present invention for implementing resets with different reset configurations in master computer 110 and slave computer 120 will be discussed in greater detail with reference to fig1 to 3 fig3 shows the sequence of the method according to the present invention the starting point in method step s 1 first is the initiation of a reset procedure by a drop in the voltage level of reset signal.