430 goes high indicating c is the smallest input in similar fashion if lines 413 and 423 are low with line 403 high b is the smallest input while with lines 403 413 and 423 low a is the desired result the outputs of fig4 control the position of switches 224 324 and 281 381 which each may be implemented as a series of gates in a manner well known to those skilled in the art as discussed previously the luminance and chrominance predictions form the weighted sum of luminance or chrominance values respectively of picture elements neighboring the pel being processed a sum may have the value of only one other element if the 34 weights 34 of yet other elements are considered to be zero some possible configurations for predictors are illustrated in fig5 a and 5b in fig5 a a predictor including three one sample delay circuits 501 502 and 503 connected in series relation is shown if the luminance component l is input to circuit 501 then when l n arrives at the last state previous samples l n 1 l n 2 and l n 3 appear at the other respective delay circuit outputs these previous samples are combined in an adder 504 via weighting resistors 505 507 if the resistors have equal values then the prediction formed would be 1 3 l n 1 l n 2 l n 3 obviously unequal values would produce different predictions in like manner as shown in fig5 b the predictor may include both a delay circuit 510 having a one line delay and delay circuits 511 513 each having one sample delays here samples from the previous line l n 2 l.