therebetween it is noted that the gate 530 is formed over a thin silicon dioxide layer 532 as conventionally known in the art each of the high doped p and n regions 508 512 1 and 512 2 comprise a silicide layer 218 and a respective contact 221 a 221 c and 521 d disposed thereover as discussed above with respect to fig2 the contact 221 a of the p region anode 122 508 is coupled to the pad 148 of the ic the contact 221 c of the first n region cathode 124 512 1 is coupled to ground 126 furthermore the second n region 512 2 which functions as the drain of the nmos trigger device 505 is also coupled to the pad 148 of the ic via contact 521 d the gate 530 of the nmos trigger device 505 is also coupled to ground 126 referring to fig5 a at least one p region 526 defining a first gate g 1 is formed in the p well 206 proximate and in line e g axially in line with the first n cathode region 512 1 and second n drain region 512 2 that is the width of the first gate p region 516 is substantially the same as the width of the integrated nmos trigger device 505 in this fourth embodiment two p first gate regions 526.