these circuits on the other hand the address latch clock input is derived directly from the system clock signal clk control of the pipe latches pipe_latch 0 pipe_latch 1 and pipe_latch 2 is provided by the pipe latch control circuitry 61 each pipe latch is driven by a respective pipe latch enable signal latch_enx 0 latch_enx 1 and latch_enx 2 coupled to its latch input enable terminal the pipe latch enable signals are derived from a pipe counter 64 which produces three count signals count the pipe counter is a free running counter which resets its count based on the total number of pipe latches after a preset number of clock counts set by the system clock signal coupled to the pipe counter clock input terminal the output count signals from the pipe counter are coupled via count delay elements 66 to count synchronization latches 68 the outputs from the three latches 68 provide the pipe latch enable signal for clocking the appropriate pipe latch 56 the clock input enable terminal of the lathes 68 are coupled to the asynchronous control signal of the latency stage in the read path in this case signal iodb_readx of the rdbamp 54 to ensure the pipe latch is latched at the appropriate time alternatively a more accurate synchronization of the data iodb_readx and the cnt_del signals in latch 68 can be achieved as follows the count delay circuitry 66 could be segmented into multiple delay stages each receiving control logic enable signals such as.