which includes an 8 bit operation code op code such as a code lda to load an accumulator such as the data buffer 2 of fig3 and an 8 bit operand which in this example may be taken to be an address code identifying a ram address to be accessed namely in this example the instruction orders the contents of a specific ram address to be transferred or loaded into the accumulator in the conventional process of fig1 a the op code lda for the illustrated i e so labelled second instruction machine cycle is fetched before starting the first instruction cycle machine cycle this further specifying is not continued in the following the general term being left to stand alone in the next fetch cycle which is coincident with the onset of the illustrated first instruction cycle i e so labelled in the drawing data in the ram address identified by the operand is fetched the data fetched in the fetch cycle starting concurrently with the illustrated first instruction cycle and the op code lda fetched before the illustrated first instruction cycle are used in the illustrated this further specifying is also not generally continued in the following second instruction cycle in the conventional process set forth above a program counter is incremented by one at the end of each instruction cycle therefore.