cross interrogate until pending stores in processor 103 cpy are drained when there is no pending stores for line a existing in processor 103 cpy processor 103 cpy at this time should naturally be accepting the release request processor 103 cpy will update its directory with no more exclusive rights and send back an acknowledgement to sc 0 101 3 once the acknowledgement is received the sc 0 101 will update its directory update to indicate that line a is now exclusive to u201c no one u201d 4 the software demote process is thus accomplished this state of exclusive to no one is equivalent to a shared or read only state with respect to how if affect exclusive xi activities concerning this line now as seen in fig4 if another processor 107 cpx requests line a exclusively 1 the sc 1 102 can quickly request the line exclusively from sc 0 101 2 4 and then reply to the requesting processor 107 cpx with an exclusive response 5 6 without acquiring any delay for cross interrogation towards processor 103 cpy this reduction of delay could be even more apparent in a system if the storage controllers for nodes 101 102 are on a different chip s than the processors where the cross chip communication is now removed to further describe a variant implementation of this demote instruction we will illustrate with a system where there is one private level 2 cache l2 per processor this is shown in fig5 each processor 103 108 in this system has a private l2 200 in this design when processor 103 cpy sends a demote request to.