transmitter 40 receives the bits of the synchronization field from the data recovery circuit 34 before the other bits of the frame thus the transmitter 40 does not regenerate the synchronization field but instead the transmitter 40 relays the buffered synchronization field to the serial bus 50 the transmitter 40 then receives the remaining bits of the frame and communicates these bits to the serial bus 50 referring to fig3 in some embodiments the data recovery circuit 34 may include an analog to digital a d interface 60 that receives a clock signal called clk 1 from a clock line of the serial bus 32 and other signals from data lines of the serial bus 32 in this manner on each cycle of the clk 1 signal the a d interface 60 samples and converts two analog data signals from the serial bus 32 into two bits that are received by a fine adjustment delay line 63 the delay line 63 delays the bits to adjust the phase between the clk 1 clock signal of the serial bus 32 and the clk 2 clock signal of the serial bus 50 the phase adjusted bits subsequently pass into a coarse adjustment delay line 65 a delay line that delays the bits by a multiple number of clk 2 cycles to accommodate an overall difference in the data rates between the incoming and outgoing data serial buses 32 and 50 in this manner the coarse adjustment.