a system clock one exception in a sdram being a clock enable signal as used during power down and self refresh modes the address operations of a sdram are somewhat different from those of an asynchronous dram in an asynchronous dram once row and column addresses are issued to the dram and the row and column address strobe signals are deactivated the dram 39 s memory is automatically precharged and available for another access a sdram on the other hand requires a separate command to precharge a row of storage cells within a memory array assuming one of the memory cells in a sdram has been addressed that page remains active even after the cell has been accessed this occurs because an internal row address strobe is generated and maintains the active state of the addressed page as a result the page remains open until a precharge command is used to deactivate the open page and put the memory device into a standby mode thus to accomplish a sdram data transfer operation an active command is issued to register a row address designated by the address signals e g a 0 a 14 for a 2 15 page memory device and a memory page is selected to be accessed data is then transferred to or from the memory page by registering the column address through a write or read command respectively other memory pages may be subsequently accessed but a precharge command is needed with the present embodiment before registering another row or page in that memory device as used herein a u201c page u201d is that portion of a.