preferred embodiment the non linear adding is implemented in a prom programmable read only memory select decoder circuit 118 and a prom array consisting of proms 121 128 the prom selected decoder circuit 118 receives the first three significant bits a0 a1 and a2 of the first pcm signal and outputs a select signal on one of 8 possible lines s1 s8 the decoding employed is a binary to decimal conversion thus only one select line of s1 s8 is enabled for any given logical state of a0 a1 and a2 each of the lines s1 s8 is connected to one of the proms 121 128 except for the least significant bits the remaining bits a3 a4 a5 and a6 of the first pcm signal and the bits b0 b6 of the second pcm signal are used to address a location within one of the selected proms 121 128 the combination of these inputs with a signal on one of the s1 s8 lines uniquely selects one address location within the prom array the addressed location contains the non linear addition of the pcm address bits the outputs o1 o8 of the proms are driven by appropriate driver circuits 130 for outputting a third pcm signal 138 wherein the bits are provided by the outputs o1 o8 an adjusting means 132 which includes a.