16 of fig1 in accordance with one embodiment of the present invention the illustrated portion of debug circuitry 16 includes terminal access circuitry 48 which is bi directionally coupled to terminals 22 terminal access circuitry 48 is bi directionally coupled to circuitry 50 by way of conductors 60 bus 20 is also bi directionally coupled to circuitry 50 circuitry 50 illustrated in fig2 includes debug protocol circuitry 42 transmit and receive circuitry 44 trace history buffer 46 and breakpoint and capture circuitry 40 which are all bi directionally coupled by way of conductors 62 alternate embodiments of the present invention may couple the circuitry within debug circuitry 16 in other ways than shown in fig2 in one embodiment of the present invention breakpoint and capture circuitry 40 includes control circuitry 29 registers 30 trigger circuitry 32 multi function debug counters 34 combining logic 36 and action select and control logic 38 debug protocol circuitry 42 implements a protocol for the input and output of data through conductors 60 and bus 20 the present invention is completely independent of the protocol used the protocol can be any known or yet to be created protocol alternate embodiments of the present invention may use both conductors 60 and bus 20 just conductors 60 or just bus 20 the transmit and receive circuitry 44 is used to transmit data between bus 20 conductors 62 and conductors 60 trace history buffer 46 may be used in some embodiments of the present invention to save software program u201c history u201d such as prior program execution memory addresses control circuitry 29 provides for the control and the interaction of the blocks within breakpoint and capture circuitry 40 and also may be used to control transmit and receive circuitry 44 and.