logic 22 and the analog input output i o circuitry interface such as the module 60 is significantly improved as compared to conventional memory interfaces the module 60 contains data bit transmitters 80 one exemplary data bit transmitter 80 being depicted in detail in fig2 each of which is associated with a data bit line of the memory bus 24 and each of which receives an associated set of data bit signals called u201c ss_data 0 3 u201d from the hsio logic 50 each data bit transmitter 80 generates via an output driver 83 its data bit signal on one of the external data bit pad terminals of the module 60 which is connected to a corresponding data bit line or trace of the memory bus 24 each of the data bit transmitters 80 also receives the ss_clock signal from the hsio logic 50 the module 60 also includes a clock transmitter 84 which has the same general design as the data bit transmitter 80 with like reference numerals being used to depict similar components the clock transmitter 84 receives clock data indicative of the clock signal to accompany the data on the memory bus 24 from the hsio 50 as well as the ss_clock signal the clock transmitter 84 generates an outgoing clock signal via the output driver 83 that appears on the external clock pad terminal which is connected to a corresponding clock line of the memory bus 24 in general each transmitter 80 84 has a relatively small fifo 82 a fifo having a depth of two for example which stores the incoming data from the hsio logic 50 as described below clock signals that control the communication of data from the fifos 82 to the memory bus 24 are adjusted for purposes of de skewing.