connected each of the 48 global vertical conductors 12 in a column is connected to one of the output terminals of the 16 demultiplexers 26 in each logic array block in the column similarly each of the 16 multiplexers 28 associated with each logic array block 16 has three input terminals connected to the global vertical conductors 12 in the column preferably the global vertical conductors 12 in each column are arranged in two sets of 24 conductors each a first set on the left hand side of logic array block 16 is connected to the first eight macrocells in the block a second set on the right hand side of logic array block 16 is connected to the remaining eight macrocells in the block in order to configure the programmable logic device 10 to perform a desired logic function a user programs macrocells 22 multiplexers 20 and 28 and demultiplexers 26 using any convenient conventional programming technique the programmable logic device 10 may contain programmable logic elements such as erasable programmable read only memory eprom transistors static random access memory programmable fuses antifuses ferro electric elements or any suitable type of storage cell preferably the programmable logic device 10 is based on electrically erasable programmable read only memory e 2 prom transistors because macrocells 22 are connected to global horizontal conductors 14 via output drivers 24 multiplexers 28 and tristate output drivers 30 the macrocell outputs of one logic array block 16 are available as inputs to other logic array blocks 16 via the multiplexers 20 connected to the other blocks further when it is desired to connect the logic of one row to another output signals from an.