signal is output to a corresponding one of the decoder lines 6 that is connected to the activated decoder note that a signal to be output from the decoder group 34 is a pulse signal in addition a signal output from the decoder group 35 or 36 is a pulse signal or a data type signal the equalizing and floating unit 32 receives the equalizing signal 33 and sets the decoder lines 6 to the floating state with respect to the decoders the equalizing and floating unit 32 then equalizes the voltages of decoder lines 6 which belong to the same decoder group referring to fig3 the equalizing and floating unit 32 will be described in detail fig3 illustrates equalizing and floating circuits 56 connected to the decoder group 35 of the row decoder circuit 7 fig3 illustrates the decoder lines 6 the equalizing and floating circuits 56 connected to the decoder group 35 of the row decoder circuit 7 the equalizing signal 33 transfer gates 41 42 43 44 45 46 and 47 and inverters 40 48 49 50 51 52 53 54 and 55 as can be seen from the figure the equalizing and floating circuits 56 corresponding to the decoder group 35 having four decoders are arranged between the row decoder circuit 7 and the decoder lines 6 an equalizing circuit which constitutes the equalizing and floating circuits 56 is composed of the transfer gates 41 42 and 43 and the inverter 40 when receiving the equalizing signal 33 the equalizing circuit causes the transfer gates 41.