the present invention relative to the prior art method is that the present invention only moves cells containing pointers instead of the entire instruction thus the present invention is much easier for implementation while providing all the advantages of the prior art method fig5 is a schematic drawing illustrating an example of the instruction issue and pointer cells compression during one clock cycle according to a preferred embodiment of the present invention again the compression technique is also well known in the art thus it will not be described in detail here fig5 shows that there were four cells in the linear array containing pointers linking to ram entries that stored the 34 br 34 34 iu 34 34 fpu 34 and 34 ls 34 instructions respectively that were ready to issue fig5 also shows cells 1 through 6 that were linking to login ram entries but were not ready for issue after these instructions were issued these entries became empty entries and the corresponding cells in the linear systolic array also became empty during the same 34 shifting 34 operation cell 1 i e the content of cell 1 moves into cell 34 br 34 i e the cell that contains pointer linking to instruction 34 br 34 cell 2 moves into cell 1 which recently became empty.