after photoresist not shown has been coated over the entire surface this photoresist is patterned to a shape of a control gate 15 of the memory cell transistor 11 see fig2 a in the memory cell region and also a shape of a gate electrode 16 of a peripheral transistor 12 see fig2 b in the peripheral circuit region then by using the patterned photoresist as a mask an anisotropic etching is carried out with respect to the polycrystalline silicon film 7 the ono film 6 and the polycrystalline silicon film 5 as a result a floating gate made of the polycrystalline silicon film 5 and a control gate made of the polycrystalline silicon film 7 are fabricated in the memory cell region whereas a gate electrode of the peripheral transistor which is made of the polycrystalline silicon films 5 and 7 is formed in the peripheral circuit region thereafter a step of forming impurity diffusion layers not shown serving as sources and drains of the memory cell transistor 11 and the peripheral transistor 12 by ion injection using the control gate and the gate electrode as a mask and further a step of forming an interlayer insulating film not shown which covers the overall areas of the memory cell transistor 11 and the peripheral transistor 12 are carried out to thereby accomplish the eeprom as described above in accordance with this first embodiment phosphorous is introduced into the polycrystalline silicon film 5 at a relatively low concentration by way of the ion injection method and the ono film 6 is left at least on the polycrystalline silicon film 5 of the memory.