ferroelectric memory of this embodiment comprises a sense amplifier circuit 5 a voltage shift circuit 7 a negative voltage generating circuit 9 a vth generating circuit 11 a feedback circuit 13 a memory cell region 15 an n channel mos transistor t 1 a p channel mos transistor t 2 a capacitor c 5 and switches 23 a and 23 b the sense amplifier circuit 5 comprises n channel mos transistors 12 17 18 a and 18 b p channel mos transistors t 8 to t 10 a capacitor 19 and nodes na and nb the voltage shirt circuit 7 comprises a gate circuit 20 an inversion circuit 21 and a capacitor c 6 the feedback circuit 13 comprises capacitors c 1 and c 2 an inversion circuit 24 and a resistance element 25 the memory cell region 15 includes a bit line bl a bit line stray capacitance c bl a ferroelectric capacitor cf and a plate line cp the bit line capacitance c bl indicates the parasitic capacitance of bit line bl represented as an equivalent circuit in the circuit diagram the capacitor c 6 included in the voltage shift circuit 7 is connected in parallel with the capacitor c 5 and the output node of the voltage shift circuit 7 is connected to the node na of the sense amplifier circuit 5 the negative voltage generating circuit 9 generates a negative voltage v mn and supplies it to the capacitor c 5 via the switch 23 b the vth generating circuit 11 generates a threshold value voltage vth and supplies it to the gate of the p channel mos transistor t.