third data stored in the selected multiple value memory cell 920 using the sense amplifier 910 through the bit line 970 step 1065 transfer the data stored in the sense amplifier 910 to the data latch 940 through the bit line 970 step 1070 transfer the data stored in the data latch to sram_r 990 as bit 1 925 of the two bit data 945 step 1080 output the two bit data 945 stored in the sram_r 990 and sram_l 980 through input output ports 915 please refer to fig1 together with fig9 fig1 shows the voltages of the word line 960 coupled to the selected multiple value memory cell 920 during a read operation according to the first embodiment of the present invention the vertical axis represents the voltages of the word line 960 coupled to the selected multiple value memory cell 920 while the horizontal axis represents the time in the read operation from fig1 it is known that word line 960 during the read operation is first charged to voltage vrw 1 then charged to voltage vrw 3 and then discharged to voltage vrw 2 the voltage sequence described above is different from the prior art and eliminates the.