of the circuits of the sense amplifier but advantageously exert a beneficial influence on the semiconductor fabrication processes after all the gates are completely disposed as previously described in fig1 the rest of the layout of the semiconductor device can be arranged according to the conventional or any other layout method in other words according to the layout method of the sense amplifiers of the present invention shown in fig1 there are the gates which perform actual operations of the sense amplifier while the dummy gates are positioned between or outside those actually operating gates without making any influence on the actual operations of the sense amplifier however the installation of the dummy gates minimizes the variances in the process deviations which may occur in the photo and etching processes for the production of the semiconductor device fig1 through 17 illustrate a layout method of the sense amplifier shown in fig4 in accordance with another embodiment of the present invention in fig1 the sources drains and gates of the pmos transistors p 1 p 2 p 3 are respectively denoted with p 1 s p 2 s p 3 s p 1 d p 2 d p 3 d and p 1 g p 2 g p 3 g while the sources drains and gates of the nmos transistors n 1 n 2 n 3 n 4 are respectively denoted with n 1.