detection circuit 350 and to a multiplexer 358 an additional input to the multiplexer 358 is received from the program counter 352 as controlled by the output of an and circuit 362 which has its inputs coupled to microcontroller register bus 366 and an output of delay counter 360 the output of the and circuit 362 is supplied to a transmission gate switch 364 which couples the microcontroller register bus 366 to the instruction ram 332 the delay counter 360 has an additional output provided as input to program counter 352 the timing error detection circuit 350 is controlled by a timing error limit register and the ssm fnd 346 signal from the servo decoder 124 the timing error detection logic 350 is loaded with a predetermined count upon receiving an 34 enable phase error counter 34 signal from the instruction decoder 354 the counter counts down until ssm fnd 346 signal stops the counter the output of the counter is continuously compared against the value in the phase limit register if the phase error register exceeds the value in the phase error limit register an interrupt is generated to the microcontroller 188 this interrupt is controlled by the microcontroller interrupt enable register one of microcontroller registers 334 the servo microsequencer 126 may be started in several ways in operation the servo microsequencer 126 begins when a strt sms signal is asserted which occurs when the start ssm search bit of the decoder configuration register is set and the servo decoder 124 has detected a ssm 540 it is stopped when the start ssm search bit.