bits of data and the minus portion is utilized for even bits of data expansion circuit 60 converts the received 40 mhz data waveform into two separate 20 mhz received data words one half of the received data word contains the odd bits of the transmitted data word and the other half of the received data word contains the even bits of the transmitted data word turning to the plus portion of data expansion circuit 60 the output of positive threshold detector 56 is connected to the clock input of d type flip flop 62 the input of five tap fifty nanosecond delay line 66 and one input of two input and gate 74 via line 57 the q output of flip flop 62 is connected to the d input of flip flop 64 the d input of flip flop 62 is connected to a logic one level and the q output of flip flop 64 is connected to the clear inputs of flip flops 62 and 64 in this configuration a positive transition of the filtered received data signal at the input of threshold voltage detector 56 will cause the q output of flip flop 62 to change from a logic zero to a logic one forty nanoseconds later a low to high transition will appear at the forty nanosecond delay output of delay line 66 which clocks flip flop 64 thereby clearing flip flops 62 and 64 as a result the q output of flip flop 62 represents the expanded odd bits of the filtered received data waveform i e the pulse width of each odd data bit is expanded to approximately forty nanoseconds as shown in fig5 line 4 the.