the fig8 timing diagram this factory present pulse repetition rate defines the overall t 0 to t 4 time interval a timing control circuit potentially implemented by a microprocessor maintains switches s 1 and s 2 in the open condition during the t 3 to t 4 time interval and disables the power supply until the desired t 0 to t 4 time interval has been completed at time t 0 the power supply will be reactivated to recharge the first and second capacitors to the power supply output voltage referring now to the fig9 schematic diagram the fig2 circuit has been modified to include a third capacitor and a load diode or resistor connected as shown the operation of this enhanced circuit diagram will be explained below in connection with fig1 and the related more detailed schematic diagrams referring now to the fig1 electrical schematic diagram the high voltage power supply generates an output current i 1 which charges capacitors c 1 and c 3 in parallel while the second terminal of capacitor c 2 is connected to ground the second terminal of capacitor c 3 is connected to ground through a relatively low resistance load resistor r 1 or as illustrated in fig9 by a diode the first.