u201d in the clock cycle c 9 in order to be kept in u201c l u201d during the period between the clock cycles c 11 and c 12 at least fig8 c also the scan shift control signal ssc is set to u201c l u201d in the clock cycle c 9 after the completion of the shifting operation fig8 b thus the and circuit 36 outputs u201c h u201d and the and circuit 37 outputs u201c l u201d fig8 d and 8e that is during the period between the clock cycles c 11 and c 12 the selecting circuit 21 selects the output signal of the flip flop 13 and the selecting circuit 22 selects the output signal of the nor circuit 34 in the clock cycle c 9 the flip flops 11 to 17 output u201c h u201d u201c h u201d u201c h u201d u201c h u201d u201c h u201d u201c l u201d and u201c l u201d from the output terminals q respectively thus the output of the nand circuit 31 is set to u201c l u201d the output of the nand circuit 32 is set to u201c l u201d and the output of the nand circuit 33 is set to u201c h u201d fig8 k 8 p and 8 u thus the nor circuit 34 outputs u201c l u201d fig8 v here the scan shift control signal ssc is set to u201c l u201d and the flip flops 11 to 17 are set to the states to latch the signals supplied to the data input terminals d in synchronization with the clock signal clk in the clock cycle c 11 in synchronization with the rising edge of the clock signal clk.