case there would not be any resource conflict any more except instructions with an ri all other iram access related instructions are executed only within their own respective instruction cycle all indirect addressing instructions are actually converted into direct addressing instructions when the instruction cycles are started except ri early fetching and ret reti a normal iram read access happens only in the first phase of a cycle and a write access happens only in the second phase of a cycle within the instruction cycle of an instruction as a maximum 2 times an iram access occurs the access mode can only be read only write only or read and write from the above it follows that an iram resource conflict u2014 where at the same time or the same clock period or periods defined by the above clock signal clk signal a read access and a write access occurs u2014 only happens in a special case u201c conflict case u201d with an indirect addressing instruction when in its previous instruction there is a write access to the iram in the present embodiment in the above u201c conflict case u201d the above dual port memory device 6 b here the dual ported array of flip flops 6 b of the data memory 6 is accessed but not the single port ram 6 a in particular single port sram 6 a of the data memory 6 as the array of flip flops 6 b is dual ported at the same time or substantially the same time or the same.