is subtracted from the output of latch 38 the previous interval ti 1 in a subtractor 40 upon its enablement the subtractor is enabled by the rising edge of the output of and gate 50 after it has been delayed by a slight time delay 44 the delay is to allow the latch 42 to settle before its output is used as the minuend of the subtractor 40 a third counter or interval counter 26 is provided to count the high speed vernier clock signal vclk provided to its input clk from terminal 27 the interval counter 26 measures the time in increments of the vernier clock during which it is enabled by an interval count enable signal ice the interval count enable signal ice is the output of the q terminal of an r s flip flop 28 the ice signal is generated as a high logic level when the flip flop 28 is set by a low to high transition of the output of and gate 52 the counter 26 counts until the flip flop 28 is reset by the rising edge of the output of and gate 50 which clears the q output and disables the counter the output of the interval counter an interval count signal ict is a digital number which is input to one terminal of a subtractor 30 to form the minuend of a second subtraction the other input forming the subtrahend of the subtractor 30 is the output of the subtractor 40.