masking methods the fault coverage is very high and independent of the number of scan chains this indicates that a scan chain configuration which maximizes compression ratio can be chosen without compromising test quality an example how the invention is included in the test architecture is given in fig1 a new compactor solution for very high compaction ratios gt 200 u00d7 in presence of many x values without compromising test quality was presented this is accomplished by a highly effective x masking register which only targets scan chains actually capturing x values the x masking information can be loaded in parallel using the dut 39 s scan chains and built in decompressor logic a novel technique uses ate timing flexibility to eliminate the need for a mask control channel and increase the overall compaction ratio the compactor architecture is design independent due to its regular structure it can readily be implemented as a push button solution the proposed single output compactor is very well suited for multi site testing enabling compression ratios of u02dc 500 u00d7 in 4 dut multi site testing setups the features disclosed in this specification claims and or the figures may be material for the realization of the invention in its various embodiments taken in isolation or in various combinations thereof m bushnell and v d agrawal u201c essentials of electronic testing for digital memory and mixed.