gate 218 while the remaining input of nor gate 218 is coupled to an asynchronous reset signal setting the asynchronous reset signal to a logic low sets the output values of the master and slave flip flops to zero regardless of the state of the clock edge however while the asynchronous reset signal remains at a logic high the output of nor gate 218 is held at a logic low which causes nor gate 208 to operate as an inverter clocked inverter 207 turns off causing master flip flop 215 to operate as a transparent latch tracking the value of the input of inverter 203 slave flip flop 216 in contrast holds its previously stored value regardless of the value at the input of inverter 203 transfer gate 209 is turned off isolating the output of master flip flop 215 from the slave flip flop 216 the two inputs of nand gate 211 serve as the inputs to slave flip flop 216 one input of nand gate 211 is coupled to the output of slave flip flop via transfer gate 209 while the remaining input of slave flip flop 216 is coupled to the asynchronous reset signal the asynchronous reset signal remains at a logic high unless a reset is initiated by a user a program or an external signal while the asynchronous reset signal remains at a logic high nand gate 211 operates as an inverter clocked inverter 210 turns on providing a feed back.