the connection of the collectors of the transistors 402 and 404 in the power amplifier module 200 the collectors of the transistors 202 and 204 are coupled together and to the voltage source vcc 1 in the power amplifier 400 the collectors of the transistors 402 and 404 are coupled to the voltage vcb the pinout of the power amplifier module 400 has been modified so that a u201c spare u201d ground pad main ground is the center island of the power amplifier 200 shown in fig3 now couples to the voltage vcb as shown in fig5 in the arrangement of the power amplifier module 400 the voltage vcb is held at 2 5 volts or higher such as the battery voltage and the voltages vcc 1 and vcc 2 are controlled down to a voltage of 0 5 volts in another embodiment the voltage vcb can be connected to the vref terminal which for example may be kept at a voltage of 2 7v or higher at all times in this configuration a pin configuration that is the same as shown in fig3 may be used with the new bias circuitry with this invention provided that the total current at vref terminal meets system specification this embodiments allows a package pin configuration to remain constant but with different connections inside the package fig6 is a schematic diagram illustrating a power amplifier module 600 including an emitter resistor and a base resistor a power amplifier 600 comprises a plurality of transistors 601 through 603 a.