one redundancy decision circuit is provided in the memory control circuit therefore it is possible to reduce the area and cost of the memory 2 from those in the conventional address conversion system where the redundancy decision circuit is provided for each of the plurality of memories in the address conversion system according to the illustrated example of the present invention before an access request is sent to the memory 2 the redundancy decision circuit determines whether the requested physical address is a normal address or a redundant address therefore the memory 2 does not have to operate respective circuits for accessing the normal address and for accessing the redundant address when the requested physical address is a normal address the memory 2 can operate only one circuit for accessing the normal address when the requested physical address is a redundant address the memory 2 can also operate only one circuit for accessing the redundant address as a result the power consumption of the address conversion system can be reduced from that of the conventional address conversion system which is required to operate both of such circuits in the above described example the memory 2 is a synchronous type memory which operates in synchronization with a clock signal but the present invention is not limited thereto for example the memory 2 may alternatively be a non synchronous type memory moreover in the above described example the redundancy decision circuit is provided in the memory control circuit but the present invention is not limited thereto for example the redundancy decision circuit may alternatively be a circuit separate from the memory.