interlayer insulating layer 161 is formed by depositing an oxide layer over a semiconductor substrate not shown divided into a pixel array section p and a logic circuit section l the interlayer insulating layer 161 is planarized by a chemical mechanical polishing cmp process the substrate can be formed thereon with interconnections formed in a multi layer structure and electrically connected to each other through contact plugs transistors controlling a signal and r g and b photodiodes sensing red r green g and blue b signals afterwards a metallic material for example aluminum is deposited over the interlayer insulating layer 161 by sputtering silicon nitride sin or sion may be deposited over the metallic material by means of physical vapor deposition pvd chemical vapor deposition cvd or atomic layer deposition ald then the two materials the metallic material and the silicon nitride are simultaneously patterned by a photo etching process in this way a pad electrode 153 is formed in the logic circuit section l the pad electrode 153 is formed only in the logic circuit unit l since the pad electrode 153 is a power interconnection that receives signals from an external driving circuit the thickness thereof is large as an example while the metal interconnection provided between interlayer insulating layers might be 1 500 to 4 000 u00e5 thick the pad electrode formed in the logic circuit unit might be 3 000 to 5 000 u00e5 thick a barrier layer may be formed under the pad electrode the barrier layer may be selected from a tin ti stacked layer or a layer of ta tan wn tac wc tisin and tasin an oxide layer is deposited over the entire surface including the pad electrode 153 the surface of.