interpolator 204 also changes the change in input impedance results in an amplitude and phase variation of the input clock signal 202 based on the impedance at each input 208 212 thus as the phase of the interpolator 204 is changed by the control 216 the amplitude and phase of the input clock signal 202 also varies this in turn results in a change in the delay 224 between the two clock signals provided to the two inputs 208 212 the delay 224 is important because it is used to generate the predetermined number of output phases fig3 shows a block diagram of a cdr circuit 300 in accordance with an embodiment of the present invention a reference clock signal 304 provides the input clock signal to two interpolators 308 a 308 b each interpolator 308 a 308 b has an a input e g a first a input 312 for interpolator 308 a and a second a input not shown for interpolator 308 b and a b input e g a first b input 316 a for interpolator 308 a and a second b input 316 b for interpolator 308 b each interpolator 308 a 308 b also includes a z output 320 a 320 b and a control 322 a 322 b respectively in accordance with an embodiment of the present invention clock signal 328 is provided to the a input of each interpolator 308 a.