34 state to the logic 34 high 34 state and the logic 34 high 34 signal of the node n23 becomes the logic 34 low 34 state through the inverter 216 at this time the nodes n25 and n26 continue to be maintained to the logic 34 high 34 state after that since at the point t6 the node n23 and the node n26 are all logic in the 34 high 34 state a node n27 that is the output of the nand gate 231 is in the logic 34 low 34 state a node n28 that is the output of the nor gate 232 is in the logic 34 high 34 state a node n29 that is the output of the nand gate 233 is the logic 34 low 34 state and the logic 34 high 34 signal of the node 25 n25 is changed to the logic 34 low 34 state after being delayed during a given period of time t6 t5 e g 100 ns through the delay circuit as shown in fig3 f thereby the node n26 is changed from the logic 34 high 34 state to the logic 34 low 34 state thus the actuating signal is changed from the logic 34 high 34 state to the logic 34 low 34 state after that as at the point t3 the sc which was changed from the logic 34 low 34 state to the logic 34 high 34 state to be applied at the point t7 after a delay of loons is inverted into the logic 34 low 34 state through the inverter 20 to be applied to the pulse generator.