a memory cell of memory 150 corresponding to the test address the comparator 140 compares the test data di with memory data do read from the memory 150 to produce a detection signal p f pass fail the detection signal p f is applied to the bist controller 110 the detection signal is active depending on a predetermined condition for example the detection signal may be active upon coincidence of the two data dl and do and inactive when the two data dl and do are not coincident in the exemplary embodiment the address generator 120 is constructed to generate 64 2 6 address patterns with the 6 bit address bits add lt 5 0 gt by using the lfsrs 122 and 124 and the lfsr controller 126 but it is understood that the number of the address patterns can be adjusted based on the number of address bits advantageously the two lfsrs can be implemented to produce the 64 address patterns and perform a check operation for a normal mode and a test mode by a segment unit without preliminary evaluating operations of 64 lfsrs the address generator 120 may comprise a plurality of serial connected lfsrs comprising the same number of output bits or the different number of output bits in general a lfsr can advantageously produce a desired amount of data combinations.