pull up transistor and a second pull down transistor are connected in series between the two nodes of the power supply their common connection node being connected to the output node a control circuit provides an output indicating when the supply voltage is below a predetermined level a control circuit is responsive to the output of the control circuit to control the voltage at the gates of the second pull up transistor and the second pull down transistor to provide the logic level at the output node only when the output of the control circuit indicates when the supply voltage is below the predetermined level application_number US 2545504 A description fig1 is a circuit diagram of a typical prior art general purpose output buffer an enable signal en and an input signal in are provided as inputs and an output signal out is provided as an output an nmos driver transistor t 1 and a pmos driver transistor t 2 are connected in series between a power supply having a voltage v cc and ground as shown a nor gate 1 a nand gate 2 and an inverter 3 are interconnected as shown and operate in conjunction with signal en to provide an enable function for the circuit when the circuit is enabled a high value of in causes transistor t 2 to turn on and transistor t 1 to turn off thus driving a high value of out at the output conversely.