with the output signal q 2 from the flip flop circuit 108 however in the second embodiment as shown in fig4 regulation of the data transfer time is performed by comparing a test pattern signal with a signal resulting from sending the test pattern signal generated at the logic circuit 401 on the sending side to the logic circuit 402 on the receiving side the logic circuits on both the sending and receiving side include test pattern generator circuits 414 and 415 respectively that generate the test pattern signal a common standard signal sync is used for initializing the test pattern generator circuits on the sending and receiving sides and is synchronized with the generated test pattern signal fig4 includes a logic circuit 401 on the sending side and a logic circuit 402 on the receiving side and shows an embodiment of the circuits 401 402 in the form of integrated circuits the logic circuit 401 includes a flip flop circuit 403 and a driver circuit 404 for signal transfer the logic circuit 402 includes a transferred signal input circuit 406 a variable delay circuit t 1 that adjusts the delay time of the transferred signal 407 and a flip flop circuit 408 there is a signal transferring circuit 405 between the logic circuits 401 and 402 a system clock signal clk is supplied from a common clock signal source 409 to the logic circuits 401 and 402 and in particular to the flip flop circuits 403 and 408 the signal is transferred in synchronism with the system clock signal clk according to the present invention as shown in fig4 the generated test pattern signal is initialized and the test pattern generator circuits 414 and 415.