image data odt is output at the output terminal 21 in addition the ring buffer 105 generates an output image data enable signal ohden indicating the effective period of the output image data odt and outputs the signal at an output terminal 22 moreover a clock which drives the read side of each of the read counter 107 and ring buffer 105 is output as an output transfer clock dclk at an output terminal 23 the image data processing block 100 a further has an output terminal 24 and an output terminal 25 the output terminals 24 25 are used when the image data processing block 100 a is used as a master and are not used when the processing block 100 a is used as a slave when the image data processing block 100 a is used as a master the timing control section 108 outputs a master image data enable signal imhedn at the output terminal 24 at the output terminal 25 an internal clock iclk is output as a master image read clock imclk in fig3 there are provided a plurality of circuits each similar to the image data processing block 100 a and these circuits are connected to.