keeper device 126 includes a floating body nfet element for helping power clamp element 128 strongly conduct current during negative mode esd stress events each inverter 124 u2032 and 124 u2033 includes a floating body pfet element 134 chained to a floating body nfet element 136 during a negative mode esd stress event circuit 100 performs in a similar manner to the example described above for floating body nfet based circuit 20 as well known to one of ordinary skill in the art however keeper device 126 is configured with a floating body nfet element with the gate terminal at gnd and the drain terminal at vdd to complement the floating body pfet element of power clamp element 128 such that keeper device 126 pulls up during negative mode esd stress to assist power clamp element 128 in yet another embodiment a tied body nfet based power clamp circuit 200 is illustrated in fig4 circuit 200 includes an rc delay or triggering element 222 having a resistor 230 connected in series to a capacitor 232 at a node 238 rc delay element 222 is connected in series to a plurality of serialized inverters 224 which is connected in series an esd triggered keeper device 226 and a power clamp element 228 a power supply for circuit 200 is typically supplied by a voltage supply referred to as vdd in the embodiment illustrated in fig4 power clamp element 228 includes a tied body nfet based element with the body tied to the source terminal for conducting current during normal operation and positive mode esd events in a similar manner to the example described above for power clamp circuit 20 as well known in the art keeper device 226 assists power clamp element 228 to.