computer system 100 host processors 102 are connected to a sequence of components beginning with a memory request unit 104 followed by a memory controller 106 memory controller 106 is followed by a system memory 108 host processors 102 use this sequence of components to access memory locations included in system memory 108 as part of these accesses host processors 102 send virtual memory access requests to memory request unit 104 memory request unit 104 translates the requests into corresponding physical memory access requests the physical memory access requests are then passed to memory controller 106 memory controller 106 then accesses system memory 108 to perform the requested operations for the described embodiment memory controller 106 and system memory 108 support a range of page types including tiled and linear pages memory controller 106 and system memory 108 also support a range of page sizes for both tiled and linear pages memory controller 106 also functions as an interface that allows other components to access system memory 108 in fig1 memory controller 106 provides this type of interface to graphics processor 110 and input output controller 112 preferably graphics processor 110 performs the majority of its processing using the memory included in system memory 108 this avoids the delays that result if graphics primitives or data are moved from system memory 108 to graphics processor 110 input output controller 112 functions as a channel allowing.