asic 34 delay 7 is the setup time of asic 34 and delay 8 is the hold time of asic 34 as seen above the read budget of circuit 32 produces a maximum read cycle frequency 115 3 mhz the calculation of the write budget of circuit 32 also starts at buffer 42 delay 9 is the output to output skew of clock buffer 42 and corresponds to delay 1 in the read budget delay 10 represents tpd skew of clock buffer 50 of asic 34 and corresponds to delay 6 in the read budget delay 11 is the tpd skew of bus driver 52 of asic 34 delay 12 is the delay associated with the dimm backplane and corresponds to delay 5 of the write budget delays 14 and 15 are the setup time and the hold time respectively of the sdram ics such as sdram 46a delay 16 is the tpd skew of clock buffer 44 and delay 17 is the tpd skew of a dimm clock buffer such as buffer 48 as seen above the write budget of circuit 32 produces a maximum write cycle frequency 106 1 mhz which is the maximum frequency at which circuit 32 may operate fig4 is a block diagram of a memory system 72 in accordance with the.