shown in line vi if an incoming byte has 8 bits then there should be no change in the contents of buffer 105 to cause oscillator 109 to be adjusted however if an input byte has 9 bits this is detected at 107 and the controller 108 would interpret this as a justification bit in the absence of a signal on line 117 so that oscillator 109 is adjusted at the appropriate rate for bit justification as determined by the operating rules for the transmission system referring to fig4 byte justification information is combined with raw sdh clock signal in a summing device 11 and the result is used as the write clock for a byte elastic store 12 thus justification bytes are blocked from entering the store the byte justification information is also made available to a byte filter coefficient block 13 and a signal therefrom is combined with elastic store 12 fill status information in summing device 14 the elastic store fill status information is a measure of the difference in the rates at which data is read into and out of the store 12 summing device 11 byte elastic store 12 first filter coefficient generator 13 and summing device 14 form.