formed of regions doped with an opposite n type impurity typically arsenic with a concentration of between about 5e18 to 5e21 atoms cm 3 the fabrication of the bit lines will not be described since it is well known in the art a thick oxide layer 14 is deposited on the surface of substrate 10 and patterned by conventional photolithographic and etching techniques to provide openings 16 between the source and drain regions that define a first layer of gate electrode area a thin gate oxide layer 18 is formed on the surface of substrate 10 in openings 16 as shown in fig2 the layer 18 preferably has a thickness of between about 100 to 300 angstroms and is formed by thermal oxidation or chemical vapor deposition silicon oxide a photoresist layer 20 is deposited on the substrate and patterned to selectively cover openings 16 the uncovered openings define the desired code implantation of the first layer of gate electrodes the resist pattern does not require a precise alignment since the openings in layer 14 act as the implant mask a suitable impurity is then introduced into the substrate 10 through the unmasked opening 16 resulting in regions 22 as shown in fig2 the impurity introduced by ion implantation techniques can be any suitable impurity of a type opposite to the background impurity in substrate 10 the impurity is preferably boron and is introduced by ion implantation using power of between about 10 to 100 kev and between about 1e12 to 1e14 atoms cm 2 the silicon oxide layer 18 can then be formed by thermal oxidation or chemical vapor deposition methods as shown in fig3 after the photoresist layer 20 is removed.