the end of the cache lines alternatively in an embodiment the unused areas of memory can be skipped in place as shown in fig4 in an embodiment mch 6 includes fsb interface 18 cache line buffer 20 compression decompression 22 error correction code ecc operation 26 inverse ecc operation 28 and mi 24 mch 6 is coupled to cpu 2 and to data 30 in another embodiment at least one of compression decompression 22 ecc operation 26 inverse ecc operation 28 and cache line buffers 20 are coupled to mch 6 not included within mch 6 in an embodiment tagging of the data elements is provided by modifying the ecc bits causing an ecc error the ecc bits are modified by inverting the ecc bits tagging is provided in a way to retain ecc protection afforded by the original number of bits alternatively in an embodiment the ecc bits are modified by adding an offset to the ecc bits in another embodiment tagging is provided by modifying data elements causing an ecc error in an embodiment other methods to tag data elements include adding additional bits per data element adding a separate tag memory to hold all tag bits etc in an embodiment when data is read tags are detected by ecc operation 26 and inverse ecc operation 28 data elements tagged are detagged and the data elements coinciding with the tags.