side power source v dd20 which supplies a power source voltage v dd20 of 0 v for example and an output voltage v 20 is obtained from the drain of the fet 22 on the other hand the driver part 30 includes one non self aligned type fet 31 and resistors r 31 r 32 and r 33 the source of the fet 31 is connected to the drain of the fet 22 and the drain of the fet 31 is coupled to a high potential side power source v dd30 via the resistor r 31 the gate of the fet 31 is connected to a node p 30 which connects the resistors r 32 and r 33 in addition the resistor r 32 is connected to a high potential side power source v dd31 and the resistor r 33 is connected to a low potential side power source v ss30 a driving voltage v 30 for driving a load not shown is output from the drain of the fet 31 fig4 a shows the cross section of the non self aligned type fet 31 of the driver part 30 on the other hand fig4 b shows the cross section of the self aligned type fet of the logic part 20 for example it is assumed for the sake of convenience that this self aligned type fet is the fet 22 the fets 31 and 22 are formed on a common compound semiconductor substrate 40 which is made of gaas for example in other words the fets of the logic part 20 and the driver part 30 are formed on the same chip in.