full to more particularly describe the present invention in more detail refer now to the following description in conjunction with the accompanying figures fig4 is a block diagram illustrating a system 300 in accordance with the present invention as applied to a graphics system the graphics engine 302 accepts a command stream through an interface 303 from the cpu 12 u2033 the graphics engine 302 in turn can utilize the graphics memory 26 u2033 as well as a storage element such as a fifo buffer 306 as the buffer for cpu purposes accordingly the effective size of the entire buffer can be virtually the size of the graphics memory 26 u2033 therefore the cpu 12 u2033 will need to check whether the fifo buffer 306 is full much less frequently than in the above conventional systems since the effective size of the fifo buffer is much larger the graphics engine 302 manages the fifo buffer 306 by checking for the end of the buffer and the buffer wrap around based upon the read and write pointers this management can be further enhanced by using double and triple buffering techniques to ensure performance is optimal accordingly from the cpu 39 s point of view the interface 303 is the storage element in fact it is a storage element with a size equal to the size of graphics memory 26 u2033 in a preferred embodiment the storage element is a fifo buffer 306 as shown in fig4 that when full is redirected to graphics memory 26 u2033 data is read from the fifo buffer 306 until empty then from memory locations in the graphics memory 26 u2033 until graphics memory 26.