value od 3 is latched into a first output latch the second output value od 2 is selected and output by first output multiplexer 32 memory device 22 completes the process of converting id 4 to od 4 at the end of access time 106 memory device 22 begins the process of transforming a fifth input data value ids not shown requiring access time 104 not shown in sequence processing in this manner continues cyclicly while a time sequence of input values is being presented to the high speed signal conversion device 10 the invention as described above can be expanded to further include a second multiplexer 34 third read multiplexer 38 read latch 40 and address module 36 wherein memory device 22 comprises a ram this embodiment allows for the writing of stored data values to memory device 22 asynchronously and for the reading out of stored data values from memory device 22 into video controller 14 upon an appropriate signal indication preferably second multiplexer 34 comprises 8 bits third multiplexer 38 comprises 18 bits and read latch 40 comprises 18 bits these elements enable data to be stored or written into the memory device 22 and further provide an alternate mechanism that enables selected memory locations to be interrogated or read from while the device 10 is responding to and.