node n 3 assumes an off state and the analogue switch 18 between the node n 3 and the node n 1 assumes an on state at the timing of point of time t 7 the potential of the node of the node n 1 is changed to the low level in the same manner as the potential of the node n 3 at this point of time the potential of the node n 2 is changed from the low level to the high level when the pulse u03c6slc 1 is changed from the high level to the low level and the pulse u03c6slc 2 is changed from the low level to the high level at a point of time t 8 the analogue switch 17 between the node n 2 and the node n 3 assumes an on state and the analogue switch 18 between the node n 3 and the node n 1 assumes an off state the node n 3 assumes the high level in the same manner as the node n 2 via the inverter 16 since the clock pulse u03c6com is changed from the low level to the high level before the point of time t 8 as mentioned previously the potential of the node n 3 assumes the potential having the same polarity as the potential of.