is eliminated in the case of the present invention so that it becomes possible to obtain improvement of the operation performance and to reduce the processing time as required in the following explanation a multiplication and accumulative addition circuit in accordance with a third embodiment will be explained in details with reference to figures in this case redundant description which is common to those of the first and second embodiments will be dispensed with in this embodiment of the present invention the intermediate results in the previous cycle are utilized for the multiplication and accumulative addition namely the equation corresponding to the operation to be performed in the third embodiment of the present invention is as follows initial data result of multiplication multiplicand a 0 u00d7 multiplier b 0 multiplicand a 1 u00d7 multiplier b 0 multiplicand a 1 u00d7 multiplier b 0 the first term may be either a predetermined initial data or the output result of multiplication as obtained by the multiplication circuit fig9 is an exemplary circuit diagram showing the multiplication and accumulative addition circuit in accordance with the third embodiment of the present invention the multiplication and accumulative addition circuit comprises a multiplication circuit 14 a selector circuit multiplexer 1 an output register 2 selectors 9 and 10 a 4 2 compactor intermediate result latching registers 4 and 5.