frequency fs and that the samples taken by the subadcs are spaced apart by a time equal to 1 n fs then if the digital outputs of the n subadcs are interleaved together properly by multiplexer 135 the input signal is also properly sampled and the output samples are properly converted to digital values at a combined sample rate of fs n fs in this way a higher equivalent sampling rate can be obtained by an n channel adc apparatus 100 in a preferred embodiment the subadcs may each be successive approximation charge domain pipelined adc cores such as those described in u s patent application ser no 12 074 706 by anthony et al and u s pat no 7 079 067 also by anthony et al each of which are also incorporated herein by reference in their entirety briefly in that type of adc core first and second pipeline stages incorporate charge redistribution charge comparison and charge redistribution driver circuits to provide multiple bits of analog to digital conversion however other types of subadcs 110 may be used fig2 a and 2b are time domain and frequency domain plots of the signals sampled by the two subadcs in the tiadc of fig1 as shown in fig2 a time samples are taken.