transfer source address a data size and a last packet data determination flag for each of the packets to the register 241 in the first arbiter 217 the sub cpu 211 activates the first arbiter 217 by activating a transfer start trigger not shown in the first arbiter 217 step s 308 subsequently the main cpu 121 sends a transfer request to the rxdmac 216 the rxdmac 216 calls the first arbiter 217 and transfers the packets a process performed by the main cpu 121 is described in detail below the main cpu 121 determines whether the interrupt request generated by the sub cpu 211 at step s 306 is detected step s 351 upon determining that the interrupt request is not detected no at step s 351 the main cpu 121 waits for the detection upon determining that the interrupt request is detected yes at step s 351 the main cpu 121 performs interrupt processing based on the request content indicated by the message interrupt request step s 352 in the interrupt processing the main cpu 121 reads data control information the packet information stored in the third ram 214 in the sub controller 210 in other words because the control information the packet information of each of the received packets is stored in the third ram 214 at step s 304 the main cpu 121 reads that information the main cpu 121 makes a setting necessary for performing transfer control to a register not shown in the rxdmac 216 based on the read control information.