to a standard cell a tool driven request is then made to move the standard cell into fpga resulting in the input to the new fpga cell to be temporarily defined as fswire 308 a if the logic designer accepts the change then the fswire 308 a is redefined as fswire 312 d which it will remain as an fpga wire unless another request comes in requesting the change it back into a standard cell wire fig5 b describes a similar process as shown in fig5 a except that the process is used to redefine an fpga wire into a standard wire thus an fpga fswire 312 upon a tool driven request to move the logic to which fswire 312 is an input from fpga to a standard cell redefines the fswire 312 to the intermediate definition sfwire 306 if the logic designer accepts the change then the sfwire 306 is redefined as final standard cell wire sfwire 310 whose definition will remain unless a new request comes in the change back to fpga logic referring now to fig6 there is illustrated a flow chart of a process of utilizing the re designation of wires to achieve an optimal logic chip starting at block 602 the initial coding with signal declarations is performed in the rtl file that is an original u201c layout u201d of the chip using fpga and standard logic cells is defined.