frame the coincidence circuit 42 produces a coincident signal when the target frame length is longer than the reference frame length that is to say the sounding rate is lower than the reference value slow the coincidence circuit 41 produces a coincident signal at this time the output of the coincidence circuit 42 is logical 34 0 34 and the output of the inverter 45 is logical 34 1 34 which is applied to the and circuit 44 accordingly the output of the coincidence circuit 41 is output as the frame clock u03c6 af through the and circuit 44 then the frame counter 43 counts the clock clk up to the target frame length at this time the coincidence circuit 42 produces a frame clock u03c6 bf when the target frame length is equal normal to or shorter fast than the reference frame length the coincidence circuit 42 produces a coincidence signal as the frame clock u03c6 bf when the coincidence circuit 42 produces a coincidence signal the output of the inverter 45 is logical 34 0 34 and the and circuit 44 is prohibited from producing an output signal then when the frame counter 43 is incremented by one the output u03c6 bf of the coincidence circuit 42 is logical 34 0 34 and the output u03c6 bf is logical 34 1 34 thereby to reset the frame counter 43 in the interpolator 10 the interpolated data are sequentially loaded into the ram 52 when the frame clock u03c6 bf is produced from the coincidence circuit 42 the target value in the frame is already stored into the.