input of an inverter 304 whose output is coupled to an input of latch 307 the output of latch 307 is the output of the register file of this embodiment of the present invention and is also fed back to an input of the tri state inverter 305 whose output is coupled to the global bit line 303 the hold mux select signal 306 which can be similarly generated as above as with hold mux select signal 206 is coupled to inverter 305 in this case the hold mux select signal 306 may be an active low signal logically the register file of fig3 performs the same operation as that of fig2 but does not have the delay associated with the multiplexor 205 the tri state inverters 202 for each local bit line group will have a separate local select signal which are generated from read addresses this is to ensure that when a local bit line group e g in this example a group of four is not selected then the tri state inverter selected puts its output into a high impedance state therefore the only local bit line group which is selected forwards the local bit line value onto the global bit line 303 in case of a stall operation or any other bit line multiplexing the hold mux select signal 306 will be used as the tri state inverter select and also as part of the decoding which.