internal clock after being captured by the feedback clock in accordance with the present invention for this data must be stored once during two clocks double registers can be alternately used a signal for selecting a register must be generated according to the feedback clock so that no asynchronous problem is incurred this is shown in fig6 as shown in fig6 data_f 0 and data_f 1 are stored once during two clocks in response to the feedback clock selection signal u201c select_f u201d respectively data_f outputted from the data selection element is inputted into the third d flip flop 109 in response to the internal clock selection signal u201c select_i u201d consequently data is outputted in response to the internal clock selection signal u201c select_i u201d fig7 a to 7 d are timing diagrams illustrating the motion of data according to a phase difference between an internal clock and a feedback clock fig7 a shows the case where a phase difference between the internal clock and the feedback clock is smaller than half a clock fig7 b shows the case where a phase difference between the internal clock and the feedback clock is accurately half a clock cycle fig7 c and 7d show a data interface when a delay value is relatively large in particular fig7 d shows the case where a phase difference between the internal clock and the feedback clock is one clock it can be seen that data stored according to a feedback operation in relation to various types of delay shown in fig7 a to 7 d does not cause violation due to.