well known in the art an insulative layer 38 is next deposited over the insulative layer 34 preferably by pecvd and a pattern of trenches 40 is etched in the insulative layer 38 by plasma etching the trench pattern is an image of the metal pattern shown in fig3 the insulative layer 38 is between about 0 3 and 1 0 microns thick the via 36 is exposed by the etching referring now to fig4 b a conductive layer 42 is deposited over the wafer 30 the conductive layer 42 used in the embodiment is an aluminum alloy and is between about 4 000 and 20 000 angstroms thick alternately other metals for example tungsten or copper may be used alternatively the configuration shown by the cross section of fig4 b may be formed by a dual damascene process which is now described referring to fig5 a a silicon wafer substrate 30 is provided integrated circuit devices not shown are formed in the silicon wafer substrate using conventional state of the art process technology a plurality of interconnection levels are formed over the wafer 30 separated by insulative layers and interconnected through contacts and vias using integrated circuit processes well known by those skilled in the art these layers and interconnection levels not shown in the figures are inferred to be included in the substrate 30 the upper surface of substrate 30 is insulative and a metal interconnective stripe 32 is formed over the insulative surface the metal interconnective stripe 32 is a portion of the uppermost.