is formed in a stripe form over the thin film transistor b and parallel to the gate electrode 124 of the thin film transistor b referring to fig5 b after depositing an insulating material on the entire surface of the planarization insulating layer 127 the pixel electrodes 128 the counter common electrode 129 the insulating material layer is selectively removed so as to form the insulating layer 130 on an area excluding the pixel area more specifically on the boundary area between the pixel areas at this point the insulating layer 130 is also not formed on a portion of the surface of the counter common electrode 129 in other words the insulating layer 130 formed between the pixel electrode 128 and the counter common electrode 129 overlaps only a portion of each of the pixel electrode 128 and the counter common electrode 129 in order to expose a portion of the surface of the counter common electrode 129 the insulating layer 130 includes a trench formed on the counter common electrode 129 in the same direction as the length the counter common electrode 129 subsequently an emission layer is formed on the pixel electrode 128 herein the emission layer is formed of the hole injection layer 132 the hole transport layer 133 the organic electroluminous layer 134 the electron transport layer 135 and the electron injection layer 136 serially deposited thereon referring to fig5 c the shadow mask 131 is used to serially deposit the hole injection layer 132 the hole transport layer 133 the organic electroluminous layer 134 the.