each channel is alternately capable of supporting 8 fast ethernet macs 8 fddi ports 6 oc 3 atm ports or one oc 12 atm port in theory each channel is capable of supporting 10 fast ethernet fe macs but as a practical matter only 8 fe macs are utilized in an embodiment of the present invention due to timing constraints the paths are further sliced into multiple subpaths over which data is routed by path controller 120 into the central shared memory referred to in the figure as packet memory 130 according to commands received from packet queue manager pqm 160 as will be seen embodiments of the present invention may slice the paths in to 1 2 4 8 or 16 subpaths to create switch configurations with 2 to 32 gb s internal bandwidth to the packet memory 130 and 1 to 16 full duplex paths operating at a data transmission speed of 2 gb s as discussed further in detail below a forwarding database 140 contains tables related to packet or flow identification forwarding and filtering and stores in the tables addresses and other well known fields obtained from packets transferred by path controller 120 a packet forwarding controller 150 maintains the tables in forwarding database 140 and decides which packets or flows are identified filtered or forwarded utilizing a comparison engine sliced according to and associated with each of the number of subpath controllers with reference to fig2 a a block diagram of an embodiment of the data path architecture utilized by.