above described arrangement and a detailed description thereof will be omitted in this embodiment as shown in fig2 a reset pulse u03c6chr is set at 34 h 34 to start the reset operations of reset mos transistors 5 and 6 as a first switch means at the same time a switch pulse u03c6sw is set at 34 h 34 to turn on the switch mos transistor 100 after the reset mos transistors 5 and 6 complete their reset operations the switch mos transistor 100 is turned off as shown in fig2 when the reset mos transistors 5 and 6 are turned off a potential difference is generated between the common output line capacitors chs and chn however since the switch mos transistor 100 is on the potential difference between the common output line capacitors chs and chn is canceled therefore the potential difference between the common output line capacitors chs and chn after the switch mos transistor 100 is turned off period b shown in fig2 can be reduced as compared to an arrangement without the switch mos transistor 100 a time u03c41 after the reset mos transistors 5 and 6 are turned off until the switch mos transistor 100 is turned off is preferably r on on resistance of the switch mos transistor 100 however even when the time u03c41 is shorter the potential difference between the common output line capacitors chs and chn can be reduced as compared to the arrangement without the switch mos transistor 100 this embodiment was compared with the arrangement without the switch mos transistor 100 in the arrangement without the switch mos transistor 100 an odd bit synchronized with an input pulse u03c61 and an even bit synchronized with an input pulse u03c62 both to a shift register sr 39 had.