490 watch for a quiet time on the row access control signal 410 and column access control signal 420 occurring after the nap exit delay t nxb or pdn exit delay t pxb has expired the quiet times 495 497 fig4 a and 412 422 fig4 b are scheduled by the memory controller dynamic random access memory dram is often used in highly pipelined systems pipelined systems generally send interrelated and interwoven commands to memory in order to produce a quiet time previous implementations of the memory controller would first approximate the amount of time required for a pipelined command to appear on the row access command signals 410 and column access command signals 420 using this approximation the memory controller would then schedule a quiet time to appear at exactly t nxb or t pxb after pdev signal 490 appears on dqa and dqb signals 430 in order to insure that the quiet time appeared with the proper timing the scheduled quiet time would need to be buffered thus making it longer than necessary for this reason one embodiment of the present invention utilizes circuitry that allows the insertion of quiet times 495 497 fig4 a or 412 422 fig4 b on row access control pins and column access control pins after the end of t nxb or t pxb without a buffer period under the control of the memory controller the current command in the pipeline for the row access control signals 410 and column access control signals 420 is permitted to complete the memory controller then.