is executed to interrupt the cpu to handle the error otherwise step 155 is executed to perform a direct memory access operation to transfer the data from system memory to memory device 35 next step 157 provides for placing the pointer into the transmit queue the process is an endless loop and is executed until the system is powered down fig6 is a high level logical flow chart of a process relating to transmission of tinygrams and jumbograms the discussion is not intended as a full discussion of the operation of a transmission controller the process is entered as step 161 where a pointer location is read from the transmit queue if the pointer value is zero as determined at step 163 the controller loops back to step 161 to read another location in the queue it a pointer was present step 165 is executed to determine the buffer size type this allows the process to determine the correct queue to which to return the pointer at step 167 the pointer is returned to the appropriate pool list 41 or 42 and deleted from the transmit queue step 167 may wait upon return of a receipt acknowledgement transmit control block 43 and control block 33 are preferably implemented as logic gates for optimal speed compared to a software implemented fifo input buffer this implementation reduces memory bandwidth demands.