in an improved leakage current behaviour of the display with the patterning of fig3 d the gate material extends right across the columns without any interruptions that can lead to undesired leakage currents through schottky diodes this can be minimized by patterning the gate material as shown in fig4 a in fig4 b an enlarged region of overlap between the gate and drain source material of the tft 2 is shown resulting in the formation of a distinct storage capacitor c lastly fig4 c shows more clearly the patterning of the semiconductor islands shown in fig3 c while fig4 d shows a variant patterning of the semiconductor islands in which the formation of parasitic tfts is avoided as is particularly evident from the cross section views of fig4 c and 4 d the parasitic transistors present in fig4 c between the source contact of tft 1 the gate and the d s contacts of tft 2 are absent in fig4 d if the oled material is to be deposited over the whole area of the pixel the method according to fig5 a and 5 b can be adopted as fig5 a shows prior to the application of the oled material a passivating layer wavy lines is applied and photolithographically patterned the oled material straight lines and the top electrode material boldly barred can then be deposited over the whole area as shown in fig5 b an alternative patterning of the passivating layer to fig5 a.