effectively isolating the voltage charge on node 52 this voltage charge is stored in capacitors 28 and 26 and thereafter used as the bias voltage v b v b remains substantially the same value indefinitely due to greatly reduced leakage current of semiconductor devices at cryogenic temperatures although it is possible to design a single stage semiconductor amplifier to convert jj signals typically 5 millivolts to the 1 2 volt signals required for cmos semiconductor logic a limitation exists in semiconductor amplifier design this limitation restricts the available bandwidth of high gain amplifiers and is referred to in the art of amplifiers as the gain bandwidth product a high gain amplifier will have a narrow bandwidth thus restricting the maximum operating frequency of the logic system it is well known in the art that multistage amplifiers can improve upon the gain bandwidth product restrictions of a single stage amplifier provided the increased delay of the signal through the added amplifier stage s is tolerable in addition a high enough gain single stage amplifier would have to be designed using long channel transistors which adds capacitance to the circuit and therefore adds delay to the signals for the above reasons a second stage of semiconductor amplification is added to the circuit of the present invention referring now to fig2 the preferred embodiment of the present invention is illustrated as a schematic circuit diagram pmos fet 36 and nmos fet 38 comprise an inverting cmos amplifier having an output connected to output node 60 and an input connected to node 54 the approximately 100 millivolt signal at node 54 is amplified to a signal voltage having high and low voltage.