plurality of arrays enabling a plurality of arithmetic logic units to perform a first number of operations on first elements of the plurality of arrays performing the first number of operations on first elements of the plurality of arrays using the plurality of alus decrementing the counter by the first number of operations to provide a remaining number of operations and enabling a number of the plurality of alus to perform the remaining number of operations on second elements of the plurality of arrays application_number US 59236509 A description the present invention is directed to circuits and methods for performing simd operations in simd architectures having a plurality of alus the following description contains specific information pertaining to the implementation of the present invention one skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application moreover some of the specific details of the invention are not discussed in order not to obscure the invention the drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention to maintain brevity other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings referring to fig1 an exemplary circuit for performing simd operations is shown in fig1 simd operation circuit 100 includes among other elements not shown operation control circuitry 102 counter 104 memory 106 alus 108 110 112.