unit 122 implements and executes fixed point integer instructions additionally the integer execution unit 122 assists in execution of floating point instruction which depend on integer condition codes integer registers and floating point condition codes the memory management unit 130 performs virtual address to physical address translation and includes a translation lookaside buffer that provides for a translation for the most frequently accessed virtual pages the data cache unit 132 provides the main interface between execution pipelines and memory within the processor 100 the data cache unit 132 executes load and store instructions as well as derivatives of load and store instructions the data cache unit 132 provides a first level cache that is coupled directly to the execution units the memory disambiguation buffer dynamically disambiguates memory addresses to enable execution of out of order instructions the secondary cache unit 140 provides a unified l 2 cache the l 2 cache is controlled by the memory scheduling window which tracks accesses that miss in the l 1 caches the mmu and snoop system request the memory scheduling window provides an interface between the instruction fetch unit and the l 2 cache the memory scheduling window also receives snoops from the external interface unit 142 and retired stores from the data cache unit 132 the external interface unit 142 controls data flow among the l 2 cache and the external cache controls system interconnect provides external cache control and provides a common interface for external processors i o bridges graphics devices and memory controllers the test processing unit 150 performs power on tests as well as diagnostic access within the processor 100 the test processing unit.