t 2 g a first conductive terminal t 21 and a second conductive terminal t 22 the third transistor t 3 can include a control terminal t 3 g a first conductive terminal t 31 and a second conductive terminal t 32 the control terminal t 2 g of the second transistor t 2 receives the control signal ckvb the first conductive terminal t 21 of the second transistor t 2 receives a diminution signal vee the second conductive terminal t 22 is electrically coupled to the first conductive terminal t 31 of the third transistor t 3 the second conductive terminal t 32 of the third transistor t 3 receives pulse signal ckv the control terminal t 3 g of the third transistor t 3 receives a second control signal vdd a node between the second conductive terminal t 22 of the second transistor t 2 and the first conductive terminal t 31 of the third transistor t 3 outputs the pulse signal ockv in the illustrated embodiment the pulse signal ckv may be full or half square wave and have a first high level logic and a first low level logic the voltage of the first high level is 18v and the voltage of the first low.