not require high speed processing hence the read and write requests initiated by host mcu 105 over control bus 130 must be captured and acknowledged by dtad processor 200 asynchronously fig2 shows a block diagram of dtad processor 200 in greater detail core central processing unit cpu 201 can be any type of digital processor capable of handling the desired functionality in a particular embodiment core cpu 201 is a digital signal processor such as the t320c2xlp processor manufactured by texas instruments inc dtad processor 200 includes internal memory that is preferably non volatile memory such as a prom eprom or eeprom type memory for storing program code and static data i o interface circuit 203 is responsible for interaction with external i o 110 shown in fig1 although i o interface circuit 203 could take advantage of the asynchronous latch in accordance with the present invention the preferred embodiment uses conventional i o circuitry in i o interface 203 serial interface 204 interacts with serial and analog signals from external i o 110 external memory interface 206 handles data read and write transactions with external memory 125 shown in fig1 analog to digital converter adc 209 handles interaction with analog interface 120 and may handle other functions such as monitoring telephone line voltage battery levels and other non speech analog signals clock and power control circuit 208 includes logic to slow down and speed up the internal clock of core cpu 201 to conserve power the host mcu interface 300 embodies the asynchronous i o circuit in accordance with the present invention mcu interface 300 is coupled to control bus 130 shown in fig1 and captures asynchronous read and write signals from host cpu 105 in response to a read or write request mcu interface 300 cycles through a.