the buffer capacity and writing to the dreq register where the capacity is greater than the transfer threshold is shown in fig6 by step 333 this operation enables further cycles of generating dreq and dack signals the advantages of these embodiments of the application are that there is a minimisation of the number of connections required only one signal in each direction furthermore in some embodiments the operation is tolerant of any amount of latency in the request or acknowledgement signals in these embodiments the sender can place as many transfers worth of data into the buffer without the receiver being required to remove any of the data provided that the buffer is large enough furthermore in some embodiments multiple requests do not cancel each other out the senders cpu according to some embodiments can be further be allowed to be recalculate and reassert the request safely at any time without causing the receiver to receive a spurious request for example where the sender attempts to reassert the request whilst an acknowledgement is waiting the request is ignored because the waiting acknowledgement overrides the request it would be understood that while the read and write pointer management can be performed by software running on the cpus the embodiments of the application can be extended to include automatic pointer management hardware furthermore although the above description describes where the control of a shared memory is performed the operations and designs in communicating predetermined commands from one cpu to another can also be implemented using embodiments of the application in general the various embodiments may be implemented in hardware or special.