is required for the two 39 s complementation of d steps 2 4 6 8 10 and 12 compute the term needed for the multiplications and steps 3 5 7 9 11 and 13 compute the quotient it must be observed that this is the fastest possible execution and it is assumed there is bypassing of the load cycles i e the l cycles of the pipelines are not shown on the diagrams also it must be observed that steps 4 6 8 10 and 12 can not be initiated earlier because these steps need the result of the multiplier that produces the previous d in two 39 s complement form the previous observation implies that steps 5 7 9 11 and 13 also cannot be initiated earlier finally it can be observed that the total number of cycles required for implementation of the prior art divider of fig1 is twenty referring now to fig3 the divider of the present invention can produce a quotient in fourteen cycles in fig3 the load cycle l of the multiplier does not appear because it has been assumed that the result is bypassed as it has been assumed in the previous discussion of the prior art divider it is also noted that because there is no need for two 39 s complementation step 1 can immediately begin with the execution however if it is not assumed that the normalized result is loaded i e the normalizer is not on the same chip then one extra cycle needs to be added for both implementations i e the present invention and the prior art implementation producing the quotient in fifteen and twenty one cycles respectively.