terminal of the flip flop 272 is the output terminal 172 of the high limit module 108 table 2 summarizes the states internally generated by components of the high limit module 108 when the value of the high limit vref 1 132 on the first terminal is greater than the value of the feedback voltage 124 on the second terminal the comparator 268 generates a signal in a logic low state the logic low state from the output of the comparator 268 indicates that the feedback voltage 124 is in range i e not above the value of the high limit 132 when the voltage at the first terminal is less than the voltage at the second terminal the comparator 268 generates a signal in a logic high state the logic high state from the output of the comparator 268 indicates that the feedback voltage 124 is out of range i e above the value of the high limit 132 the flip flop 272 latches the state of the output signal of the comparator 268 at the falling edge of the clock pulse received from the timing input terminal 184 which is inverted at the clock terminal of the flip flop 272 upon the falling edge of the clock pulse the output state of the comparator 268 becomes the latched state at terminal q of the flip flop 272 the change of state of the output at terminal q of the flip flop 272 is synchronized to the falling edge of the received clock pulse from the timing input terminal 184 the received clock pulse is the.