is made under and on the left side of the dielectric layer 41 a drain d is made under and on the right side of the dielectric layer 41 there is semiconductor material 43 between the source s and the drain d the adjacent transistors t 41 t 42 are made side by side and with gates doped with different dopant furthermore the adjacent transistors have different threshold voltage vt from each other a length of 4 l for the adjacent transistor in x direction is only four fifth u2158 of that for the traditional transistors in parallel connection as shown in fig2 u2158 is calculated from comparison of the corresponding lengths 4 l v 5 l and then 4 l 5 l u2158 when the number of transistor is extremely large to be made on a single chip the occupied area of a single chip on the semiconductor wafer saves half the occupied area for a single chip according to this embodiment and compared with a traditional one as shown in fig2 is as follows the length in x direction for traditional transistors in series connection is 2n 1 l however the length in x direction for continuous multigate transistors in series connection is n 2 l 2n 1 l is simplified to be 2 nl when n is extremely a large number n 2 l is simplified to be nl when n is extremely a large number the threshold voltages setting are the same as that described for fig3 as an example a typical operation parameters can be described as follows t 41 is at high state when the gate g 41 is applied with a voltage of v dd and t 41 is at low state.