asrten configuration bit when the asrten configuration bit is asserted or high then the multiplexer 92 routes the intas 14 0 signals to the input terminals of the flip flop 90 and when the asrten configuration bit is deasserted or low the multiplexer 92 routes the intin 46 32 signals to the input terminals of the flip flop 90 as shown in fig1 the int_mid 47 16 bits are furnished by a multibit d type flip flop 88 which receives the intin 31 0 signals at the input terminals of the flip flop 88 and is clocked by the pclk signal referring to fig1 the int_mid 15 0 bits are furnished by a multibit d type flip flop 92 which is clocked by the pclk signal the input terminals of the flip flop 92 are coupled to the output terminals of a multibit multiplexer 94 the selection by the multiplexer 94 is governed by the logical state of the sslten configuration bit in this manner the logical state of the sslten bit determines whether the multiplexer 94 routes the serirq 15 0 signals for the sslten bit being asserted or high or the intio 15 0 signals for the sslten bit being deasserted.