fed to respective nand gates 63a 63b and 63c respectively the outputs of the comparators 61b and 61c logic 1 high are also applied to inverters 62a and 62b respectively the inverters invert the logic 1 high to logic 0 low and feed the inverted signal to nand gates 63a and 63b respectively since nand gate 63a is fed a logic 1 from comparator 61a and a logic 0 from inverter 62a the output of nand gate 63a is logic 1 or 34 off 34 nand gate 63b is also at logic 1 because of the logic 1 input from comparator 61b and the logic 0 input from inverter 62b however the nand gate 63c is fed a logic 1 input from comparator 61 c and a logic 1 input from inverter 62c and nand gate 63c goes to logic 0 or 34 on 34 for the accessory controlled by output 43c the diode 64c is for isolation purposes the logic 1 output from the inverter 62c is from the logic 0 input received from the output of the comparator 61d it will be appreciated that each of the nand gates 63a through 63g are fed inverted logic signals from inverters which receive logic signals from associated comparators nand gate 63h receives a constant logic 1 signal and goes from normal logic 0 to logic 1 when comparator 61h goes from logic 0 to logic 1 the outpts 43a b c and d and 45a b c.