on the adjusted program window this is accomplished by generating a conversion table from the expected reference cell bit pattern and the actual bit pattern read from the reference cells the conversion table can also be generated from reading the conversion information stored in memory in an alternate embodiment the difference between the initial reference fixed bit pattern and the recently adjusted reference cell bit patterns is then determined the conversion table is applied to the read data bit patterns from the memory cells to get the actual data the embodiment illustrated in fig5 can be performed by the memory controller of the memory device in one embodiment it is performed prior to every program operation alternate embodiments perform the method after a certain number of erase program cycles have been performed fig6 illustrates a functional block diagram of a memory device 600 that can incorporate the memory cells of the present invention the memory device 600 is coupled to a processor 610 the processor 610 may be memory controller a microprocessor or some other type of controlling circuitry the memory device 600 and the processor 610 form part of a memory system 620 the memory device 600 has been simplified to focus on features of the memory that are helpful in understanding the present invention the memory device includes an array of non volatile memory cells 630 that can be flash memory cells or other types.