signal line of vhdb symbol g denotes a grounded terminal and symbol n10 denotes a signal line for the grounded terminal g transistors m4 m5 and m7 are n channel enhancement mosfet 39 s and a transistor m6 is a p channel enhancement mosfet symbols iv1 to iv3 denote logical inverters though not shown in fig2 the first power supply voltage vdd and the ground voltage are supplied to a power supply line and a grounded line of each of the logical inverters iv1 to iv3 explanation will now be made of the connection of the high voltage inverting circuit dtv in the present embodiment the drain and the gate of the transistor m4 are connected to the signal line n1 of the second power supply voltage vpp and the source thereof is connected to a signal line n11 the drain and the gate of the transistor m5 are connected to the signal line n11 and the source thereof is connected to a signal line n12 the source and the substrate of the transistor m6 are connected to the signal line n12 the gate thereof is connected to the signal line n2 of the first power supply voltage vdd and the drain thereof is connected to a signal line n13 the drain of the transistor m7 is connected to the signal line n13 the gate thereof is connected to the signal line n2 of the first power supply voltage vdd and the source thereof is connected to the.