the signal paths short and timing skews are minimized or eliminated the phase locked loop circuitry further reduces timing skews which occur when off chip signals are used the process for forming the interposer substrate 100 will next be described with reference to fig3 a 3e first as shown in fig3 a a silicon wafer 200 which will ultimately yield many interposer substrates 100 has holes 210 drilled in it which will serve as through holes the holes 210 are then subjected to an oxide deposition this oxide deposition forms an oxide layer 220 on the inner surface of the holes 210 the oxide layer serves to create an insulating layer between metal later deposited within the hole and the rest of the interposer substrate 100 after the oxide deposition the holes 210 are filled with a metal conducting substance 230 such as aluminum al copper cu gold au or silver ag these holes 210 provide a high density high bandwidth connection between the chips 110 120 fig2 attached to the opposite sides of the interposer substrate 100 after the holes 210 are formed and treated active and passive circuits 240 are formed within the silicon wafer 200 by techniques well known in the art the silicon wafer 200 with active and passive circuits 240 formed therein is shown in fig3 c then one or more levels of metallurgy not shown are formed on the surfaces of the interposer substrate 100 as are required finally the silicon wafer 200 is divided into a multitude of interposer substrates 100 fig2 as shown in fig3 d the dotted lines in fig3 d are exemplary dicing lines after this the interposer substrate 100 is ready to have the ic chips 110 120 mounted on.