n vdd u2212 vth the circuit 100 may implement each of the charge pump circuits 102 a 102 n on electrically separate substrates e g separate wells however more than one stage 102 a 102 n may be implemented on a single substrate the circuit 100 may allow the charge pump circuits 102 a 102 n to utilize the output voltage of a previous charge pump circuit as a bias voltage e g well bias voltage for a succeeding charge pump circuit for example the charge pump circuit 102 a may provide the output voltage u2212 vdd u2212 vth that may be presented to the charge pump circuit 102 b ideally each succeeding stage 102 a 102 n may have an output voltage equal to an output voltage of the previous stage 102 a 102 n plus the bias voltage e g u2212 vdd u2212 vth for example if the bias voltage u2212 vdd u2212 vth is u2212 3 volts an ideal circuit with six charge pump stages 102 a 102 n may generate a u2212 18 volt output referring to fig2 a detailed schematic of the stage 102 a is shown each of the stages 102 b 102 n may have a similar implementation as the stage 102 a the charge pump 102 a may be implemented on an electrically independent substrate e g an independent well from the other stages 102 b 102 n the stage 102 a generally comprises a transistor 120 a transistor 122 a capacitor 124 and a capacitor 126 the stage 102 a generally comprising the input 112 a the input 114 a 1 the input 114 a 2 and the output 116 a the input 112 a may receive the voltage vss the input 114 a 1 may receive the clock signal.