types interfaces that are either now known or later developed fig3 is a schematic of a high speed output data cell that can send data to a memory device and that is improved by incorporating an embodiment of the present invention this schematic includes an output cell 300 including d flip flops dff 305 and 310 and multiplexer mux 315 this figure as with the other included figures is shown for illustrative purposes and does not limit either the possible embodiments of the present invention or the claims single data rate signals dh and dl are respectively received on lines 320 and 325 into flip flops 305 and 310 the clock signal clk on line 330 clocks flip flops 305 and 310 on its rising edge in other embodiments a falling edge could be used flip flop 305 provides data output d 1 on line 335 and flip flop 310 provides data output d 0 on line 340 the multiplexer 315 receives d 1 at input mux 1 d 0 at input mux 0 and the clk signal at the data select input mux s in this embodiment the mux 1 signal is transmitted through the out of the multiplexer on line 345 while the mux s signal is 1 and the mux 0 signal is transmitted while the mux s signal is 0 the data rates of.