the transmission completion interrupt request described with reference to fig1 is supplied to the compressed image decoder 32 upon a lapse of the one frame period the arrangements of the frame memories 34 and 36 used in this embodiment will be described below fig3 is a block diagram showing an arrangement of the frame memory referring to fig3 a tc524256 memory is used as the frame memory as shown in fig3 a memory array 110 comprises a 1m bit dram having 512 column bits 512 row bits and a depth of 4 bits a transfer gate 112 transfers data between the memory array 110 and a serial register 113 in units of columns the serial register 113 stores the data transferred by the transfer gate 112 a serial data selector 114 sequentially inputs outputs data stored in the serial register 113 in accordance with a serial address pointer value a serial i o buffer 115 inputs outputs data output from the selector 114 a serial address pointer 116 automatically updates a start address set by a column address buffer 126 a sense amplifier 118 detects a content of a row set by a row decoder 128 in the memory array 110 an i o gate 120 performs an input output operation of an output from the sense amplifier 118 on the basis of the output from the column decoder 122 an i o buffer 124 inputs outputs random access data 126 denoted.