r e are the correct and obtained results respectively we provide an additional metric for information data acc inf that measures error significance as hamming distance this metric is defined as 1 u2212 b e b w where b e is the number of error bits and b w is the bit width of the data the amplitude and significance metrics were averaged over the entire simulation to evaluate the approximate circuits table i summarizes results u2014 minimum clock period area error rate and throughput improvements u2014 for each implementation of the 16 bit adder with different k values according to the results with smaller k the minimum operating frequency increases but the error rate increases as well with higher k the error rate is reduced significantly but the benefit of the approximate circuit i e clock period reduction is small in the table throughput improvement over conventional design is calculated including error recovery overhead from the implementations a maximum throughput improvement is achieved when k 3 if we correct erroneous results with error correction and detection as in fig3 then 17 2 additional clock cycles are required for error correction with this overhead the present configurable approximate adder with error correction can improve data throughput by 24 6 over a conventional cla adder gate level simulation at each possible clock period was conducted to compare five adders carry look ahead adder cla lu 39 s adder s l lu u201c speeding up processing with approximation circuits u201d computer 37 3 2004 pp 67 73 etai etaiim n zhu w goh w zhang k yeo and z kong u201c design of low power high speed truncation error tolerant adder and its application in digital signal processing u201d ieee trans on vlsi systems 18 8 2010 pp 1225 1229 and the.