not contained within the base cell a large multiplexer per output bit labeled mux n mux 0 in the figure is used to select the appropriate base cell to read data from the large multiplex may be created from smaller standard cell multiplier cells or may be created with an array of standard cell nand and cells as shown in fig5 b in fig5 b rsel read select control signals are generated by decoding the multiplex address selection bits and rdata read data signals are outputs of the base cells as shown in fig5 a with the nand and structure shown in fig5 b the register bit x goes low only if the both rsel and its associated rdata are high this value would most likely be inverted before output of the register file the construction of the register file shown in fig5 a is fully compatible with standard soc cell based static timing techniques the subject matter disclosed herein presents a novel way to include into the base cell the first level of the read port nand structure shown in fig5 b cells labeled as u201c c 0 u201d u201c c 1 u201d and u201c cm u201d such that the second level and i e mx between two adjacent cells from fig5 b i e cells labeled c 0 c 1 cm is also included into the base cell this approach results in few overall transistors and less silicon area required by the register array while retaining a register file organization which is fully compatible with standard soc cell based static timing techniques fig6 b shows one embodiment of the.