ffs and the data signal so as to output the result as shown in fig1 the hogge type phase comparison circuit has characteristics for outputting a pulse as a phase difference signal according to a delay time from a rising edge or a falling edge of the data signal to a rising edge of the clock signal an operation of the circuit of the fourth embodiment is described with reference to fig1 a and 11b fig1 a shows an example in a case where the rising edge of the data signal is steep and fig1 b shows an example in a case where the rising edge of the data signal is gradual level changes at points indicated by numerals 1 2 3 in fig9 are respectively indicated by the same numerals 1 2 3 in fig1 a and 11b the data signal and the clock signal are input as shown in 1 and 2 in fig1 a and 11b the amplifier 501 outputs a signal 3 that is obtained by identifying an edge of the data signal by using the decision threshold level vth and the amplifier 50 2 outputs a signal 4 that is obtained by identifying an edge of the data signal by using the decision threshold level vth dth the hogge type phase comparison circuit 51 1 compares the signal 3 with the clock signal 2 so as to output a signal 5 the hogge type phase comparison circuit 51 2 compares the signal 4 with the clock signal 2.