controlling the word driver 27 with the predecode signal by adopting such a predecode system the unit decoders constituting the main decoder 26 b can be arranged in a high integration state according to the word line pitch of the memory array thereby to reduce the chip size incidentally the multi value flash memory of the aforementioned embodiment is equipped on the common silicon substrate as shown in fig4 and 10 with the function circuits 11 and 14 for transforming two bits data into quaternary data and vice versa however a dedicated controller unit having those functions can be separately provided in this modification the flash memory chip need not be provided with the functions intrinsic to the multi value so that its chip area does not increase another advantage is that a plurality of flash memories mdfm can be connected to a single controller unit cont and controlled by a bus bus as shown in fig1 this controller unit is constructed to have an address generating function and a command generating function in addition to the aforementioned data transforming inverse transforming functions fig1 shows the internal power source generator 28 for generating the word line voltage and a substrate potential vsub and the switching circuit 29 for selectively feeding them to the word driver 27 and the like and fig1 shows an example of the construction of the word driver 27 the internal power source generator 28 generates the necessary word line voltages in response to the internal control signals which.