and removed from in between the bitline oxides 640 u2033 this also etches thins the bitline oxides then the exposed silicon 612 between the bitline oxides 640 u2033 is etched resulting in sti trenches 672 etched into the silicon 612 between the bitline oxides 640 u2033 the sti trenches 672 may be etched using a reactive ion etch rie which exhibits good selectivity to oxide the bitline oxides u201c oxide pillars u201d 640 u2033 provide the masking for the silicon trench etch so that the trenches 672 are self aligned to the bitlines the depth of the sti trenches 672 in the array area may have an exemplary trench depth in the range of 50 nm 500 nm such as 100 nm 300 nm other sti trenches not shown formed in the cmos periphery area may be formed very early in the process during the active area mask typically a fab will have an sti etch module which is dictated by cmos requirements thus they may feel that the sti in the array has to be the same however as disclosed herein sti in the array area may be formed separately and independently from sti in the cmos area the trenches 672 may extend into the silicon 612 at an angle somewhat less than 90 degrees so that the trenches 672 taper from wider at the surface of the silicon to narrower within the silicon and do not undercut the bitlines 646 the trenches 672 taper.