to start data acquisition the output of the logic circuit 102 is connected to bus drivers 86 as may best be seen in fig3 the combination and single triggers require the logic circuits 100 and 102 as previously indicated one of the inputs to this set of logic circuits is the outputs of the trigger rams 66 the enables for allowing or inhibiting the triggers to occur are controlled by function data codes 9 and 10 function data code 9 loads the start enables into a register which is then gated with the start trigger ram outputs similarly function data code 10 loads the stop enables into a register which is gated with the stop trigger ram outputs depending upon which triggers are enabled the proper starting or stopping data acquisition or stop clocks will be activated the start and stop data acquisition logic has as inputs the output from the combination and single trigger logic the stop data portion has another input which is supplied from the snapshot ram address counter 88 as may best be seen in fig3 when it is enabled both start and stop data acquisition provide an output that is supplied to the ram control logic 72 the stop data acquisition has two additional outputs which are supplied to a trigger and go through the bus driver logic 86 these are the stop clock stpclk and global stop request gstprq.