random circumstances a data cache error for a cache associated with the processor 111 may occur such an error can be completely corrected i e the processor 111 does not need to be replaced but will guarantee that the processors 111 and 113 will break lock step at some future time because the data cache error causes timing differences between the processors 111 and 113 the processor 111 may detect the data cache error and use the detection of this data cache error to signal the logic circuit 115 that the processor 111 is experiencing an error that will cause a loss of lock step and that the processor 111 is u201c bad u201d the logic circuit 115 may then u201c turn off u201d thereby ending lock step operations and processing may continue using the u201c good u201d processor 113 at some future time recovery from the loss of lock step and correction of the data cache error is executed to restore lock step operation of the processors 111 and 113 fig3 illustrates further architectural details for recovery from loss of lock step in the computer system 100 of fig2 in fig3 the computer system 100 is shown with additional processors 121.