eight instructions of window 102 additional inputs include long word load operation flags register file decode signals invalid destination register flags destination address signals and addressing mode flags for all eight instructions ddc 208 comprises 28 data dependency blocks 204 each block 204 is described in a key 206 each block 204 receives 3 inputs ixs 1 ixs 2 and ixs d ixs 1 is the address of source input number 1 of instruction x ixs 2 is the address of source input number 2 of instruction x and ixs d is the address of the source destination input of instruction x each block 204 also receives input iys d which is the destination register address for some previous instruction y a top row 208 for example receives i 0 s d which is the destination register address for instruction 0 each block 204 outputs the data dependency results to one of a corresponding bus line 114 for example the address of i 2 s d must be checked with operand addresses s 1 s 2 and s d of instructions 7 6 5 4 and 3 each block 204 performs the three comparisons to illustrate these comparisons consider a generic block 700 shown in fig7 which compares instruction y 39 s source destination operand with each operand of instruction x in this example the three following comparisons must be made these comparisons are represented by three comparator blocks 702 704 and 706 respectively one set of inputs to comparator blocks 702 704 and 706 are the bits of the iys d field which is represented by number 708 comparator block 702 has as its second set of inputs the bits of the ixs 1 similarly comparator block.