signal on line 87 is given every second outputvalid flag the address starts at 0 and increments every second out putvalid flag until 39 instead of advancing to 40 the address is reset to 0 thus providing the double buffering scheme this works so long as the reading does not occur during the outputvalid flag and that the previous segment 39 s data can be written to dram in the time it takes to generate a single segment 39 s data the process is shown in the following pseudocode address generation for reading is trickier since it is tied to the timing for dram access both reading and writing buffer ef access and therefore color 1 generation it is more fully explained below address generation for buffers c d e f and colorn are all tied to the timing of dram access and must not interfere with color 1 processing with regards to buffers e and f the basic principle is that the data for a single segment of color n either odd or even dots is transferred from the dram to buffer ef via buffer cd once the data has been read from dram those dots are replaced based on the values in colorbuffern this is done for each of the colors in odd and even dots after a complete segment 39 s worth of dots has accumulated 20 sets of 64 cycles then the process begins again once the data for all segments in a given printline has been transferred from and to dram the current.