bits stored in comparison register 498 and an increment logic block 482 for computing a new increment value within each processing element based on the current dayclock value and the carry in value stored in register 481 further each processing element may include a multiplexer 487 for providing a mechanism to load an initial value into increment register 488 a sequencer 470 for controlling the operation of each processing element and a pair of registers 481 and 483 for synchronizing the carry and ge signals finally each dayclock module may include an output multiplexer 500 for serially multiplexing the carry and ge signals to the next succeeding dayclock module in the exemplary embodiment sequencer 470 has a mode input 472 a module input 474 and a clock input 476 sequencer 470 provides control signals to increment counter 482 via interface 478 to comparator 504 via interface 480 to increment register 488 via interface 489 to input multiplexer 487 via interface 491 and to output multiplexer 500 via interface 493 the mode input 472 may be used to select between the configurations shown in fig4 and fig5 the module input 474 may designate the position of the particular dayclock module within the 72 bit dayclock the clock input 476 may be used to synchronize the operation of the dayclock modules for illustrative purposes only processing element 141 of fig4 a is shown however it is recognized that the other processing elements may be similarly constructed.