is the voltage used to adjust the output power the impedance can now be calculated where cox is the gate oxide capacitance per unit area w the gate width l gate length rf the resistor connected to the source of the transistor ron the equivalent u201c on u201d state resistance and vgt the voltage at the gate of the transistor which is set by vvswrc with vvswrc variation from 0 to 2 5v the compensation load will vary from a high impedance to rf ron ohms as shown in fig1 the parameters of the transistor are as follows v d v s 0v and v dd gt v gs gt 0 when the power amplifier pa is on the vswr compensation is off if the ac signal v p gt v t then the mos transistor is turned on and non linearities occurs fig8 shows the mos circuit implementation 40 for load compensation at high input powers the dummy load is based on a nmos in u201c cold fet u201d mode acting as a variable resistor voltage gate control vds 0v the mos size w l 200 0 25 is chosen to not degrade the output power performance in u201c off u201d mode and to be able to handle voltage swing without self biasing which may induct more insertion loss of the matching network with reference to fig1 a load compensation circuit 45 with dc shift according to the present invention is described which solves the problems previously described of the linearity degradation at high rf power levels by providing an output which does not degrade with rf power levels the fet compensation load implementation circuit 45 is inserted between the transmitter stage 50 and the transformer circuit 20 the compensation load circuit 45 serves as the.