a unique output register out reg of the system as a function of a certain external timing signal clock also generated by the central control unit cpu assume moreover that such a data transfer must take place in the shortest possible time when the stimulated block lt i gt has the currently required data ready and the clock signal is still at logic zero the latter condition indicates that the system is about to request new data at the output should the request of the output data for example represented by the raising edge of the clock signal anticipate slightly the data_ready signal the system must still be able to output the correct data in such an exemplary situation the data transfer managing system sinc_async_control efficiently fulfils its task by processing the data_ready lt i n gt signals that is the information that the content of the output registers of the respective asynchronous blocks has been updated the external clock signals clock and the signals req lt 1 n gt this is among the different output registers of the respective asynchronous blocks and the appropriate signals load lt 1 n gt are generated for performing the loading of the correct data in the output register out reg the signals req lt 1 n gt enable only one of the data sources to transfer data toward the output register out reg purposely generated by.