program the state of the latch the latch is reset to a high logic state using the precharge transistor 515 where the node nb is charged to a high value with the precharge transistor 515 and the word control gate 517 off the storage transistor 516 a is turned on if the storage transistor is programmed to a low state no trapped charge the node nb will fall to a value equal to vml when the word control gate is turned on for the second time the state of the latch 512 is switched to a low state if the storage transistor is programmed to a high state trapped charge the node nb remains in the high voltage state and when the write control gate is turned on a second time the latch remains in the high state fig9 shows the timing of the pchg signal connected to the precharge transistor 515 the wcg signal connected to the word gate transistor 517 and the mg signal connected to the storage transistor 516 a in fig1 is the schematic diagram of the third and fourth embodiments of the present invention two nmos storage transistors mh and ml are connected in series between a high bias bh and a low bias bl the storage transistors mh and ml are nonvolatile and are formed with a charge storing insulator film 710 under the gate of each storage transistor the charge storing insulator 710 which lays between the oxide formed over the semiconductor substrate and the gate of each storage transistor is an insulator which is capable of storing a charge for example a nitride film or a nano crystal.