state machine 28 controls the input reference selector 20 the loop filter bandwidth and switches the dpll automatically into holdover mode when required the mtie module 21 compensates for the phase offset between the new reference input and the dpll output clock in case of a reference switch or a recover from holdover mode the phase detector 22 converts phase difference between the input reference clock and output feedback clock to a signed binary number representation the loop filter 23 performs output phase slope limiting filters the phase error output of the phase detector to a frequency offset signal for the dco the bandwidth of the dpll is determined in the loop filter 23 the dco 24 is the actual clock generator it generates a clock that is phase locked to the input reference clock the frequency of the generated clock is determined by the system clock the center frequency setting inside the dco and the frequency offset value from the loop filter the frequency converter 25 multiplies the current phase of the dco by a constant fraction and thereby generates a clock of a frequency that is a fraction of the dco output clock frequency the output divider 26 divides the output clocks of the dco and the frequency converter down to the required clocks and an 8 khz frame pulse when the dpll is a primary master it locks to the input clock selected by.