as illustrated the r c time constant of the incorporated resistors and capacitor coupled with the nor gates as illustrated dictates and forms a periodic square wave pulse train 1 in the preferred embodiment the period of the pulse train 1 is 3 3 milliseconds in duration the pulse train 1 is communicated to first and second counters 12 and 14 respectively forming the clock input thereto in the preferred embodiment these counters are suitably formed from common 34 4017 34 counters two counters are used for redundancy in a manner which will be appreciated by understanding the following description the output of the q0 bit least significant of each of counters 12 and 14 forms signal g1 and g2 respectively output of bits q1 of each of timers 12 and 14 form signal d1 and d2 respectively output of timer bits q2 of each of timer 12 and 14 forms signals h1 and h2 respectively the q3 bit output of each of timers 12 and 14 is communicated to its own reset pin to recommence the counting sequence of their shared clock input pulses 1 the pulses d1 d2 g1 g2 and h1 h2 are communicated to the pulse adder b the pulses d1 and d2 are also communicated to the gating network d for use as will be described below the adder b functions to form a hard wired or operation on selected signal combinations more particularly the d1 and d2 signals are combined with the g1 and g2 signals to form the composite signal u2218 the d1 and d2 signals are combined with the h1 and h2 signals to form the composite signal f the o and f.