the output l4 of the memory sp to reset the flip flop ff this signal is also simultaneously applied to the further address unit ad2 to target the further multiplexer mx in such a manner that the first address register rg1 is connected through to the address control unit ad1 by means of the output signal of the flip flop ff the condition multiplexer bm is caused to deliver a load signal ld for the address unit ad1 at its output therefore the content of the first address register rg1 is loaded into the address unit ad1 this however is precisely the address of that command word which was pending for processing upon occurrence of the interrupt after the completion of the interrupt therefore the processing of the commands is continued at that location at which the interrupt occurred if an interrupt is desired internally in the control unit for example because a subprogram is to be executed then the memory sp delivers a signal at its output l3 which is supplied to the second address register rg2 this output signal causes outputing of the address stored in the address unit ad1 and feeding of the same to the second address register rg2 by contrast the address of the first command word of the subprogram is output into the address unit ad1 by way of the lines al1 and the multiplexer mx the load.