m w l for each successive utterance frame n the frame selection of the dynamic time processing operations performed in dtw processor 207 is controlled by frame sequence logic 307 shown in greater detail in fig5 in the embodiment illustrated in fig2 5 dtw processor control 430 provides control pulses sw1 and fsr as well as control signal c responsive to pulse sc from sequence controller 400 word counter 220 in fig2 is reset to its w w 0 state by pulse sw1 the fsr pulse resets counter 505 to its initial state counter 505 stores the number of utterance frames of the level already processed the utterance starting frame inserted into latch 501 is transferred to counter 503 by pulse fsr the n output of counter 503 provides the input speech pattern frame signal for the dtw processing the fsr signal also sets flip flop 370 via or gate 369 the dmtr signal is thereby enabled at the beginning of each dtw scan signal c from control 430 is applied to or gates 251 and 252 of level store address logic 290 frame signal n from counter 503 then passes through and gate 236 to the n address input of store 210 and gate 258 is responsive to the output of or gate 252 to pass level signal l from level counter 250 to the l address input of store 210 at the beginning of the dtw processing for the level the initial speech pattern segment frame from counter 503 of fig5 provides the speech pattern.