34 and hence the first bit b21 is output to the down highway dhw via the driver drv2 in this manner as shown in td in fig1 the transmission data td1 and td2 respectively supplied from the down highways dh 1 and dh 2 are transferred via the down highway dhw in bit multiplexing form the clock signal 2mclk from the time division switch tdsw is received by the receiver rec3 and then inverted by the inverter inv4 then the clock signal cr2 from the inverter inv4 is applied to the clock terminal c of the flip flop ff6 and the clock signal cr1 from the receiver rec3 is applied to the clock terminal c of the flip flop ff5 the data td received via the receiver rec2 is applied to the data terminals d of the flip flops ff5 and ff6 via the inverter inv5 the flip flops ff5 and ff6 respectively latch data in synchronism with the clock signals applied to the respective clock terminals c hence as shown in rd1 and rd2 in fig1 it is possible to separately receive data segments related to the down highways dh 1 and dh 2 the transmission clock signal with respect to the up highway uhw is generated from the clock signal cr2 from the inverter inv4 by the inverters inv6 and inv7.