the registers reg 0 to reg 7 become data 0 a reset circuit 10 u2032 outputs a reset signal for example data 1 accordingly after data 1 is taken into the register reg 7 the last stage and then data 0 is taken in again all the outputs from the registers reg 0 to reg 7 become data 0 the reset circuit 10 u2032 generates a reset signal for example data 1 in response to this in such case the synchronizing clock that makes the register reg 7 to transit from data 1 to data 0 is not used for an operation for the shift register 1 to transit data 1 that is a period from timings t 8 to t 9 is a dead cycle when data 1 does not transit between registers on the other hand the shift register 1 of this embodiment inputs outputs from the n 1 registers in this embodiment the registers reg 0 to reg 6 which is excluding the last stage into the reset circuit 10 by such connection when data 1 transits from the register reg 6 which is n 1 stage to the register reg 7 which is n stage all the outputs from the registers reg 0 to reg 6.