three control bits that are encoded onto the pixel clock represent horizontal sync vertical sync and data enable the inverse of data enable is also called blanking although three bits have eight possible combinations only five of those combinations are used for the three control bits those five combinations for the data enable horizontal sync and vertical sync in that order are 000 001 010 011 and 111 the other three combinations 100 101 and 110 are not used the timing diagram of fig2 shows a typical timing relationship of the three control bits timing signal 100 is the vertical sync timing signal 102 is the horizontal sync timing signal 104 is the data enable as shown in fig2 the data enable signal 104 only goes active while the vertical sync 100 and horizontal sync 102 are inactive therefore there are only five valid combinations of the three control bits in the preferred embodiment the five combinations of the three control bits horizontal sync vertical sync and data enable are encoded on the lvds pixel clock since the phase detector of the receive pll 198 is designed to work on the rising edges of the pixel clock the duty cycle of the pixel clock is irrelevant the.