deposited or otherwise formed electron barrier layer a charge collection electrode 108 is patterned into a two dimensional array of pixel electrodes that are under charge generator layer 104 or are embedded at a bottom surfaces thereof an electron blocking layer 106 may cover pixel electrodes 108 also called charge collection electrode a read out circuit is interposed between charge generator layer 104 and a substrate 114 and comprises respective signal storage capacitors 112 coupled electrically with the pixel electrodes and a thin film transistor tft array comprising respective gating transistors 110 coupled electrically with the junctions between the pixel electrodes and the signal storage capacitors transistors 110 are normally in an off state but can be enabled turned on by a gating signal delivered over gate pulse line 116 to thereby deliver charge accumulated in signal storage capacitors to a charge amplifier 118 a programmable high voltage power supply 120 applies a positive potential to top electrode 100 relative to ground and to grounded signal storage capacitors 112 to thereby induce an electrical field in charge generator layer 104 additional electrical fields can be generated as well for example by forming and appropriately biasing special electrodes that extend into the underside of charge generator layer 104 between adjacent charger collector.