cells are repaired as described above the originally assigned normal data input and output lines are connected to the data transfer lines like in the normal state in the columns having numbers higher than that of the column having the faulty cells the data transfer lines corresponding to the columns having numbers equal to and less than that of the column having the faulty cells are connected to the normal data input and output lines or the redundancy data input and output lines corresponding to the columns preceding by one column therefore the difference of lengths of the data paths of the respective columns during the redundancy operation are reduced fig9 is a block diagram showing a second embodiment of a faulty cell repairing circuit applied to a memory device of fig3 referring to fig9 the present embodiment relates to faulty cell repairing circuits for memory devices having a normal memory cell block including first second and third normal columns and a redundancy memory cell block having first and second redundancy columns a faulty cell repairing circuit of the memory device according to the present embodiment includes first second and third normal data input and output lines mio 0 mio 1 and mio 2 first and second redundancy data input and output lines rio 0 and rio 1 first second and third data transfer lines tio 0 tio 1 and tio 2 and first second and third switches 901 903 and 905 the first second and third normal data input and output lines.