p q r of the first memory 41 is as shown in formula 35 the controller generates addresses p q r of the first memory 41 so that the first outer parity generated in the first outer error correction encoder 43 may be stored in the first memory 41 according to formula 35 for second outer error correction coding the second data block stored in the first memory 41 is delivered into the second outer error correction encoder 44 there are n1 u00d7 l codewords for second outer error correction coding and information elements of one codeword are composed of d1 symbols herein the codeword for second outer error correction coding is supposed to be f8 s8 s8 0 1 n1 u00d7 l 1 besides the information element of codeword f8 s8 is supposed to be g8 s8 t8 t8 0 1 d1 1 the relation between addresses s8 t8 of information element g8 s8 t8 of codeword f8 s8 and addresses p q r of data e2 p q r stored in the memory is shown in formula 36 the first controller 45 generates addresses p q r of the first memory 41 so as to deliver the information elements g8 s8 t8 of codeword f8 s8 sequentially into the second outer error correction encoder 44 the second outer error correction encoder 44 encodes the entered information element g8 s8 t8 and generates a second outer parity the parity element generated when the information element g8 s8 t8 of codeword f8 s8 is processed by second outer error correction coding is supposed to be g8p s8 u8 u8 0 1 d2 1 at this time the codeword is.