same way in both fig1 and 2 the truth table executed by comparator 30 is identical to the truth table executed by comparator 20 but with logic layer 16 eliminated this is of great practical utility since it substantially speeds up the comparison process and reduces the number of transistors and the circuit area required for the comparator fig3 is a simplified top view of portion 40 of integrated circuit 42 illustrating how a fixed reference value c 3 0 is wired into the circuit of fig2 using programmable connection cells 32 fig4 5 are views similar to fig3 but according to further embodiments of the present invention fig3 4 correspond to programmable connection cell 32 1 electrically coupled between bus 12 and logic circuit 18 1 39 fig5 corresponds to cell 32 2 electrically coupled between bus 12 and logic circuit 18 2 39 connection leads 33 comprising in the example of fig2 4 leads 33 11 33 12 33 13 33 14 are coupled to inputs gh ph gl pl of logic circuit 18 1 passing underneath or above connection leads 33 and generally insulated therefrom are power bus and ground connection leads 44 comprising logic level 34 1 34 e g vcc on lead 44 1.