same tiered substrate structure comprising the p layer 12 n layer 14 and n layer 16 are provided together with trenches 18 and 20 the thermal sio 2 layer 22 and si 3 n 4 layer 24 with the cvd sio 2 layer 26 form a common starting point as in the first preferred embodiment other insulation layers may be used also boron ions are implanted into the trench bottoms for the formation of a p doped channel stop 32 this embodiment differs from the first embodiment in that the next step is the application of a photoresist 40 completely covering the substrate surface and filling each of the trenches using known techniques the resist 40 is opened over trenches where contact is desired fig4 illustrates the structure after an rie step has opened the trench bottom and removed some of the top oxide layer typically rie in a timed etch step to remove oxide from the trench 20 to form the 34 future 34 silicon substrate contact that is fig4 illustrates a structure having trench 20 with oxide removed such that the trench is opened for contact while trench 18 remains filled with photoresist material this timed etching also opens the area above trench 20 by selective removal of the cvd oxide 26 the photoresist 40 is then removed referring now to fig5 subsequent steps and the next intermediate stage of the device are illustrated in fig5 a selective epitaxial p doped silicon zone 44 has been deposited and grown in the substrate contact.