the width of the encoded data bus as shown in a related application ser no 08 697 969 entitled 34 method and apparatus for built in self test of integrated circuits 34 which is now abandoned also assigned to the assignee of the present application and incorporated by reference herein in its entirety for all purposes the small number of lines required to be routed is an example of efficiency of this invention this implementation requires only one more line than an implementation that does not distinguish between row and column addresses the main controller shown in fig2 coordinates and synchronizes the tests that are conducted on the individual memories row and column address clocks 13 and 14 address initialization signal 15 address reset signal 16 and increment decrement signal 17 control generation of the addresses for the memory although this controller requires two address counters rather than the single counter required for the undifferentiated case the counters are smaller the number of bits in the two counters combined in most cases equals the number of bits in the single counter used in the undifferentiated case therefore the total chip area used by the counters in the present invention is similar to the chip area of the single counter in the undifferentiated approach referring again to fig1 the decoder 85 decodes the pattern information and provides data to the memory under test this data is decoded and asserted onto the data bus 86 this signal and the addresses are synchronized by the local timing de skewing circuit 70 the signals on the data bus 81 address bus 84 and control line 83 exercise.