second group of parallel data bits in response to the data strobe signal the first transmission circuit can be configured to transmit each of the parallel data bits of the first group to each of a plurality of corresponding output terminals in response to a first write signal the second transmission circuit can be configured to transmit each of the parallel data bits of the second group to each of a plurality of corresponding output terminals in response to a second write signal moreover the first and second write signals can be alternately activated with a predetermined time difference the serial data bits of the first group can be output right after the output of the serial data bits of the second group and the data input buffer can further include an output latch for latching data bits in each output terminal wherein the output latch latches a respective data bit in each output terminal until the first write signal is activated and then the second write signal is activated or until the second write signal is activated and then the first write signal is activated according to additional embodiments of the present invention a data input buffer can include a conversion circuit configured to output odd data bits out from a plurality of serial data bits to a first node in response to a data strobe signal and to output even data bits from the serial data bits to a second node in response to a data strobe signal a first latch circuit can be configured to latch respective data bits in the first.