bonding wires 104 as illustrated in fig3 pads 1 8 and 9 12 are arranged to form two shallow u201c v u201d shapes having legs arranged obliquely with respect to one of the edges 106 of chip 100 as illustrated in fig3 this arrangement of the pads allows the bonding wires 104 between the several end pads on each leg of the u201c v u201d shape i e pads 1 3 6 8 9 11 and 14 16 to be bonded to a conventional lead frame 102 while improving the separation between adjacent bonding wires and the overlap of other pads to reduce the likelihood of shorting increasing the oblique angle between a group of pads and the edge of the chip can increase the number of pads that may be successfully bonded to the lead frame and permit the mounting of semiconductor devices having an increased number of pads fig4 is a plan view showing an arrangement of pads 1 10 on a semiconductor chip 100 according to a second exemplary embodiment of the invention with portions of a conventional lead frame 102 being connected to the pads with bonding wires 104 as illustrated in fig4 pads 1 5 and 6 10 are arranged in opposing u201c v u201d shapes configured to allow connection to a conventional lead frame 102 using bonding wires 104 of substantially equal length by allowing the use of bonding wires of substantially equal length this pad arrangement reduces signal skew and improves signal integrity fig5 is a plan view of a pad arrangement in accordance with a third exemplary embodiment of the invention as illustrated in fig5 a plurality of memory cell.