and 2 a when the circuit is powered up both vw 0 and vw 1 are at vddh whereas vr is at vss when a write operation occurs vw 0 is temporarily switched to 0 from vddh thereby allowing pm 0 to conduct while vw 1 stays at vddh the switch at vw 0 is represented by a falling edge 202 v 0 is then built up to vddh as represented by a rising edge 204 thereby building up carrier charges in nm 2 until there is a high electric field between the drain and source of nm 2 when a voltage difference between the drain region and the source region vds and a voltage difference between the gate region and the source region vgs is bigger than a predetermined threshold voltage the hot carrier effect is caused due to hot carrier effect the current ids going through nm 2 becomes lower relative to that going through nm 3 nm 2 will now have a low conductance and a high resistance and is considered u201c programmed u201d when vw 0 is switched back to vddh as represented by a rising edge 206 pm 0 ceases to conduct throughout this period since vw 1.