and optional other processors not shown are shown as separate hardware entities in other embodiments the number of processors may differ as may the boundary of various components and functional units in some embodiments the processors may be replaced by separate hardware execution threads or u201c logical processors u201d running on one or more physical processors processors 202 212 222 may contain certain special circuits or logic elements to support secure or trusted operations for example processor 202 may contain secure enter senter logic 204 to support the execution of special senter instructions that may initiate trusted operations processor 202 may also contain bus message logic 206 to support special bus messages on system bus 230 in support of special senter operations in alternate embodiments memory control functions of chipset 240 may be allocated to circuits within the processors and for multiple processors may be included on a single die in these embodiments special bus messages may also be sent on busses internal to the processors the use of special bus messages may increase the security or trustability of the system for several reasons circuit elements such as processors 202 212 and 222 or chipset 240 may only issue or respond to such messages if they contain the appropriate logic elements of embodiments of the present disclosure therefore successful exchange of the special bus messages may help ensure proper system configuration special bus messages may also permit activities that should normally be prohibited such as resetting a platform configuration register 278 the ability of potentially hostile untrusted code to spy on certain bus transactions may be curtailed by allowing special bus messages to be issued only in response to special security instructions additionally processor 202 may contain secure memory 208 to.