with line 10 a and or 13 u2014 are u2014 at a relatively low level of resistivity u2014 electrically connected with each other transfer gate 7 is switched off i e both the connections of transfer gate 7 u2014 connected with line 10 b and or 15 u2014 are u2014 relatively highly resistively u2014 disconnected from each other and transfer gate 6 is switched on and or through i e both the transfer gate connections of transfer gate 6 u2014 connected with line 14 and or 10 b u2014 are u2014 at a relatively low level of resistivity u2014 electrically connected with each other the output line 11 b of the clock receiver circuit device 1 is thereby u2014 at a relatively low level of resistivity u2014 electrically connected with the ground potential present at line 13 and u2014 relatively highly resistively u2014 electrically disconnected from line 12 which is connected with the supply voltage vddq the clock signal bout emitted onto output line 11 b is thereby u2014 corresponding with the second input signal bclk and as shown in fig2 u2014 u201c high logic u201d in addition the output line 11 a of the clock receiver circuit device 1 is u2014 at a relatively low.