31 for ntsc store 32 which is an and gate supplies an end of sample pulse fig3 d on horizontal line 30 26 4 to sample finished transfer circuit 56 the horizontal synchronization pulses are also supplied to a delay circuit 34 which may be formed for example as a one shot multivibrator with a 20 microsecond delay to cause the sample pulses which are derived from the horizontal synchronization pulses to occur in the middle of the horizontal lines another one shot with a 20 microsecond delay comprises sample pulse generator 36 which supplies sample pulses to enable gate 26 and to store 32 shift pulses shown in fig3 c are applied to register 22 from gate 26 so that register 22 stores levels high or low indicating the phase relationship for lines 26 29 for ntsc or 23 26 for pal these lines occur at the same position of the picture for the two systems but have different numbers due to the different numbering conventions for the two systems a four bit parallel bus carries these levels to decoder 37 decoder 37 compares these levels to a fixed code this code is determined by whether a pal or ntsc signal is being applied to the circuit the decoder 37 is controlled by a signal from a manually operated pal ntsc switch not shown terminal 38 receives a high signal that indicates that a threading operation is not going.