output of the adder u2018 frequency u2019 is accumulated in the dco accumulator consisting of the second adder and the register running on the master clock frequency u2018 mclk u2019 the carry bit u2018 dco_overflow u2019 of the accumulator is used as enable signal for the overflow counter 12 which counts how many times the dco has overflowed the counter wraps around when it reaches the maximum 2 dco u2014 acc u2014 width u2212 1 the overflow signal u2018 dco_overflow u2019 and the remainder u2018 remainder u2019 of the dco accumulator are also used as jitter shaping module inputs the u2018 remainder u2019 consists of all bits of the accumulator excluding the most significant bit u2018 dco_overflow u2019 the overflow counter output u2018 low_freq_ovf u2019 coming directly from one of the counter bits represents an output clock with desired frequency which is chosen by the output clock frequency control bus u2018 clk_freq u2019 the u2018 low_freq_ovf u2019 is also used as the jitter shaping module input the overflow counter is a basic binary counter running on the master clock frequency u2018 mclk u2019 with counting enable signal u2018 dco_overflow u2019 to perform jitter shaping on the overflow counter output u2018 low_freq_ovf u2019 the jitter shaping module is used for a given clock frequency and accumulator width the dco output clock frequency can only have discrete values therefore the desired output clock frequency has limited accuracy the remaining value in the dco accumulator at a carry u2018 remainder u2019 represents the exact phase error of the.