could be used in principle as counters 21 and 22 although in the exemplary embodiments of fig4 and 5 which are preferred systems the counters previously described are used because they are especially well adapted to integrated mos circuit technology the number of locations of each shift register 38 39 defines the maximum word length which that shift register can accept as there are two shift registers 38 39 the counter in fig4 is an 8 bit counter and the words contained within the shift registers 38 39 are transported to the input z of the serial adder at a repetition frequency equal to the shift frequency the number of shift register locations the serial adders are either so called half adders or full adders in any case the serial adders 36 and 37 are so embodied as to form an output s as the sum of the prevailing signals at the inputs x and z and to transport any possible carry amount to the next word location thus the serial adders add a particular pulse from the air data frequency f lm or the correction frequency f k to the lsb of the word already contained in the associated shift registers 38 or 39 in this manner the pulses of the frequencies f lm or f k increase the.