used in the first embodiment and the method of controlling the equalizer circuit are implemented in combination a lower current consumption can be performed while an increase in the memory cell area and a reduction in the accessing speed are suppressed in the second embodiment of fig5 the bit line equalizer circuit 107 according to the first embodiment shown in fig1 is replaced by two bit line equalizer circuits 132 and 133 which are connected between the bit lines bllz and bllx and between the bit lines blrz and blrx respectively the brs generator circuit 131 inputs the equalization control signal eq and outputs the bit line equalization control signals brsl and brsr that have been converted into voltage which are inputted to the bit line equalizer circuits 132 and 133 respectively the structure and operation of the bit line equalizer circuits 132 and 133 are identical with those of the equalizer circuit 107 fig1 even in the case where the bit line separation gate of the unselected memory block is kept in the nonconductive state the circuit structure can solve a problem such as the destroy of data due to floating of the bit line potential similarly in the circuit structure shown in fig5 it is.