of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor including precharging a sense node to thereby precharge a bit line coupled to the cell string for a program or data read operation and simultaneously resetting a cell channel in a state in which the drain select transistor is turned off the source select transistor is turned on and the memory cells are turned on by applying a first voltage to a number of word lines coupled to the memory cells during a first time period wherein the first time period is less than a bit line precharge time period application_number US 64726909 A description hereinafter some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings the figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of the disclosure fig2 a is a block diagram of a nonvolatile memory device according to an embodiment of this disclosure referring to fig2 a the nonvolatile memory device 200 includes a memory cell array 210 a page buffer unit 220 a y decoder 230 an x decoder 240 a voltage control unit 250 and a control unit 260 the.