the disclosure of which is incorporated by reference herein in its entirety the ddr2 driver circuit 200 comprises an external termination resistor 210 e g an equivalent termination resistance a termination resistor etc with a resistance of 25 ohms an in series on chip resistor 220 e g a stub series resistor an off chip resistor etc with a resistance of 20 ohms a nmos transistor 230 and a pmos transistor 240 are both shown as either one of which can be calibrated although not both at the same time fig2 illustrates only one of the multiple ddr2 fingers for simplicity additionally a counter such as counter 120 coupled to the gates of the nmos transistor 230 and the pmos transistor 240 is also not shown for simplicity in one embodiment the external termination resistor 210 and the in series on chip resistor 220 are set such that the transistor impedance is calibrated to 18 u00b1 3 ohms the specifications of the sstl u2014 18 standard set the external termination resistor 210 to be 25 ohms to achieve the minimum current the external termination resistor 210 terminates to v tt which is half the supply voltage v ddq the sstl u2014 18 standard sets v ddq at 1 8 volts and thus v tt is 0 9 volts v ss is connected to ground a further simplified and equivalent ddr2 driver application substitutes either one of the pmos transistor 240 or the nmos transistor 230 although not both at the same time with a single impedance for calibration calculation purposes with a transistor impedance 330.