detected by the receivers fig1 indicates a modification in which the baseband interface is the same as that for annex a except that the sync inversion block becomes a sync replacement block the a b switch responsible for inserting the measurement packets receives both is control and synchronization from the u2018 clocks sync generation and control block u2019 the clock the u2018 clocks sync generation and control block u2019 applies an fec phase offset to the frame sync counter to generate the measurement insertion synchronization the u2018 frame sync counter u2019 gives an output every 47 reed solomon frame syncs approximately 10 times a second the u2018 10 byte capture fifo u2019 captures the first 10 bytes after each u2018 reed solomon frame sync the u2018 control block u2019 reads the capture fifo output to calculate the required fec phase offset the u2018 control block u2019 carries out a correlation of the output from the capture fifo with the first 6 bytes of the measurement packet 1 to determine if phase alignment is achieved if there is no correlation the fec phase offset is incremental to delay the measurement packet insertion point relative to the u2018 frame sync counter u2019 output this process is continued until correlation is achieved since the calculation of the correct bits to.