124 address signals are received via an address link 126 that are decoded at address decoder 106 to access the memory array 104 address buffer circuit 116 latches the address signals the memory cells are accessed in response to the control signals and the address signals it will be appreciated by those skilled in the art that additional circuitry and control signals can be provided and that the memory device of fig1 has been simplified to help focus on the invention fig2 is a schematic of a nand memory array 200 as a portion of memory array 104 in accordance with another embodiment of the invention as shown in fig2 the memory array 200 includes word lines 202 1 to 202 n and intersecting local bit lines 204 1 to 204 m for ease of addressing in the digital environment the number of word lines 202 and the number of bit lines 204 are each some power of two e g 256 word lines 202 by 4 096 bit lines 204 the local bit lines 204 are coupled to global bit lines not shown in fig2 in a many to one relationship memory array 200 includes nand strings 206 1 to 206 m each nand string includes floating gate transistors 208 1 to 208 n each located at an intersection of a word line 202 and a local bit line 204 the floating gate transistors 208 represent non volatile memory cells for storage of data the floating gate transistors 208 of each nand string 206 are connected in series source to drain between a source select gate 210 e g a field effect transistor fet and a drain select gate 212 e g an fet each source.