this step employs arsenic rather than the more conventional phosphorous arsenic is employed since it will diffuse more slowly than phosphorous so that the source regions will not unduly deepen during subsequent high temperature processing steps the arsenic atoms define the n type source regions 50 and 51 which are annular regions surrounding the p regions 42 and 43 following this operation an annealing step is carried out wherein the wafer is heated at about 975 u00b0 c for 20 minutes in nitrogen gas and thereafter for 100 minutes in dry oxygen while the temperature is ramped down it is important to note that the gate oxide still has not been applied to the device and is not subject to any thermal cycling to this point the wafer of fig5 is then subjected to a third mask step in which the mask is provided with openings to enable the formation of a photoresist coating over the various dots 36 and 37 the photoresist coating is shown in fig6 and 7 as the photoresist coatings 52 and 53 all exposed oxide is then removed by an appropriate oxide etch as shown in fig7 thereafter the photoresist layers 52 and 53 are stripped and.