validity of pulses rather the signals generated by comparator 76 are combined with those produced by comparator 74 to achieve the desired results in accordance with the subject invention the signals of the second comparator means 76 are supplied to a delay means 84 delay means 84 may be defined for example by a monostable multivibrator the length of the delay is calculated based on various factors such as the particular threshold levels which have been selected however the time period must be sufficiently long enough such that the output of delay means 84 occurs during the time when the pulses have exceeded the upper threshold level t 1 fig4 c illustrates the output of the delay means when supplied with the signals generated by comparator 76 shown in fig4 b the output a 3 b 3 and c 3 of delay means 84 is identical in character to the output of comparator 76 except for a uniform delay the output from delay means 84 and the output from the first comparator means 74 are then supplied to a gate means 90 preferably gate means 90 consists of a logical circuit such as an 34 and 34 gate as well known in the art an 34 and 34 gate will generate a positive going output pulse only when both incoming signals are high it is to be understood of course that if it is desired that a low signal be indicative of a.