present invention has application in any device requiring the generation in response to an input pulse that possibly has less than a minimum length duration of an output pulse guaranteed to have at least the minimum duration referring now to fig2 a block diagram of the address transition circuitry for the nonvolatile memory device is illustrated address transition circuitry 200 has three functional components these components are address transition detector 210 safe length pulse generator 300 and transition preprocessor 250 the input to address transition detector 210 is a multi bit address signal specifying an address to be read address transition detector 210 detects a change in one or more bits of the input address signal single bit transition detectors such as a 1 transition detector 220a and a 2 transition detector 220b each detect a transition on a different address bit line of the multi bit address signal and pulse summation circuit 230 combines these detections into a single address detection signal thus upon detecting an address transition address transition detector 210 generates an address transition detected pulse atdp in the prior art pulse atdp would feed directly into transition preprocessor 250 upon receipt of pulse atdp transition preprocessor 250 will prepare the memory array for the read operation of the new address when pulse atdp ends transition preprocessor 250 will be ready for the read signaled by the new address if the address transition detected by address transition detector 210 was.