voice commands fig7 is a block diagram of an example processor system 1000 adapted to implement the methods and apparatus disclosed herein the processor system 1000 may be a desktop computer a laptop computer a notebook computer a personal digital assistant pda a server an internet appliance or any other type of computing device the processor system 1000 illustrated in fig7 includes a chipset 1010 which includes a memory controller 1012 and an input output i o controller 1014 as is well known a chipset typically provides memory and i o management functions as well as a plurality of general purpose and or special purpose registers timers etc that are accessible or used by a processor 1020 the processor 1020 is implemented using one or more processors the processor 1020 includes a cache 1022 which may be implemented using a first level unified cache l1 a second level unified cache l2 a third level unified cache l3 and or any other suitable structures to store data as persons of ordinary skill in the art will readily recognize as is conventional the memory controller 1012 performs functions that enable the processor 1020 to access and communicate with a main memory 1030 including a volatile memory 1032 and a non volatile memory 1034 via a bus 1040 the volatile memory 132 may be implemented by synchronous dynamic random access memory sdram dynamic random access memory dram rambus dynamic random access memory rdram and or any other type of random access memory device the non volatile memory 1034 may be implemented using flash memory read only memory rom electrically erasable programmable read only memory eeprom and or any other desired type of memory device the processor system 1000 also includes an interface circuit.