outputs a control signal to the selection circuit 60 according to the result of the comparison in the latching stage the scan line 20 maintains the first switch 12 off the first clock 62 maintains the third switch 54 on and turns on the forth switch 56 and the second clock 64 turns off the second switch 52 to confirm the output signal of the comparator 58 finally in the oscillating stage the states of all switches are maintained when the voltage stored in the storage capacitor 14 is higher than the reference voltage v 50 70 the control signal is a high voltage and the selection circuit 60 outputs the common voltage v com 66 to the liquid crystal capacitor 16 when the voltage stored in the storage capacitor 14 is lower than the reference voltage v 50 70 the control signal is a low voltage and the selection circuit 60 outputs the inverted common voltage xv com 68 to the liquid crystal capacitor 16 please refer to fig6 fig6 is a diagram of the voltages of the pixel driver 50 during operation a voltage v scan is the voltage of the scan line 20 v data is the voltage of the data line 18 v 50 is the voltage of the reference voltage v 50 v ck 1 is the voltage of the first clock 62 v ck 2 is the voltage of the second clock 64.