which the measured delay equals the msd is designated as the cluster boundary and is added to the list of clustered nodes steps 320 and 322 the list of clustered nodes identifies the nodes where a terminator is installed if there remain other components and nodes within the circuit this process continues step 324 until the entire circuit is divided into one or more clusters identified by a list of clustered nodes this adaptive partitioning or clustering process is depicted by the exemplary circuit of fig4 a and 4b which are shown herein for illustrative purposes only referring to fig4 a there is shown an exemplary driver 400 driving a load circuit that includes a network of components 402 in this example the load circuit is divided by the synthesis process into three clusters 404 1 404 2 and 404 3 each cluster 404 exhibits a delay equal to the measured maximum stub delay and can be separately terminated terminations 406 1 406 2 and 406 3 are then installed at the terminus node of each driver as shown the selection of the type of termination is described as above thus the termination synthesis technique of the present invention provides an automated method of deriving optimum termination schemes for electronic circuits regardless of their size and complexity while the above is a complete description of a specific embodiment of the present invention it is possible to use various alternatives modifications and equivalents for example.