detailed diagram of a compensation circuit 102 having compensation interpolation in accordance with the present invention conditions to be compensated conventionally vary in a relatively smoothly form across a crt screen such as across a scan line and between adjacent scan lines hence in many applications it may be acceptable to store compensation parameters for a limited subset of spaced apart calibrated pixels and then to interpolate between the calibrated pixels in order to derive the compensation parameters for the in between uncalibrated pixels for example in a medium resolution 512 pixels per line by 512 lines per frame monitor configuration the compensation memory 222 may be implemented to store a compensation parameter for each 32nd pixel involving a total of 256 compensation parameters 16 by 16 compensation parameters per monitor this can reduce the memory requirement and the related efforts required to generate the compensation parameters from 262 144 compensation parameters in the fig2 type configuration to 256 compensation parameters in this fig3 configuration and this can reduce the adc resolution requirement from 9 bits per adc in the fig2 type configuration to 4 bits in this fig3 configuration similarly in a high resolution 1024 pixels per line by 1024 lines per frame monitor configuration the compensation memory 222 may be implemented to store a compensation parameter for each 16th pixel yielding a total of 4096 compensation parameters 64 by 64 compensation parameters per monitor this can reduce the memory requirement from.