cells sram memory cells flash memory cells or some other types of memory cells the memory device 300 includes a command decoder 306 that receives memory commands through a command bus 308 and generates corresponding control signals within the memory device 300 to carry out various memory operations row and column address signals are applied to the memory device 300 through an address bus 320 and provided to an address latch 310 the address latch then outputs a separate column address and a separate row address the row and column addresses are provided by the address latch 310 to a row address decoder 322 and a column address decoder 328 respectively the column address decoder 328 selects digit lines extending through the array 302 corresponding to respective column addresses the row address decoder 322 is connected to word line driver 324 that activates respective rows of memory cells in the array 302 corresponding to received row addresses the selected data line e g a digit line corresponding to a received column address are coupled to a read write circuitry 330 to provide read data to a data output buffer 334 via an input output data bus 340 write data are applied to the memory array 302 through a data input buffer 344 and the memory array read write circuitry 330 the command decoder 306 responds to memory commands.