at the subsequent stage for example if the launch capture switching signal is u201c 1 u201d the active signal lo 3 is selected and output to the or circuit 123 on the other hand if the launch capture switching signal is u201c 0 u201d the active signal co 3 is selected and output to the or circuit 123 since the clock is provided for each of the clock domains cd 1 to cd 3 at a high speed the high speed selection circuits 111 to 113 are difficult to dispose within the control circuit 110 because of the restrictions of the layout therefore the switching to the launch side or the capture side can be performed at speed by embedding the high speed selection circuits 111 to 113 at the outside of the control circuit 110 especially just before the gate clock buffers gcb 1 to gcb 3 to the or circuits 121 to 123 the active signals selected by the selectors sel 1 to sel 3 are input and the mask signals en 1 to en 3 are input from the control circuit 110 the mask signals en 1 to en 3 are output only to the clock domains cd that need the launch edge capture edge to the gate clock buffers gcb 1 to gcb 3 the.