and queueing events are described with verilog hdl operating in conversion module 71 this implementation is exemplary and it should be clear to those skilled in the art that such race condition resolution techniques may be performed in other languages or in code operating in driver software referenced above operatively connected to pli or vhpi code without a queuing system such as that disclosed above changes in multiple trigger signals that occur at the same time would result in unpredictable behavior from both the implemented fpga 81 and the hdl models 11 of design components running in simulation when trigger signals change in logic simulator 20 events are scheduled in logic simulator 20 in response to the those changes those events include the disclosed events that issue input vectors to the disclosed implemented fpga 81 however when multiple trigger signals change at the same time more than one trigger signal may update in logic simulator 20 prior to the scheduled input vector transfer this behavior causes the conversion module 71 that transfers input vectors to implemented fpga 81 to issue changes to more than one trigger signal to the implemented fpga 81 via signals 60 a and or 61 a simultaneously this creates a.