resist 602 the deposition of a layer of dielectric material in a similar manner as described above in fig9 the planarization of the resultant structure in a similar manner as described above in fig2 and the removal of the sacrificial layer 502 of fig2 in a similar manner as described above in fig2 the resultant structure includes an isolation fin 2602 having sloped sidewalls 2601 that are arranged at an oblique angle u03c6 relative to the planar surface 203 of the substrate 202 once the sacrificial layer 502 has been removed the similar processes as described above in fig1 18 may be performed to fabricate an arrangement of multi fet devices that are isolated by an isolation region 1201 that includes the isolation fin s 2602 the methods and resultant structures described above provide an arrangement of multi fet devices on a substrate that are isolated by isolation fins that define isolation regions on the substrate the isolation fins provide a dummy gate stack with a more uniform height the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention as used herein the singular forms u201c a u201d u201c an u201d and u201c the u201d are intended to include the plural forms as well unless the context clearly indicates otherwise it will be further understood that the terms u201c comprises u201d and or u201c comprising u201d when used in this specification specify the presence of stated features integers steps operations elements and or components but do.