row bias switch 130 may select a lower operative voltage vhv in such a way to provide a lower row bias voltage rb the selection of the desired set of bit lines bl is instead carried out by means of a column decoder 135 and a column selector 140 the column decoder 135 receives the column address cadd and accordingly generates a plurality of column selection signals yc each associated with a respective bit line bl the column decoder 135 determines the set of bit lines bl identified by the received column address cadd and asserts u2014 e g to the ground voltage u2014 the column selection signals yc associated with said bit lines bl the other column selection signals yc are instead deasserted u2014 e g to the supply voltage vdd the column selection signals yc are provided to the column selector 140 which accordingly enables the bit lines bl associated with the asserted column selection signals yc by connecting them to a read program r p circuit 145 that includes all the components e g sense amplifiers comparators reference current voltage generators pulse generators program load circuits and the like which are normally used for programming the desired logic values into the selected memory cells mc and for reading the logic values currently stored therein the other bit lines bl are instead kept insulated from the r p circuitry 145 the column selector 140 includes a plurality of controlled column switches 150 e g p channel mos.