pulse each time a square wave transition in one direction or the other but not both occurs each time the controller receives a pulse the cycle counter 97 and interval counter 101 are reset thereafter as illustrated in fig8 and previously described with respect to fig6 the controller idles until the next pulse is received from the transition detector then the interval counter value x i which is inversely related to the frequency of the just completed cycle of the incoming signal is transferred to a suitable bin in the memory 103 thereafter the interval counter is reset and the memory address is advanced next the controller tests the output of the cycle counter 97 to determine if the preset number of cycles n have been counted if not the controller cycles back to the idle point when the preset number of cycles n have been counted by the cycle counter 97 the interval counter value stored in the memory bins are nondestructively read out and summed thereafter the results of the summation is divided by the value of n to determine the mean time between pulses x as previously described x is inversely related to the mean frequency of the incoming signal then either phase jitter is determined in accordance with equation 1 or in accordance with equations 2 and 3 which route is followed depends on desired accuracy and acceptable system complexity next the signal.