being coupled to a corresponding bank enable line en1 en2 en3 the enable line of the first memory device within each memory bank 1a 2a 3a is also coupled to an odd field enable line enodd and the enable line of the second memory device within each memory bank 1b 2b 3b is also coupled to an even field enable line enev the input latch unit 20 and the input buffer latch unit 22 are equivalent to the input latch unit 10 and the input buffer latch unit 12 illustrated in fig3 the output buffer unit 24 contains a plurality of output buffer latches 62 72 that correspond to the memory devices contained within the memory banks the output buffer latches 62 72 are coupled to corresponding output latches 80 90 contained within the output latch unit 26 each of the output buffer latches 62 72 are coupled to a common output buffer enable line ob while each of the output latches 80 90 are coupled to corresponding output latch enable lines ol1 ol6 the memory controller 34 generates the various control signals ras cas r w en1 etc supplied to the input latch 20 the input buffer latch unit 22 memory banks 1 2 and 3 output buffer latch unit 24 output latch unit 26 and addressing units 28 32 fig4 also illustrates how the pixel data for the image illustrated in fig1 is stored in operation to prevent the occurrence of multiple addressing when reading the pixel data to provide a rotated image the pixel data for the first field is stored in the first memory devices 1a 2a 3a of each memory bank while the pixel data for the.