the downwardly curved portions of the substrate surface 54 since those portions of the substrate are shielded during the ion bombardment by the overhanging margins of the nitride masks 26 consequently these channel stops are inherently aligned with and spaced apart from the source and drain regions of the n channel fet eventually formed under the first surface area 34 of each of the wells 56 referring now to fig9 which show the well portions of two separate but neighboring or adjacent cmos devices it can be seen that this zone of ions 60 is also implanted beneath the exposed surface of the substrate 52 extending between the neighboring p wells 56 since the diffused edges of the wells 56 extend beyond the edges of the nitride masks 26 the zone 60 overlaps the periphery of each of the wells thus it forms a buried conductor that conductively interconnects the adjacent wells 56 in the present process this zone is preferably formed by a boron implant at 10 kev to obtain a surface concentration level of between 7 u00d7 10 13 to 2 5 u00d7 10 14 cm 2 a thick layer of oxide is then grown on the exposed portions of the substrate surface 52 and the remaining field oxide layer 32 by low temperature thermal oxidation in a suitable ambient to form a relatively thick final field oxide layer 64 as illustrated in fig7 this step is performed at a low temperature to prevent any further lateral diffusion.