nmos 419 and therefore the levels of the voltages vh and vl increase in contrast to this if the control voltage vtune is smaller than the reference voltage vth the levels of the voltages vh and vl decrease in fig4 vb 1 vb 2 and vb 3 represent bias voltages according to various exemplary embodiments the current mirror 42 includes a plurality of constant current power supplies having the same shape each of the constant current power supplies includes a pmos 421 a pmos 422 an nmos 423 and an nmos 424 connected in series between a power supply vdd and a ground gnd the voltage vh may be input to a gate of the pmos 421 and the voltage vl may be input to a gate of the nmos 424 in accordance with the levels of the voltages vh and vl a frequency control current ictrl_pll may be output from an output terminal in which a drain of the pmos 422 and a drain of the nmos 423 are connected to each other as described above in the current mirror 42 the frequency control current may be controlled on the basis of the voltages vh and vl input from the differential amplifier 41 and the frequency control currents ictrl_pll which have the same current value as each other and are of the same number as the cdr circuits are generated and delivered in the exemplary embodiments described above the oscillator osc in the pll circuit is a known current controlled oscillator ico however the oscillator in the pll circuit may be a voltage controlled oscillator vco that is controlled.