a reduced threshold voltage and high leakage current fig9 11 depict the improved process which is the focus of the present invention array processing for the improved process is identical with the processing for the conventional array as processed up through fig5 fig9 takes up immediately following the processing as described in fig5 referring now to fig9 the array of fig5 is shown following the conformal deposition of a silicon dioxide liner layer 91 a silicon nitride liner layer could be used in place of silicon dioxide liner layer 91 referring now to fig1 the array has been subjected to an anisotropic silicon dioxide etch which has created a silicon dioxide lining on the walls of tapered trenches 41 it will be noted that the anisotropic silicon dioxide etch has removed the portions of liner layer 91 from the bottoms of tapered trenches 41 referring now to fig1 a storage node polysilicon 2 layer 111 has been conformally deposited over the array surface such that it completely lines each tapered trench 41 following doping of the polysilicon 2 layer 111 with phosphorus the array is masked with a storage node plate photoresist mask 112 referring now to fig1 the array has been subjected to an isotropic polysilicon etch which creates individual storage node plates 121 following this etch photoresist mask 112 is stripped referring now to fig1 a capacitor dielectric layer 131 is conformally deposited over the array 39 s surface following which a polysilicon 3 cell plate layer 132 is conformally deposited from the final capacitor structure of fig1 it will.