processor core determines whether both an exception line and an exception enable bit are asserted i e true or set as previously mentioned a processor core masks interrupts by deasserting the exception enable bit in response to the exception line and or the associated exception enable bit not being asserted control loops on block 2404 in response to both the exception line and the associated exception enable bit being asserted control transfers from block 2404 to block 2406 in block 2406 the processor core deasserts resets the exception enable bit to prevent subsequent interrupts from interrupting the current interrupt next in block 2408 the processor core changes control flow to an appropriate interrupt handler then in block 2410 the processor core acknowledges the pending interrupt by issuing a mmio load to ipc 240 in response to the mmio load ipc 240 returns the event path number field of the row of ict 242 that corresponds to the physical processor thread and atomically in the same row sets the operating priority to the value of the event priority and resets the assigned field next in block 2411 the processor core pulls the event source number from the next idb of the event path number entry then in block 2412 the processor core executes a program that is registered to handle interrupts from the source specified by a value in the u2018 event source number u2019 field next in block 2414 following completion of the program the processor core issues a mmio store to ipc 240 to signal an eoi then in block 2416 the processor core resets the operating priority in.