test signal tm enable signals en lt 0 x gt and the verification read data s a lt 0 gt the read data control unit 400 selects one verification read data s a lt 0 gt from the verification read data s a lt 0 x gt applied through the switching unit 200 depending on the write addresses wadd lt 0 x gt during an activation period of the test signal tm the read data control unit 400 senses the verification read data s a lt 0 gt several times in response to the enable signals en lt 0 x gt to sequentially output the data into a global input output line rgio the latch control unit 500 sequentially outputs latch enable signals len which correspond to the data applied to the global input output line rgio during the activation period of the test signal tm to the read data latch unit 600 the read data latch unit 600 includes a plurality of data latches to store the verification read data s a lt 0 gt applied to the global input output line rgio in the plurality of data latches sequentially in response to the latch enable signals len the verification read data stored in the read data latch unit 600 is outputted to an external data output unit dq in response to a.