bits a b c and d provided that the corresponding control signal is asserted i e clka clkb clkc and clkd if the control signal is not asserted then a logic zero is passed instead the input stage circuits are operatively coupled to nor gates 120 and 122 as shown the outputs of which are themselves operatively coupled to nand gate 124 as shown finally the output of nand gate 124 is operatively coupled to output stage 126 which is enabled by the data enable input dataen as shown thus as shown in fig7 if all the control signals are asserted the output data returns the compressed bit according to the function data not not a b not c d circuit 110 therefore allows for error checking of memory cells wherein each memory cell is written with a test bit of logic zero if each of the memory cells is not defective the output bits a b c and d will yield a compression bit of not not 0 0 not 0 0 0 which is equal to the test bit if any of the memory cells is defective and otherwise returns an output bit of logic one the compression bit will also return a logic one since the expression not not a b not c d always returns a logic one in the case where at least one of a b c or d is logic one when only one of the control signals is asserted the output data returns just the output bit corresponding to that control signal according to the function data not not x 0 not 0 0 x where x is the output bit corresponding to that control signal in other words the output data passes the output bit corresponding to a.