second combinatorial logic output signal c2 that would result from operation of the fig1 circuit if signal a were false as further shown in fig2 multiplexer circuitry 26 is connected to receive the first and second combinatorial logic output signals c1 and c2 respectively generated by the true and false logic circuitry 22 and 24 the output signal a generated by the first logic block 20 serves as the select signal for the multiplexer circuitry 26 such that the multiplexer circuitry 26 provides the first combinatorial logic output signal c1 as the multiplexer output signal mux out when signal a is in the true logic state 34 1 34 in the fig2 embodiment and provides the second combinatorial logic output signal c2 as the multiplexer output signal when signal a is in the false logic state 34 0 34 in the fig2 embodiment in the fig2 embodiment of the invention the output mux out of the multiplexer circuitry 26 is provided as a further input signal to the first logic block 20 however those skilled in the art will appreciate that this signal can be utilized anywhere on the chip or provided as a chip output those skilled in the art will further appreciate that the multiplexer circuitry 26 can be implemented utilizing any of a number of well known logic configurations in some cases the utilization of and or multiplexing logic will further enhance the speed of operation fig3 and 4 provide a specific example of the implementation of the present invention fig3 shows a simple logic configuration that corresponds to the fig1 circuit specifically the first logic block 10 provides the output signal a to a nand gate 30 of combinatorial logic block 12 the nand.