conventionally required for this operation it can be seen that a counter having any number of bits can be tested completely if two or more sections are treated in the aforementioned manner it becomes inefficient however to separate a counter into too many sections if the size of the counter is relatively small in general if one section has n and the other has n 1 bits then 2 2 n 1 3 clock cycles are required to test the counter completely it is most efficient to separate the odd bit counter into two sections differing in size from one another by only one bit in the case of equal sections of n bits each however the number of clock cycles required to test a counter completely by the aforementioned inventive technique is 2 n referring now also to fig1 which is depicted as fig1 a 11b for convenience a schematic circuit diagram is shown depicting apparatus for carrying out the present invention the fig1 depicts a dynamic random access memory dram controller which controls the address path between a processor not shown and a dram array not shown the controller uses an 11 bit row latch and an 11 bit column latch and counter.