the operation of the incoming time division switching device will now be explained with the aid of fig5 the first line je 0 31 of this figure contains a succession of eight bits eb0 eb1 eb7 belonging to time slot it0 all the interfaces on the inputs of switching circuits cce1 to cce8 are synchronous each bit duration is divided into eight parts the durations u03c40 u03c41 u03c42 and u03c43 being used for writing into memory whilst durations u03c40 39 u03c41 39 u03c42 39 and u03c43 39 are for reading the next line u03c4 in fig5 represents a clock signal whose frequency is eight times the bit rate this signal is applied to the count input of counter cee1 and is also applied to the input of register rege in this manner the various data available at the various instants u03c40 u03c41 u03c42 and u03c43 are obtained on the output of register rege line cee1 in fig5 shows the variation of the contents of counter cee1 the next line u03c4 39 shows a signal which is the complement of that shown on line u03c4 the following table illustrates the writing of data into memory me table i__________________________________________________________________________writing into memory menumberoftime write line pageslotsintervals ed1 ed2 ed3 ed4 ed5 ed6 ed7 ed8 cee3 cee1 addressed cee2 selected__________________________________________________________________________.