routings pl 1 a and pl 1 b are arranged aligning the top edge and bottom edge of the outline ol 1 for transmitting positive bias and ground bias respectively thus the distance between the parallel power routings pl 1 a and pl 1 b equivalently defines the height h 1 of the cell cl 1 after the outline ol 1 and the layouts of the semiconductor structures are arranged a substrate range covering the layouts of the semiconductor structures is equivalently defined and an actual cell can be implemented by the semiconductor process because the cell height of the invention is set to a non integer multiplication of the basic length l e g a routing track layout area of cells can be effectively reduced for example a normal prior art cell has a height of 7 routing tracks on the other hand a cell of the invention can has a reduced height of 6 5 routing tracks and a layout area reduction of approximate 7 is gained under the condition of same cell widths by applying the aforementioned design criterion of the invention various cells can be designed to have cell heights of a non integer multiplication of the routing tracks as shown in fig3 another cell cl 2 can be established according to the invention that is a layout outline ol 2 of the cell cl 2 can have a bottom edge aligning the.