or mixing in of two program segments free of interfering signals so that the memory 22 is only required to accept a relatively small amount of data the function or control units the memories and the switches which are responsible for the processing of the second program segment are illustrated on the drawing with the same reference characters as similar elements for the first program segment and are further provided with a lower case 34 a 34 the memory 19a thus stores the code word sequences of the second segment and feeds the same to the memory 22a while the time code signal memory 18a stores the associated time codes the determination of an edit location or fade in location which is free of interfering signals takes place by cyclically reading the code word sequence stored in the two data memories 19 and 19a this process is brought about by a reversal of the switch s5 to activate the address control logic circuits 25 25a which are responsible for the intermediate memories 18 18a 19 19a a clock pulse generator 27 a manually controlled unit 26 for controlling the frequency of the clock pulse generator and the forward backward cycling of the memories during cyclic reading.