send data signal is transmitted to pci control logic 6 on the other hand when the processor wants to receive data from the i o bus a receive data signal is transmitted to pci control logic 6 responsive to the signals pci logic 6 generates the earlier noted add time signal as defined by the timing diagram in fig5 the address subject to translation as provided in fig1 and 2 is received from the 601 processor at input 7 decoder 8 determines the class or type of the address distinguishing between an i o address a memory address or a configuration address if decoder 8 detects an i o address that information is conveyed to pci control logic block 6 and multiplexor block 9 responsive to such i o address detection pci control logic generates control byte enable cbe signals to indicate the type of cycle in conventional pci format to indicate the onset of i o memory or configuration cycles address translator 11 provides the contiguous to non contiguous by page translation functionally described with reference to fig1 and 2 multiplexor 9 passes the access protected and non contiguous addresses translated by block 11 when addressing i o and contiguous translated addresses from translator 12 when not addressing i o the address generated by the 601 processor either contiguous for non protected operations or non contiguous for protected i o operations serves as one input to multiplexor 13 the other input to multiplexor 13 is the data which is to be impressed on the pci bus lines pci a d when the.