positive byte justification or taken up all by additional useful information bytes negative byte justification as a rule three bytes containing justification bits and three bytes containing information bits are present the justification indication for this byte justification is also contained in the pointer area the overall frame period is 125 u03bcs this corresponds to a 155 52 mbit s bit rate the main components of the circuit in accordance with the invention as shown in fig2 are a buffer memory 6 a write address counter 7 a read address counter 8 a frame counter 12 and a control loop comprising the circuit units 8 16 18 19 and 17 as will be further explained herein below the count of the write address counter 7 and the count of the read address counter 8 are compared to each other by means of a comparator 16 whose output signal constitutes the control error of the aforementioned control loop this control loop controls the read clock signal t2 for the read address counter 8 with which the bits are read from the buffer memory 6 the nominal bit rate of the clock t2 is 129 264 mhz two requirements are attached to a change of this clock first that when possible the distance between write and read.