can be seen from fig2 a 2 b and 2 c too thus they are able to receive inputs from the latter ones in particular and according to the present invention there are four potential low exponents e 4 7 available as input the exponent of the first csa16 which is not zero has to be selected this is done using the zz signals as output from csa16 blocks as shown in fig4 further inputs are the signals ei 0 3 which are received from the input exponent and the input signal ej 3 which indicates to a csa64 block if it is the high or the low order block and finally a carry representing signal which is set to u2018 0 u2019 in the csa64 block calculating without carry fig2 b and set to u2018 1 u2019 in the csa64 block calculating with carry fig2 c for selection of the higher exponent bits the internal signal egv is needed egv is built by selecting one of the four potential eg signals again the eg signal of the first csa16 block which is not zero is selected the preselection exponents ehp 0 3 and ehm 0 3 can be built as 4 bit state of the art decrementer because their operation is not timing critical in the diction of the present invention the function thus described is realized in the implementation shown in fig4 for more detailed explanation a description by means of the corresponding boolean equations or expressions is given again co gg o gg 1 pp 0 gg 2.