shown in fig2 c 2h which is the same as fig2 g because the change is occurring in the other cross sectional view and 2m in order to form a source drain region 4 which is utilized as a buried bit line n type ions are ion implanted into a relevant portion and then an upper part of the ion implanted portion is oxidized so as to form a second insulating layer 5 this process is carried out in such a manner that a silicon oxide layer and a silicon nitride layer are deposited and a portion of the nitride layer and the oxide layer are etched in an area under which the source drain region bit line 4 is to be formed by applying a photo etching method then an ion implanting process and oxidation process are carried out then bit lines 4 are formed as a buried layer thereby improving the topology in this way a buried bit line layer 4 is formed under the second insulating layer oxide layer 5 then as shown in fig2 d 2i and 2n a gate insulating layer 6 and a polysilicon layer are deposited and a patterning is carried out by applying a photo etching method so as.