the system moves from auxiliary standby 218 back to powered from v primary 214 initialization 212 is also entered if an external reset is asserted or subsequently after all power has been temporarily removed at any time during the auxiliary standby operation 218 an input wakeup may occur for example a communications triggered wakeup 222 may cause state 224 where the microcontroller 24 a and memory 26 a are enabled as well as phase locked loop 62 and any necessary ldos 63 64 66 microcontroller 24 a executes the main program and a specific communication input routine at the completion of this the communication triggered wakeup 230 is cleared and the system returns to auxiliary standby 218 via 230 alternatively if primary power is restored vprime_ok is asserted the system returns to powered from v primary 214 via 226 and 228 an external interrupt wakeup may occur 232 causing state 234 where the microcontroller 24 a and memory 26 a are enabled along with phase lock loop 62 and ldos 63 64 66 as necessary microcontroller 24 a executes the main program and a specific external interrupt wakeup routine at the completion of this the external interrupt wakeup 232 is cleared and the system returns to auxiliary.