the counter output pulse 40 fig6 illustrates a counter unit 50a of a second embodiment of the present invention with fig7 showing the operational flow chart of this second embodiment in fig6 components which are the same as corresponding elements in the counter unit 20a are indicated by the same reference numerals the difference between the counter units 50a and 20a is that an addition counter 51 and a comparator 52 are used in the counter unit 50a instead of the subtraction counter 21 in the counter unit 20a the counter unit 51 still receives the reference pulses angular pulses and enabling signals on inputs 18 19 and 25 respectively but provides at input 53 of comparator 52 and accumulating count corresponding to the number of angular pulses counted since the receipt of the reference pulse the comparator 52 has a second input 54 on which it receives the set count from the memory 23 a third input 55 of the comparator 52 receives an enabling signal from the start stop device 26 an output signal of the comparator 52 is delivered on output line 56 which is like output line 30 of subtraction counter 21 connected to the coupling mechanism 33 via one shot circuit 31 and amplifier 32 not shown in fig6 referring to fig7 the.