data stored in the initial set up data region 3 is small the cell block of the region 3 may be constructed with less word lines than the normal cell block in this case the memory chip area can be made smaller bit lines bl of memory cell array 1 are connected to data register 6 through sense amplifier circuit 5 in ordinary cases the sense amp circuit 5 and data register 6 are integrally formed with data latch circuits as shared therebetween column decoder 7 and row decoder 4 are prepared for selecting a bit line bl and a word line wl respectively address ad and command cmd are input to address register 12 and command register 10 through i o buffer 9 respectively to be programmed data da are input into the i o buffer 9 and then transferred to data register 6 via data bus bus row address and column address are decoded by row decoder 4 and column decoder 7 respectively thereby selecting memory cells many kinds of high voltages as used for data programming and erasing are generated by a boost circuit 8 the command data taken in the command register 10 is for example decoded by controller 11 the data program and erase sequences are controlled by the controller 11 in a program mode such a sequence control is performed that a verify operation is performed for verifying.