processor system resources 70 processor system resources 70 provides system and server management software and the like and a platform for various server applications as described herein host processor system resources 70 is coupled to buffer framer 72 via bus 84 which in preferred embodiments consists of a computer bus such as what are known as a pci bus or isa bus in other embodiments other suitable computer type buses are utilized which may include proprietary local buses buffer framer 72 includes buffer 71 and preferably includes a plurality of multi protocol framing deframing engines such as for what are known as asynchronous transfer mode atm or high level data link control hdlc protocols which may be synchronous or asynchronous in other embodiments other communication protocol framers deframers are provided as may be desired by the particular office work environment buffer framer 72 in certain preferred embodiments includes for example one or more atm framers deframers 73 a and one or more and preferably a plurality of hdlc framers deframers 73 b although not expressly shown buffer framer 72 includes other controlling circuits such as a slot mapping memory multiplexers demultiplexers arbitration control and other circuitry such as for example described in u s pat no 5 533 018 to dejager et al for u201c multi protocol packet framing over an isochronous network u201d which is hereby incorporated by reference as will be described in greater detail buffer framer 72 includes the capability to transfer raw or protocol processed data which may be mapped to particular slots of tdm bus 78 and made available on different ports buffer.