of silicon process can be used relative to sti and locos processes see wolf 34 silicon processing for the vlsi era vol 3 the submicron mosfet 34 pages 330 420 in the process a gate oxide layer 32 is formed during the sti or locos process on the remaining surface of the substrate 31 as is usual next in step 54 of fig5 a as shown in fig2 a and 3a a blanket of gate conductor electrode layer g1 g2 g3 g4 was deposited over the silicon dioxide sti locos structures 33a 33b 33c and gate oxide layer 32 the gate conductor material comprises ether doped polysilicon or doped polycide doped polysilicon with a thickness from about 1500 u00e5 to about 3500 u00e5 referring again to fig2 a and 3a in step 56 a hard mask has been formed as a silicon dioxide cap layer ox1 ox2 ox3 ox4 deposited over the blanket gate conductor electrode layer g1 g2 g3 g4 the silicon dioxide cap hard mask layer ox1 ox2 ox3 ox4 is formed by a conventional cvd chemical vapor deposition teos tetra ethyl ortho silicate process which is selected from plasma enhanced cvd teos pecvd teos or low pressure cvd teos lpcvd teos process with a thickness from about 1 000 u00e5 to about 2 500 u00e5 in step 58 a gate conductor mask has been formed over the gate conductor electrode layer and the silicon dioxide cap then etching through the mask has formed the four gate electrode stacks g1 ox1 g2 ox2.