the data programming time data of a plurality of bits are transformed by a data transforming logic circuit into data multi value data according to the combination of the bits and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array a program pulse is generated according to the data latched in the latch circuit and is applied to a memory element in a selected state so that a threshold value is made to correspond to the multi value data in the data reading operation the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi value data so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi value data stored in the register as a result the following effects can be achieved the peripheral circuit scale of the memory array can be suppressed to a relatively small size in the programming operation the verify voltage value of the word line is sequentially changed by a predetermined value in a direction away from the near side of the erasing word line voltage so that the total number of the program pulses i e the program time period can be reduced compared to the multi value flash memory system in which the verify voltage is set at random thereby to realize a programming operation performed in a short time moreover after a weak erasing operation of the memory elements in the memory array is executed the memory.