the a2 sequence is stored as the d1 bit at address a1 of the temporary memory circuit as discussed at step 60 of fig4 the next data of the cpu ram i e the 34 1 34 bit at the sixth leftmost position of the a2 sequence is stored as the d2 bit at address a2 of the temporary memory and the above described operations are repeated the logic levels at the fourth and fifth leftmost positions of the a2 sequence are not compared with each other in other words this embodiment stops the comparison operation after the comparison operation is repeated n times and then restarts the operation starting with the first two bits of the next n 1 bit section of the a2 sequence when all data for example 252 bits for each channel in the first area of the cpu ram is processed the data of the second area of the cpu ram area is stored as the font information in the display ram refer to step 62 of fig4 since a method of compressing the waveforms b1 d1 to the b4 d4 waveforms of fig6 is the same as the method of compressing the waveform a1 to the waveform a4 no further discussion thereof is included herein the software controlling.