b stage structure is shown with the sampling only phases removed one additional switched capacitor circuit scn 2 i for the first stage i and scn 2 i 1 for the second stage i 1 is added at the sample phase for simultaneous residual signal amplification in this way no opamp is idle and all the pipeline stages can operate in a 2 phase clock scheme for every two phases there is one residual signal v o i 1 generated such that the overall result of all pipeline stages is a higher throughput and therefore a higher data conversion rate the operation of the embodiment is set out below fig3 is a timing diagram of 2 phase operation scn 1 i and scn 2 i are the two switched capacitor circuits for stage i scn 1 i 1 and scn 2 i 1 are the two switched capacitor circuits for stage i 1 vres i k and vres i 1 k 1 represent the same signal sample but are processed in different stages the same applies to vres i k 2 and vres i 1 k 3 vres i k 1 and vres i 1 k 2 the amplification mode means both amplification and hold operations fig4 is a graph of pipeline stage residual output voltage during transience there are two amplification hold phases amp 1 and amp 2 for each clock cycle at the same time the sampling operation is under way and thus there are two sampling operations sam 1 and sam 2 for each clock cycle the difference of residual output signal values vres i k amp 1 and vres i k amp 2 here are shown exaggerated for illustration similarly for vres i.