8 kb 7 1 kb 7 2 kb 7 7 db 7 8 the 8 bytes ck 1 to ck 8 are equal to kb 7 1 to kb 7 8 for each round n a key register holds the 8 bytes kb n 1 to kb n 8 the key register for the round n 1 is derived from the key register for the round n by a 64 bit permutation called kd perm the successive key register values are obtained by using the kd perm transformation between decipherment rounds at each round n n is valued for 1 to 7 the key byte kk 7n 7 i results from xor ing the byte kb n i with the byte valued to n 1 referring now to fig4 this shows a generalised form of block diagram of a stream cipher unit in accordance with the invention wherein a shift register 40 holds input data and a mapping logic mechanism 42 comprises a first mapping logic unit 44 coupled to the shift register 40 and a second mapping logic unit 46 connected in series with the first logic unit 44 so they perform sequential logic operations the outputs of logic units 44 46 being coupled back to the shift register 40 and the output of logic 46 providing an output signal at 48 each logic unit 44 46 is arranged to carry out the operations and transformations shown in fig2 insofar as logics 44 46 merely perform logical operations and do not contain.