at 1 2v and a low voltage at 0 8v for testing purposes four benchmark circuits were created by placing different combinations of the three largest circuits of iscas 39 89 benchmarks s35932 s38417 and s38584 within two voltage domains these combinations are shown in table 3 certain simplifications were imposed in these working examples such as choosing identical size buffers which degrade the quality of the solution but are sufficient to demonstrate both the novelty and the efficacy of the invention the register transfer language rtl level designs were synthesized using design compiler of synopsys and the placement of the circuits are performed using synopsys u00ae ic compiler u2122 the skew and the power analysis were performed using synopsys u00ae customsim u2122 xa simulator at the spice accuracy level with the spice models due to the tight slack constraints at the domain that operates at 0 8v 500 mhz was selected as the operating frequency in order to verify the variation tolerance all tests were performed at the following three different process corners in order to compare the quality of results with the standard single voltage mesh and the results of sitik amp taskin 2012 the following procedure was performed first the same circuits were synthesized with a single voltage domain mesh whose pre mesh drivers were sized using the proposed method described in the u201c pre mesh driver selection u201d subsection herein for consistency the pre mesh trees were synthesized using synopsys u00ae ic compiler u2122 software in the multi corner mode then a custom implementation of the multi voltage domain clock mesh design algorithm in sitik amp taskin 2012 was applied on the same circuits to compare to the proposed work the maximum slew slew const.