plurality of die zones 12 the ic wafer 10 comprises an integrated circuit layer 20 an insulated layer 30 and an electromagnetic shielding layer 40 the integrated circuit layer 20 comprises a plurality of solder pads 22 arranged at the top surface thereof and respectively electrically connected to an electronic device 24 embedded therein each solder pad 22 is located at the border area of each die zone 12 the insulated layer 30 is located on the top surface of the integrated circuit layer 20 defining a through hole 32 corresponding to each solder pad 22 for the implantation of a package layer 34 the package layer 34 comprises a conductive bump 36 and a seed layer 44 the conductive bump 36 is mounted in the through hole 32 of the insulated layer 30 and protrudes over the top surface of the insulated layer 30 the seed layer 44 is arranged between the conductive bump 36 and both of the sidewall of the through hole 32 and the associating solder pad 22 the arrangement of the seed layer 44 enhances the bonding force between the conductive bump 36 and the associating solder pad 22 further distribution of the seed layer 44 along the sidewall of the through hole 32 can isolate the insulated layer 30 avoiding electric current leakage or moisture influence however the package layer 34 can simply provide the conductive bump 36 for positive bonding force and electrical conduction with the associating solder pad 22 achieving the same expected effects the electromagnetic shielding layer 40 is disposed above the the electronic device 20 and spaced from each through hole 32 at a predetermined distance and electrically isolated from the solder pads 22 the electromagnetic.