illustrating an application of the circuit 100 is shown the circuit 100 is shown implemented in the context of a logic block 114 the logic block 114 may have an input 116 that may receive the signal input from a pim 118 an output 120 that may present a signal e g mc_out to an input 122 of the pim 118 an output 124 that may present a signal e g io_in to an input 125 of the pim 118 and a number of input outputs 126 a 126 n that may connect to a number of i o pins 128 a 128 n the logic block 114 may comprise a product term array 130 a product term matrix 132 a number of macrocells 134 a 134 n a number of i o cells 136 a 136 n and a power control block or circuit 137 however other configurations of logic blocks may be implemented to meet the design criteria of a particular application for example the i o cells 136 a 136 n may be implemented separately from the logic block 114 such an implementation may be found in co pending application u s ser no 09 475 879 which is hereby incorporated by reference in its entirety the circuit 106 may be implemented in one example as a portion of the product term array 130 one or more of the signals c 1 cn may be presented to inputs 138 a 138 n of the.