80 is provided in the read data path in the separate write data path in which write driver 82 is provided registers and another buffer 84 are provided in this fashion read data can be stored in the output buffer 80 while write data is written into the column select circuit 76 via the write data bus on which write driver 82 and registers 84 are coupled this allows the read data to traverse the read data path while the write data traverses the write data path at the same time as the read data circuit 60 allows the read address information to be stored and placed closer to the memory array 14 in readiness for a write enable signal than circuit 20 this ensures that the write address information is placed through the time delayed buffer 72 b as the read address traverses the read address path therefore portions of the read and write address operations can overlap one another moreover circuit 60 allows the read data to be output and stored along the read data path at the same time as write data is initiated onto the column select circuit again circuit 60 allows overlap of data read and write operations fig5 illustrates in more detail that overlap functionality and the advantages thereof fig5 is best illustrated in reference to the state diagram of fig6 state diagram 90 includes certain.