signal cs 2 writes input data into the redundancy memory cell instead of the defective memory cell or reads data and outputs the data therefrom on this occasion the control signal rs 1 of low level is transmitted to the switching circuit 12 according to embodiment 5 described above as with embodiment 1 the semiconductor device which has the configuration where the replacement of the data of the defective memory cell is performed on the output data line of the read only storage device so that the data read time in the case of replacing the defective memory cell is equal to the data read time in the case of reading data from the memory cell array is obtained by virtue of the configuration where the address storage circuit and the data storage circuit is shared between the mask rom core and the rewritable storage device with the area increase in the semiconductor device curbed the replacement of the data of the defective memory cell in the mask rom core and the rewritable storage device is permitted according to embodiment 5 the signal from the address storage circuit and the data from the data storage circuit perform replacement of the defective memory cell instead of this as with embodiment 2 the signal from the address storage circuit and the signal from the bit storage circuit may replace the data of the defective memory cell by the bit as a result the similar effect to that in embodiment 2 can be obtained according to embodiment 5 the semiconductor device with one mask rom core and one rewritable storage device was described it is possible to increase the signal cs and apply the present invention to the semiconductor device having a combination of mask.