and a predetermined negative voltage of approximately 10 v when in an active state the operation of the voltage generating circuit shown in fig1 will be described hereinafter with reference to an operation waveform diagram of fig1 prior to a time t0 negative voltage generating circuit 8 attains an inactive state and supplies a voltage of 0 v to node n1 transistor 9 receives the power supply voltage vcc at its gate and is turned on to transmit a voltage of 0 v to node n3 under such a state transistors 10 and 11 are turned off because a voltage of 0 v is provided to the inverter circuit formed of transistors 12 and 13 node n4 is charged by transistor 12 to attain a level of 5 v which is the power supply voltage vcc the voltage on node n4 is supplied to node n2 via inverter circuits 14 and 15 therefore the potential of node n2 takes the level of 5 v which is the power supply voltage vcc under this state when the input signal in is 0 v transistors 19 and 20 are turned on and off respectively whereby the output signal out attains the voltage level on node n2 i e the h level of the power supply voltage vcc of 5 v when the input signal in is 5 v transistors 19 and 20 are turned off and on respectively whereby the output signal out attains the voltage level on node n1 i e the l level of 0 v when the input signal in is 0 v transistor 16 transmits a voltage higher by the absolute value of the threshold voltage vthp however this voltage is sufficient of a level in which the latched states of transistors 17 18.