is illustrated per process step as illustrated in example fig2 a a lower structure of an image sensor in accordance with embodiments may include shallow trench isolation sti film 204 photodiodes and transistors provided on and or over predetermined locations in pixel and peripheral areas of semiconductor substrate 202 first photodiode 206 and second photodiode 208 are formed in semiconductor substrate 202 adjacent to a respective sti film 204 gate electrode 210 is formed on and or over semiconductor substrate 202 embodiments illustrated in example fig2 a to 2c illustrate a pair of photodiodes and a single gate electrode indicating a transistor to simplify the corresponding drawing and thus are not limited thereto for instance other photodiodes and transistors are omitted to simplify the corresponding example drawings bpsg layer 212 serving as a pmd pre metal dielectric layer and first capping layer 214 are sequentially formed on and or over the entire semiconductor substrate 202 including gate electrode 210 and photodiodes 206 208 first capping layer 214 can be formed of silane sih 4 bpsg layer 212 and first capping layer 214 may then be patterned to form a plurality of contact holes exposing gate electrode 210 and sti film 204 contact 216 for establishing electrical connection between the lower structure and an upper line structure.