or system management interrupt smi causing the system to awaken and respond if desired the wake signal can also be disabled by disabling the wake_en signal if link 19 is inactive a codec sensing a wake event cannot notify the system directly because no data can be transferred over an inactive link following conventional protocol the codec indicates a wake condition by raising its data_in line to controller 10 controller 10 responds by asserting a signal to the system telling it to wake up in one embodiment this is a power management event pme interrupt the system initiates whatever system wakeup functions are necessary and also directs controller 10 to activate link 19 which it does by pulsing the sync line on link 19 a sync pulse on an inactive link tells the primary codec to start the bit clock link 19 is now active and controller 10 will place sync pulses on the sync line at a 48 khz rate permitting data to flow over the link in the normal manner the codec that sensed the wake event can now send a message to controller 10 more fully defining the wake event so that the proper processing can be initiated fig3 shows a system level block diagram of the invention wakeup circuit 40 and controller 10 can be contained within an input output control hub ich 34 register 36 contains a gpi_sts_chg bit that is used by wakeup circuit 40 this register bit can be updated by controller 10 over line 46 whenever controller 10 receives a transmission over link 19 containing this status bit in one embodiment this status bit is contained in bit 0 of slot 12 of the input transmissions from the codecs the data_in.