to all source areas the lta implant must thereby take note of where the drain regions are relative to the source regions further in this embodiment it is necessary that all the drain regions of transistors across the semiconductor substrate all be aligned with and on the same side as the gate conductor 120 and all the source regions must be aligned on the other side the embodiment hereof is then better suited for memory structures which can take advantage of a consistent and regular source drain layout across the entire wafer fig5 g illustrates a processing step subsequent to fig4 g wherein an oxide 126 is deposited across the nitrided oxide 122 deposited oxide 126 is formed preferably from cvd techniques subsequent to the steps shown in fig5 g fig6 g illustrates an anisotropic removal of only the horizontal arranged regions of oxide 126 resulting from the anisotropic etch drain side oxide 128 and source oxide 130 are formed note that contrary to the previous embodiments sidewall spacers on both the source and drain sides are of equal thickness asymmetrical ldd regions can therefore be achieved not by varying the sidewall thicknesses but also by employing a combination of lta during ldd implant through or preceeded by a nitrided oxide as a diffusion barrier fig6 g illustrates a relatively long ldd at the drain side of the channel relative to the almost nonexistence ldd at the source side the source drain implant used in forming the p channel device is performed at an angle substantially perpendicular to the upper horizontal surfaces resulting in.