is connected to the gate of fet 121 the circuit generally designated as 56 has an operational amplifier chip 125 which in one embodiment of the invention was a 1458 manufactured by various companies such as motorola a similar amplifier chip 127 is contained in the peak detector portion of the circuit a wide band differential amplifier 129 is contained in the agc amplifier 48 and in one embodiment of the invention was a 1590 differential amplifier chip manufactured by various companies such as motorola the two npn transistors 131 and 132 are both of the type 2n918 in one embodiment of the invention while the final transistor 135 of the power amplifier in one embodiment of the invention was a 2n3866 since the design of the circuitry is reasonably straightforward other than the tuned circuit frequency responsive amplifier 46 further designators or explanation will not be provided of the detailed circuit diagram of fig3 as is well known to those skilled in the art data transmission lines suffer from frequency response roll off with increased length resulting in greater susceptibility to environmental electromagnetic noise this environmental electromagnetic noise lowers the system bit error rate ber performance to alleviate the problem line lengths may be restricted or a response equalizer may be inserted into the line equalizers may be used solely or in conjunction with line build out lbo networks and attenuators to minimize the number of specific networks required to equalize all line lengths required by the data system specification these techniques require significant amounts of test time for the networks and the required related data receiver circuitry to insure that any network will function properly with any receiver the alternative to extensive.