form of atm cells in the illustrated case the circuit 22 is able to transmit outgoing data signals at a frequency of 622 mhz on the line 23 and the connection 12a 39 with the aid of a series parallel converter 31 and a memory 34 among other things as shown in fig3 each of the input lines 12a of the sub block 22 are connected to a series parallel converter 31 the incoming digital signals on the lines 12a are thus subjected to a four channel series parallel conversion wherein the signals arriving on parallel lines 31a are delivered to a control logic 33 and there processed at an internal rate the requisite synchronization is effected through the medium of a synchronizing unit 38 which receives signals from control logic 33 signals converted to a parallel format are delivered to a control block or control logic 33 and from there to a memory 34 a ram memory the stored information is delivered from the ram memory or a rom memory through the control logic 33 to a buffer circuit 35 which in turn delivers the information to a single channel parallel series converter and clock pulse converter 36 when converting in the opposite direction or reverse sense signals enter a single channel series parallel converter and clock pulse converter 37 on the line 23 39 whereafter parallel format signals are sent to the control block 33 stored in the memory 34 and delivered in parallel form to the buffer circuit 35 from where they are.