u03c615 are supplied to the circuit blocks b0 b1 b2 b3 b4 and b5 respectively as clock signals to be used for transferring data in a similar manner based upon the other reference clock signal u03c620 clock signals are successively delayed by delay circuits t20 t21 t22 t23 and t24 to generate clock signals u03c621 u03c622 u03c623 u03c624 and u03c625 the clock signals u03c620 u03c621 u03c622 u03c623 u03c624 and u03c625 are supplied to the circuit blocks b0 b1 b2 b3 b4 and b5 as operation clock signals the above delay circuits t10 through t14 and t20 through t24 may be formed by inverter chains for example as shown in fig1 and a delay time t is set to be sufficiently small to be substantially negligible with respect to the clock signal cycle in alternative embodiments other delay circuits may be used an operation of the logic integrated circuit composed in this manner will be described with reference to fig2 a and 2 b fig2 a shows operations of the two circuit blocks b0 and b1 as described above the circuit block b0 starts operation at the rise time of the reference clock signal u03c620 and the operating current flows through the circuit block b0 at the same timing the operation of the circuit block b1 is started by the clock signal u03c621 with a delay of t with respect to the circuit block b0 and the operating current flows therethrough as shown in fig2 a the operation of the following circuit blocks are performed in a similar manner as a result the operating current for the entire chip of a logic integrated circuit is time wise divided by the number of divided blocks forming the circuit as shown in fig2 b as clearly shown in fig2 a.