last situation which can cause nor gate 110 to go low is when the buffer is long and the add decode line is pulsed the buffer long line l is inverted by inverter 102 and together with the add decode signal is input to nor gate 108 thus if the fifo is long l high and the add decode is pulsed a active low pulse the output of nor gate 108 goes high as a result the output of three gate nor 110 goes low and a sixth divide by twenty eight is accomplished in the cycle of one hundred ninety three when the fifo is short only four divide by twenty eight 39 s are accomplished instead of the six which occur when the buffer is long if the fifo is short s is low when the delete decode signal is pulsed the short line is inverted by inverter 104 and the inputs into nor gate 106 consist of the high output from inverter 104 and the active low of the delete decode line the high output from inverter 104 causes the output of nor gate 106 to go low thereby causing the output of nor gate 110 to go high as a result when the fifo is short the delete decode signal coming from the common circuit does not cause a divide by twenty eight i e a divide by twenty eight is deleted from the cycle similarly when the fifo not long when the add decode line is pulsed nor gate 108 has a high value received from inverter 102 which keeps the nor gate 108 output low with nor gate 108 low nor gate 110 is kept high and the divide by twenty eight is avoided i e a divide.