the low order address bits of the address then once the line fill operation has been completed the process returns to the step s 3 where the newly cached data will be read out from the cache memory 20 to the cpu 10 and the u201c unused u201d tag bit s is are cleared corresponding to the strip that is read e g 314 is cleared if 316 is read however if at the step s 4 it is determined that the page table entry corresponding to the virtual address issued by the cpu 10 is not currently present in the tlb 35 then at a step s 6 the mmu 30 accesses the page table stored in the main memory 40 and obtains the page table entry corresponding to the virtual address issued by the cpu 10 from the page table in this way the physical address corresponding to the virtual address and the cache line size specifier stored in association with the appropriate page table entry can be obtained then at a step s 7 the tlb 35 is populated with the newly obtained page table entry and at the step s 8 a cache line fill and set unused tag bits operation is performed to transfer the data values stored in the main memory 40 at the determined physical address into an appropriate cache row of the cache memory 20 with the number of portions to be filled being selected in dependence on the obtained cache line size specifier s 8 also sets the corresponding u201c unused u201d tag bits for each of the strips loaded by the line fill then once the line fill operation has been completed the.