and whether a known branch instruction is associated with the instruction address via a hit or miss in the btac 44 in the following second cache access cycle the instruction address moves to the fetch2 stage 52 and instructions are available from the instruction cache 16 and or a branch target address bta is available from the btac 44 if the instruction address hit in the respective cache 16 44 if the instruction address misses in the instruction cache 16 it proceeds to the fetch3 stage 54 to launch an l2 cache 26 access those of skill in the art will readily recognize that the fetch pipeline may comprise more or fewer register stages than the embodiment depicted in fig2 depending on e g the access timing of the instruction cache 16 and btac 44 a functional block diagram of one embodiment of a btac 44 is depicted in fig3 the btac 44 comprises a cam structure 60 and a ram structure 62 in a representative entry the cam structure 60 may include state information 64 an address tag 66 and a valid bit 68 as discussed above and in applications incorporated by reference the tag 66 in one embodiment may comprise a single branch instruction address bia in another embodiment referred to herein.