in u201c automatic insertion flow of on chip controller for at speed testing u201d by franco cesari and salvatore talluto presented at the snug europe 2007 conference and which is incorporated by reference or they may be instantiated at rtl level and recognized by script according to the technique disclosed in u201c full hierarchical flow for custom on chip controller and scan compression insertion for at speed testing u201d by franco cesari paolo giovacchini salvatore talluto and alfredo conte presented at the snug europe 2008 conference and which is incorporated by reference the icocc needs to know each state of the controlled occs and a script for example in tcl language may provide the required coupling of the signal state clk_ctrl_data_ of each occ in order to identify the pair of clock domains to be stimulated for launching and capturing the transition at speed the occ signal state is declared at rtl for example as verilog u201c wire u201d and coupled to ground before the scan chain occ insertion only after the scan insertion step can the tcl script be loaded it will allow coupling the signal state to the icocc circuitry building the appropriate bus interface to each occ by way of exemplary illustration a generic top level digital design with the requested signals is reported below as an embodiment adapted to perform the insertion of the at speed scan structure for an embodiment employing three occs for each clock domain the number occs that may be employed for each clock domain may be.