the write selector gates w 3 and w 4 are controlled by a read selector gate line wsgm 3 mw the selector gates g 5 and g 7 are controlled by a selector gate control line sg 5 35 and the selector gates g 6 and g 8 are controlled by a selector gate control line sg 6 36 word lines wlm 0 wlmn 4 m 0 4 m n are connected to the memory cells a 5 a 8 and b 5 b 8 and the source line slm 5 m is connected to the source of the bottom memory cells b 5 b 8 through source gates s 5 s 8 controlled by a source selector gate line ssgm 2 m the array configuration shown in fig1 is capable of simultaneous memory operations in fig2 is shown the voltages necessary to program memory cell b 2 in sector 830 the bold lines show the voltage paths applied from the write bit lines 11 w and 12 w when the write selectors gates w 1 and w 2 and the selector gates g 2 and g 4 are turned on by applying vdd to the write selector gate line 30 w and the selector gate line 32 the voltage from the write bit lines 11 w and 12 w are applied to the sub bit lines 62 and 64 the program conditions for the nand type array include all the word lines connected to the sector the selected word line wl 1 is applied with high voltage such as.