inputs and outputs will be ttl cmos compatible with tri state outputs the latch buffer architecture can be user configurable having described the physical embodiment of the invention in detail we now turn to a an example for purposes of describing the operation of one embodiment of the invention as shown in fig2 in operation data may be introduced onto channels chan 0 through chan 7 through the i o ports such as input 10 as shown in fig2 the multiplexer 20 for each channel selects the data to be throughput in accordance with the 3 bit control signal on line mux cnt for example if the bits appearing on mux cnt during a control cycle read 34 001 34 channel 1 would be switched onto the output of multiplexer 20 the latches 30 50 and 60 together with multiplexer 70 determine which direction the data is flowing in or out if latch 60 receives an output enable signal it is passed on the next control clock cycle to enable data to flow through buffer 80 if buffer 80 is disabled through the operation of flip flop 60 data can flow into the channel in this case channel 7 from elsewhere in the digital system such as a user input similarly multiplexer 70 is controlled by latch 50 and determines whether data will flow into the i o port 10 through latch 30 or through buffer 40 from.