columns and rows the width of each memory cell increases along a write line to compensate for write current shunting application_number US 23104102 A description mram arrays such as mtj array 2 shown in fig1 exhibit measurable amounts of write current shunting through the memory cells to adjacent lines as illustrated by the arrows in fig1 consequently the write current applied to the write conductors 4 drops with distance along a write conductor from the high potential side to the low potential side left to right as shown in fig1 due to the current shunting that takes place through the mtj cell to adjacent read or write lines the effective write field applied to an mram cell for a fixed value of i applied in a write conductor thus decreases along the length of the conductor as a result bit yield is degraded in mtj mram arrays the effect is described with reference to fig1 3 referring initially to fig1 an mram array 2 is shown formed on a substrate 3 the mram array is made up of a plurality of column and row lines with a memory cell formed at each line junction a voltage potential v is applied to a column line 4 having n memory cells representing n logic bits b i b l through b n when a write current i l is applied at the high potential side of column line 4 an effective.