10pqfp 80 62 5 5 8pqfp 100 64 5 15 16ppga 100 64 5 15 16______________________________________ fig7 depicts the use of the boundary scan sensor driver ic 39 s to implement a test fixture of any arbitrary board system or ic built without jtag bus capability test control system 85 is a jtag bus compatible controller which allows the user to communicate with the boundary scan ics 87 using the jtag bus unit under test 89 is the board system or ic which is to be tested in designing a circuit board using parts which do not have jtag capability the designer may use as many of the boundary scan sensor driver ics as needed to couple the signals to be tested to a jtag bus by serially interconnecting the parts into scan paths of the desired lengths as shown in fig7 the jtag bus may then be used to test and observe the data supplied by and used by these parts the use of the boundary scan sensor driver ic makes it possible to advantageously design a circuit board or system having advanced testability and observability while using existing non testable ics without additional hardware design fig7 depicts the use of several driver sensor ics to implement a jtag test fixture for any unit for which testability is required be it a single ic or circuit board or system the user can create the test fixture simply by coupling multiple driver sensor ic 39 s together until a sufficient number of i o pins is available connecting the boundary driver ic i os to the unit under test and coupling the jtag ports of the boundary scan sensor driver ics in parallel on a.