signals r g and b are all of 8 bits and the word length of the output data of the data expansion circuit 16 r is of 10 bits the above described effect of the edge enhancement is able to be achieved when u03b2 2 for the offset registers 162 and 182 according to the first embodiment it has a simple construction in which the data zone expansion circuit 16 r and the data zone contraction circuit 18 r are provided at stages before and after the image processing circuit 20 r respectively and the image processing can be performed even in the pixel value saturated regions with improved image quality fig7 a shows a data zone expansion circuit 16 ra employed in an image processor of a second embodiment according to the present invention the circuit 16 ra includes a 9 bit up counter the output of the data zone expansion circuit 16 ra has a parallel output obtained by providing one pulse of a clock to the clock input ck after a parallel input r 7 to ro is loaded on the counter and an added lowest bit u201c 0 u201d the output is 2 r 1 2r 2 for the input r that is u03b1 2 and u03b2 2 fig7 b shows a data zone contraction circuit 18 ra employed in the image processor of the second embodiment according to the present invention the.