and then passed to the first port of the quad port cache 30 as a sequence of n bit words a plurality of these n bit words may then be passed in parallel from the second port of the quad port cache 30 to the embedded memory array 40 as respective pages of write data during a read operation a selected page of memory may also be passed from the embedded memory array 40 to the third port of the quad port cache 30 portions of the selected page of memory may then be passed from the fourth port of the quad port cache 30 to the output block 16 as n bit words fast fall through performance may also be achieved by immediately accessing data written into the quad port cache 30 during a following read operation as illustrated by fig2 4 the quad port cache 30 and the embedded memory 40 of fig1 may be used within a multi bank buffer memory device 10 a in particular fig3 illustrates a block diagram of a preferred quad port cache bit cell 30 a used in the multi bank buffer memory device 10 a of fig2 fig4 is a detailed electrical schematic of the cache bit cell 30 a of fig3 the bit cell 30 a of fig3 comprises a multiplexer data mux having a plurality of select inputs that are individually selected in response to a plurality of control signals these control signals include a retransmit path signal retransmit path an embedded memory path signal embedded memory path and a direct path signal direct path a plurality of registers are also provided including a data input register a retransmit register and a data output register the data input register.