channel mosfets q20 q21 are rendered conductive at all times since their gates are always served with ground potential of the circuit and the gates of the n channel mosfets q22 q24 are served with the read control signal we cs collector outputs of these transistors t5 t6 are transmitted to a data output buffer dob via emitter follower transistors t7 t8 the emitters of the transistors t7 t8 are connected to n channel mosfets q18 q19 that form operation currents therefore and are served with the read control signal we u00b7 cs operation of the circuit of this embodiment will be described below with reference to a timing chart of fig3 in the reading operation a write enable signal we is set to the high level and a chip select signal cs is set to the low level therefore a read control signal we u00b7 cs becomes the high level and an inverted signal we cs thereof becomes the low level not shown accordingly if the address signals axi ayi supplied at this time assume the low level the nor gate circuit g5 is opened to produce an output signal u03c6 pa0 of the high level which renders the mosfet q13 conductive an operation current flows into the differential transistors t1 t2 and the read signal from the memory array m ary0 is amplified and.