on the size and construction of the dram memory macro being built up by the circuitry of fig1 also shown on fig1 are the idle current line node 4 cmos transistor t 12 idle current source j 4 and idle line capacitance c 4 idle current line 4 also attaches to other local bit line sense amplifier circuits implied both above and below the existing local bit line sense amplifier circuit shown on fig1 extending for the entire height of the dram macro under consideration only one such transistor t 12 current source j 4 and capacitor c 4 exist for the idle line 4 shown other local bit line pairs with their corresponding local bit line sense amps to the right or left of the one shown in fig1 each contain a similar idle current line all of which attach to current source j 4 and large capacitor c 4 at node 4 as indicated in fig1 a typical layout and construction of such a dram macro utilizing the high speed dram local bit line sense amplifier is shown schematically in fig2 each of the local bit line sense amps shown as a box in fig2 inscribed with the letters s a is connected to two local bit lines and one global bit line as shown in fig1 and is accessed by m word lines where m is given as 128 but could be 64 or 256 for.