nd 7 it is added to the output of the data latching circuit 9 by the adder 10 the added output is delayed by one clock by the data latching circuit d 11 in accordance with the field identification signal fld for distinguishing two fields in one frame the addition output of the adder 10 or the delay output of the data latching circuit 11 is alternately selected for each field to output it the output means of the fld is not shown as shown in the same drawing the data latching circuits 7 9 and 11 provided as long as all are latched by the clock of 8 fsc from the terminal 16 one sample is delayed by one clock then the output of the mux 12 is inputted into the data latching circuit d 13 and is delayed by one clock by the clock of the 4 fsc the clock of the 4 fsc makes the clock of 8 fsc from the terminal 16 through the frequency division by the counter 17 the output of the data latching circuit 13 together with the clock of 4 fsc of the terminal 15 as the intermediate digital picture signal of the sampling frequency of the approximately 4 fsc is outputted.