of the registers in a power managed computer system referring to fig1 an illustrative embodiment of a computer system utilizing the present invention is shown the computer system 100 comprises one or more processors 105 1 105 n u201c n u201d being a positive whole number and a main memory element 130 e g dynamic random access memory u201c dram u201d static random access memory u201c sram u201d etc coupled together by a host bus 110 and a host to peripheral bridge 120 in general the host to peripheral bridge 120 operates as an interface between a host bus 110 and a peripheral bus 135 the main memory 130 also includes a non volatile memory or a separately powered memory e g dram sram for saving contents of registers or other memories when power is removed alternatively the register contents may be written to mass storage such as hard disk before power suspension so that they can be retrieved after power up processors 105 1 105 n are any microprocessors in one embodiment processors 105 1 105 n are the pentium u00ae processors or pentium u00ae pro microprocessors manufactured by intel corporation at santa clara calif host to peripheral bridge 120 typically includes a.