1 illustrated in fig1 hence as illustrated in fig4 in the memory device 101 illustrated in fig3 the above time t 3 that is necessary to charge the input of the inverters 109 a 109 a from 0 5 usupply to 0 25 usupply or 0 75 usupply may e g only be approximately 0 75 rc while in the memory device 1 illustrated in fig1 as mentioned above the u201c evaluation time u201d t 2 e g may be approximately 1 4 rc in the memory device 101 illustrated in fig3 correspondingly similar as is the case in the memory device 1 illustrated in fig1 the above inverters 109 a 109 b lead to a respective additional delay u03c4 gate delay u201c gate delay time u201d of the output signal i e a voltage u do output at the output line 117 of the memory device 101 see fig4 however as the time t 3 that is necessary to charge the input of the inverters 109 a 109 a from 0 5 usupply to 0 25 usupply or 0 75 usupply as explained above in the memory device illustrated in fig3 is considerably smaller than the u201c evaluation time u201d t 2 in the memory device 1 illustrated in fig1 and as also from a respective comparison of the fig2 and 4 the reading out of a memory cell in the memory device 101 is considerably faster than in the memory device 1 and e g might only take the amount of time t 1 t 3 u03c4 gate delay or less versus t 1 t 2 u03c4 gate delay as is the case in the memory device 1 fig5 illustrates a.