steps and is maintained as subsequent unplanarized layers are deposited or formed thereon the oxide layer 14 is deposited over and generally covers layers 18 20 and 22 the oxide layer 24 that fills the steps 28a u02dc 28n also creates a new set of steps 30a u02dc 30n at the upper surface of the oxide 14 the step height of the alignment mark s are generally maintained in layers 18 20 and 22 and oxide layer 14 a problem may arise from conductive layer 16 first many conductive materials are opaque to the wavelengths of light conventionally used in semiconductor and or integrated circuit alignment thus rendering use of alignment marks in underlying layers difficult if not impossible consequently alignment marks tend to be effectively erased by a planarized opaque layer of material second planarization of the uppermost or outermost layer eliminates any steps therein the alignment marks thus tend to be erased by techniques used in modern semiconductor and or integrated circuit manufacturing processes the first and second conductive layers in region 40 may also comprise an electrically conductive material or materials as described above preferably however the first conductive layer and the functional layer in region 40 independently comprise a material providing a conventional circuit element interconnect function such as titanium aluminum copper a heavily doped polysilicon and or a metal silicide more preferably titanium the functional layer in region 40 may alternatively or additionally provide a conventional atom migration barrier function such as titanium nitride etch stop or etch inhibition function such as silicon nitride resistance lowering function such as titanium tungsten alloy conductive material adhesion function such as titanium.