of data memory 111 and an interrupt stack memory is implemented by atb 118 and the interrupt stack data section of data memory 111 this type of cache memory implementation is well known in the art and an example of such a memory is detailed in u s pat no 4 197 580 of s j chang and w n toy the cache memory is active during all normal memory read operations while the virtual to real address translation is taking place the word address bits are used to access the tag memory 112 and the data memory 111 only a small number of words contained in main memory 104 are also duplicated in data memory 111 tag memory 112 defines which words of main memory 104 are duplicated in data memory 111 cache control 110 performs the function of moving data words from main memory 104 into data memory 111 and properly updating tag memory 112 this operation of updating the tag memory 112 and the data memory 111 is defined in the above noted chang et al patent for each cache data word location in data memory 111 there is a corresponding data location in tag memory 112 which is also addressed by the same word address bits each data location in tag memory 112 contains the real address where the corresponding data word in data memory 111 can be found in main memory 104 when processor 101 transmits the virtual address via address bus 105 and read request via bus 107 atb 102 starts the translation from the virtual address to the.