between its drain and source which is adjusted via application of the bias signal vhpbias to its gate the rc time constant of the signal vtrig at node n 2 is dominated by the total capacitance at node n 2 and the resistance between the drain and source of transistor q 3 via careful selection of the capacitance of the capacitor c and of the biasing voltage vhpbias the width of the pulse of the signal vtrig can thus be adjusted the processed signal vtrig is fed to the input of the inverter 204 and then output represented as the signal pix_out in fig5 in addition the u201c dead u201d time of the spad 202 can be adjusted via selection of the quench signal vquench which adjusts the resistance between the drain and source of transistor q 1 and therefore the discharge rate of the anode of the spad 202 this pulse shaper 206 provides for a properly shaped output signal of a desired length and does so with low area overhead and low power consumption through the use of a sole and only transistor q 3 plus capacitor c as opposed to the prior art design of fig1 the logic components of which utilize multiple transistors the capacitor can be implemented as a mim or mom structure over existing.