the peripheral transistor 12 by ion injection using the control gate and the gate electrode as a mask and further a step of forming an interlayer insulating film not shown which covers the overall areas of the memory cell transistor 11 and the peripheral transistor 12 are carried out to thereby accomplish the eeprom as described above in accordance with this first embodiment phosphorous is introduced into the polycrystalline silicon film 5 at a relatively low concentration by way of the ion injection method and the ono film 6 is left at least on the polycrystalline silicon film 5 of the memory cell region therefore when phosphorous is introduced at a relatively high concentration into the polycrystalline silicon film 7 by way of the vapor phase diffusion method the silicon nitride film of the ono film 6 functions as a diffusion stopper of phosphorous as a consequence the impurity concentration of the polycrystalline silicon film 5 of the memory cell region can be maintained at a relatively low level and further the impurity concentration of the polycrystalline silicon film 5 of the peripheral circuit region can be set to the relatively high level in this embodiment the polycrystalline silicon films 5 7 forming the gate electrode of the peripheral transistor.