when contact hole etching is performed is deposited on the entire surface to have a film thickness of e g about 80 u00e5 by lp cvd furthermore a dielectric interlayer 28 made of bpsg is deposited and planarized by cmp contact holes are then formed by photolithography and rie in the peripheral circuit region a contact 25 is formed by burying a metal material such as titanium titanium nitride tungsten in the memory cell array region a memory cell bit line contact 24 is formed after that aluminum or the like is deposited on the entire surface and photolithography and rie are used to form a wiring layer 26 such as a bit line in the memory cell array region and a peripheral circuit wiring layer 27 in the peripheral circuit region a dram is completed by forming a stacked capacitor 34 including a plate electrode 35 capacitor dielectric film 36 and storage node electrode 37 in this embodiment as in the first second and third embodiments described above the gate electrode sidewall film thickness is small in the memory cell array region and large in the peripheral circuit region this improves the data holding characteristic in the memory cell array region and at the same time increases the operating speed in the peripheral circuit region by forming the source drain structure as a shallow junction also as in the first and second embodiments a self alignment contact formation process can be applied when the gate electrodes are formed this achieves high applicability to a device having a high integration degree such as a general purpose dram memory cell in this.