interrupts to the cpu 328 however large buffers result in longer latencies between processing of incoming atm cells the architecture illustrated in fig3 allows the connection of other communication devices such as an analog modem 332 to the pci bus interface 312 using a typical v 90 pci interface 336 to transport atm cells across the system bus the v 90 interface 336 transports input to the pci bus 316 through pci bus interface 312 once the atm cells are stored in buffer 324 cpu 328 processes the atm cells to reassemble the data cells during reception and segments the data prior to transmission by using a cpu 328 which is typically a general purpose microprocessor such as a pentium ii microprocessor from intel corporation of santa clara calif significant hardware savings may be had over hardware implementations of a sar chip 0024 fig3 b illustrates a simplified diagram of the flow of information within the computer system in fig3 b a utopia bus interface 348 receives atm cells from a network not shown the atm cells are transferred along an ingress direction 350 to a cell first in first out memory fifo 354 which buffers the data when the cpu is ready to reassemble the atm data the content of fifo 354 is.