106 an and gate 124 and a system 108 for the chip 100 to function the pll 110 can apply one of several frequency clocking signals to the system 108 the pll 110 receives a reference clock signal ref_clk through the communication channel 120 and generates a plurality of output clocking signals freq 0 to freq n the pll 110 transmits the clocking signals to the mux 106 through the communication channels 122 and 126 however for each clocking frequency generated by the pll 110 there is a designated communication channel for each frequency but only two communication channels are depicted for the purposes of illustration then one of the frequencies output from the pll 110 is selected by virtue of the frequency select freq_sells signal into the mux 106 through the communication channel 118 the mux can then output a clocking signal clk to the system 108 through the communication channel 128 the clk however can be gated off due to the outputs from the chip io 102 and the pervasive logic 104 of the system 108 the chip io 102 outputs a power save mode acknowledge psm_ack to the and gate 124 through the communication channel 112 the psm_ack signal is typically related through the chip io 102 from an external device additionally the pervasive logic 104 outputs a clock enable signal clk_en signal.