for read data to appear in the local interface after the start of a read request the write latency is a time necessary for write data to appear in the local interface after the start of a write request ir iw indicates the read write operation internal read write operation in the mram in the dram shown in fig4 a row address r has for example 17 bits r lt 16 0 gt the row address r lt 16 0 gt is input together with the active command and set in the dram in the mram case a shown in fig4 the row address r has for example 18 bits r lt 17 0 gt the mram has a large page size as compared to for example the dram for this reason the row address is divided for example divided into upper bits r lt 17 14 gt and lower bits r lt 13 0 gt and input twice a precharge operation is designated by the rising edge of the clock when the precharge command is input and a preactive operation is designated by the falling edge that is the precharge command can set the precharge operation and the preactive operation in the preactive operation the upper row address r lt 17 14 gt is input and set in the mram in addition an active operation is designated by the rising edge and falling edge of the clock when the active command is input in the active operation the lower row address r lt 13 0 gt is input.