within the staircase from the top providing full coverage for the various failure analysis techniques for example because the signal traces are visible from the top various laser excitement failure analysis techniques may be used to isolate problems on any portion of a signal path on any layer in debugging other integrated circuits that are not specifically designed for testability many portions of a signal path may be obscured by overlapping traces fig6 illustrates an embodiment 600 of a shift register wherein the unit delay cells 602 are configured to easily perform a high speed test the data in 604 travels through a flip flop 608 to a string of unit delay cells 602 to a second flip flop 610 the signal travels out of the second flip flop 610 through a second string of unit delay cells 602 to a third flip flop 612 the signal travels out of the third flip flop 612 through a third string of unit delay cells 602 to a fourth flip flop 614 all of the flip flops share a common clock line with each clock cycle data must simultaneously propagate through the rows of the unit delay cells 602 if a problem exists within one of the many unit delay cells the data will not propagate properly and will become corrupted such problems will become more apparent when the clock speeds are high the present embodiment is directed at high speed testing of the integrated circuit whereas the.