memory unit 7 to load a data register in the data unit the address held in register p in the address unit 9 is incremented by one due to the balancing of the delays of memory read and data unit operations these two operations complete at the same time and the results are available in registers for use on the next instruction when the data from a read request operation is used to load a register in the address unit 9 then the memory read latency cannot be hidden from the programmer in the way that it is for data unit operations as the latency cannot be hidden its effect is minimized by ensuring that the content of an address register targeted by a load address instruction is changed after a fixed number of instructions have been issued following the load address instruction the load address fixed latency fifo 15 is included in the return path from the memory unit 7 to the address unit 9 and its operation ensures that a fixed number of instructions is issued in between a load address instruction and the changing of the target register contents this allows the programmer to predict exactly when in a sequence of instructions a load address operation will take effect and to code appropriately fig3 shows the internal arrangement of the memory unit 7 the dma unit 2 may issue a single read or write request in.