circuit is insensitive to the stray capacitances and offsets of the comparator and the operational amplifier in particular the input signal is sampled during only one phase of the clock which pilots the operation of the switched capacitance network application_number US 59644490 A description with reference to fig5 in the circuit according to the invention the circuit for determining the polarity of the input signal comprises a comparator circuit 10 identical to that described above connected to a flip flop circuit 12 which is preferably of the d type the clock input of the flip flop is piloted by the signal u03c6 2 which is complementary to the phase signal u03c6 2 the outputs of the flip flop 12 are indicated q and q the circuit of fig5 includes two multiplexers ma and mb each having two inputs for receiving the clock signals u03c6 1 and u03c6 2 respectively and an output with reference to ma two controlled switches s a and s b are provided between its u03c6 1 and u03c6 2 inputs and its output and are piloted by the outputs q and q of the flip flop 12 similarly two controlled switches s c and s d are provided between the u03c6 1 and u03c6 2 inputs and the output of mb and are piloted by q and q respectively if u03c6 1 and u03c6 2 have the waveforms shown in fig6 two signals indicated u03c6 a and u03c6 b whose waveform depends on the polarity of the input signal v.