read addresses are concerned the processings of steps s218 and s219 are identical therefore the reset signal rst and the enable signal en are used for the signal to the enable terminals e of the counters count2 count10 and count11 in common fig3 shows the state of the storage units 0 to n obtained immediately after reset is performed 34 0 34 is stored in all the storage units 0 to n at step s204 it is decided whether the operation mode is a first mode or a second mode in response to respective cases the routine branches into step s205 or step s210 through the connector j5 the first mode is equivalent to a case where the mode signal mode is 34 0 34 at step s205 the input data din is employed as the write data to the ram write operation is performed synchronously with the rise of the clock clk at step s206 it is decided whether the write address is n 1 or not this processing is executed by the comparator cmp2 for inputting the mode control value w mode cnt and 203 204 1 as long as the write address is not n 1 both the write address and the read address are increased by 1 at step s208 this processing is executed by the counters count10 and count11 while the processing of step s208 is also executed in response to the rise of the clock clk it is performed after step s205 fig3 shows processings for the storage units 0 to n to be executed when the clock clk first rises after the reset processing is performed since the write address has been set to 34 0 34 at step s219 a value.