of the present invention and which addresses the problems associated with some cells i e j cells in the previously described embodiment as explained above in describing the embodiment of fig8 non selected bit lines are charged to 0 v which for higher vpass voltages e g 10 v still causes higher gate disturb in this embodiment of the present invention non selected bit lines are all charged to 2 v and the selected bit lines are charged to 0 volts also the higher and lower vpass voltages are applied opposite to what is depicted in fig8 i e 10 and 7 volts versus 7 and 10 volts respectively as shown by cells q r and s vertical fields can be reduced throughout the array such that gate disturb can be suppressed throughout array 100 fig1 shows a biasing method for a nand array 1100 comprising phines type memory cells in the program operation according to still another embodiment of the present invention as explained with respect to fig9 non selected bit lines are charged to 0 v unfortunately while most memory cells in the array of fig9 experience lower gate disturb some of the cells i e cells m are still subject to larger vertical fields resulting in higher gate disturb the embodiment depicted in fig1 addresses this situation in this embodiment non selected bit lines are charged to 3 v not 0 v and the selected bit lines are charged in the program operation to 5 v 3 5 v and 0 v in this way as depicted by cells t u v w and x the vertical field in all cells is effectively minimized whereby undesirable gate disturb is also minimized as will be appreciated by those skilled in the art.