discharged by the thin gox nmos transistors mn 51 and mn 52 is increased and the efficiency of protecting against esd is improved here the gates of the nmos transistors mn 51 and mn 52 are connected to the ground vss and turned off during a normal operation as described above the circuit of fig5 can be applied to the case where a voltage applied through the input pad 300 is lower than breakdown voltages of the thin gox transistors mn 51 and mn 52 and preferably to part for example 310 d and 310 e of the esd protection units 310 a through 310 e of fig3 0041 fig6 is a circuit diagram of the esd protection unit shown in fig3 according to another illustrative embodiment of the present invention a second protection unit d 32 is implemented by thin gox transistors mn 61 and mn 62 connected in series between an input pad 300 and ground potential vss that is a drain of the nmos transistor mn 61 is connected to the input pad 300 and a gate of the nmos transistor mn 61 is connected to a power supply voltage vcc also a drain of the nmos transistor mn 62 is connected to a source of.