stage switches the central processor 150 transmits control words to the time slot memories via a peripheral bus 155 when updating is required each control word so transmitted is accompanied by a write address defining the particular time slot memory to store the control word and the address within the memory where it is to be stored a peripheral bus interface circuit 156 receives each control word and its associated address from central processor 150 and decodes that portion of the address defining which time slot memory the control word is to be stored in in response to this address portion the peripheral interface circuit 156 decoder generates an enable signal which is transmitted from time t 8 to t 0 to the specific memory to be accessed each time slot memory includes an and gate 324 fig2 and 3 the output of which and gate is connected to the write enable lead 34 w 34 of that memory the enable signal generated by peripheral interface circuit 156 is applied to one input of the and gate 324 of the selected time slot memory enabling that and gate to complete a path for a logical 34 1 34 write control signal from timing distribution unit 132 the time slot memories thus are not written into during each time slot but are written only when the peripheral bus interface circuit 156 detects a control word to be written from central.