the gates of pmos transistors 201 and 202 pmos transistor 203 and nmos transistor 206 form a current control circuit which is coupled in parallel with the current paths of the differential comparator circuit and ensures that a substantially constant current is drawn from current source 210 during all operating phases of comparator 200 the sources of pmos transistors 201 203 are commonly connected to node n 1 such that these transistors receive the source current i s provided by current source 210 the drains of pmos transistors 201 203 are coupled to the drains of nmos transistors 204 206 respectively the sources of nmos transistors 204 206 are commonly coupled to the ground supply 251 the drain of nmos transistor 204 is also coupled to the gates of nmos transistors 204 and 205 similarly the drain of nmos transistor 206 is connected to the gate of nmos transistor 206 the gate of pmos transistor 201 is coupled to switches s 1 and s 3 switch s 1 is further coupled to receive a reference voltage v ref and switch s 3 is further coupled to receive a ramp voltage v ramp the gates of pmos transistors 202 203 are commonly coupled to a first terminal of sample capacitor 215 the second terminal of sample capacitor 215 is coupled to the ground supply 251 the drains of pmos transistor 202 and nmos transistor 205 are commonly coupled to the first terminal of output capacitor 220 i e the comparator output terminal the second terminal of output capacitor 220.