stage 560 is provided at the exit of each request fifo 580 every request leaving fifo 580 is checked against the first entry in the corresponding back end barrier insert fifo 550 when there is a match the sideband data is appended to the request before being sent on to the memory arbiter when a barrier either as sideband data or as a separate barrier request is included in a request queue the gwam for that thread is flushed all entries in the gwam can be erased as there is no longer any incoherency hazard associated with those memory address entries in summary to support the order enforcement the incoherency detection module performs the following steps when an incoming read address falls within one of the gwam address range slots 1 issue barrier request for the threads that need one 2 assign appropriate block check sideband data to the read request 3 toggle the internal 1 bit time stamp which is attached to every read write 4 flush the gwam of the threads that have barrier requests issued fig6 illustrates the functional hardware blocks of an order enforcement memory arbiter in accordance with this embodiment the memory arbiter maintains a barrier status register 600 and current time stamp register 605 the barrier status register 600 indicates whether and from which threads barriers have been issued through the thread arbiter 610 the barrier status register is cleared every time the internal time stamp.