241 and 242 are contact connections between the wirings 231 232 and the impurity regions fig6 d shows the second level of porycrystalline silicon introduced by the present invention in this example for reducing a resistance the polycrystalline silicon 211 is formed in a mesh like manner along the peripheral edge of the respective memory cells through the contacts 215a and 215b the polycrystalline silicon 211 is connected to the n type region 214 while through the contacts 250a and 250b the polycrystalline silicon 211 is lso directly connected to the p contact region in the d well region 220 as shown throughout fig6 a to 6d especially in fig6 d in the layout according to the embodiment of the present invention each of the memory cells is formed on a relatively small region having a length of 37 u03bcm and a width of 32 5 u03bcm in this layout the wirings 251 and 252 for connecting the transistors q 3 to q 6 are formed of the same level of polycrystalline silicon as those for the word lines 207 and 208 as described above according to the present invention a reduction in size of about 22 can be achieved in the memory cell matrix without losing the latch up phenomena suppression function although the above embodiment is described regarding the situation where the v ss power wiring formed of the polycrystalline silicon with the n type impurity the n type substrate and the p type well regions is employed the matter can be similarly effected by.