in the following step the interconnect holes are then filled with polysilicon 59 fig7 d the polysilicon on both sides is then etched back and stopped on the lto fig7 e after removing the lto the 2 u03bcm doped polysilicon is exposed again and ready to be etched for the front and back side oxide opening 61 fig7 f another layer 62 of 0 5 u03bcm polysilicon is deposited and doped with boron or phosphorous fig7 g the front and back side polysilicon pads are patterned followed by the oxide etch on the back side for ground opening 63 and heavily doped for ohmic contact after this step the array of devices can be built on top of the front side polysilicon the process flow for fabricating a wafer with through wafer interconnects of the type shown in fig3 is shown in fig8 we start with a 400 u03bcm thick double sided polished si wafer 71 which is thermally oxidized to 2 u03bcm thick 72 to serve as a hard mask for the deep etch both sides are then patterned with 20 u03bcm diameter openings 73 for each interconnect fig8 a the through wafer deep etch is done by etching half way from both sides of the wafer fig8 b by this means a 20 to 1 high aspect ratio via hole can be achieved the wafer is then heavily doped with boron or phosphorous 74 depending on the wafer type to build the pn junction diode inside the holes fig8 c the interconnect holes are then filled with polysilicon 76 fig8 d the polysilicon on both sides is then etched back and stopped on the oxide fig8 e it is ready to be etched for the front and back side oxide opening.