resistor 18 thereby increasing the speed of the transition however during circuit testing the out node is shorted to ground causing the extra current through the upper output transistor 14 to flow for extended periods of time resistor 18 is intended to limit the short circuited output current to prevent damage to upper output transistor 14 however increasing the value of resistor 18 decreases the current available to upper output transistor 14 slowing the low to high output transition fig2 illustrates the ttl gate 22 of the present invention ttl gate 22 comprises an input transistor 12 upper and lower output transistors 14 and 16 resistors 13 and 15 and current limiting resistor 18 connected substantially as described in connection with fig1 the input capacitance of the subsequent gate not shown is represented by capacitor 20 which must be charged and discharged for the gate output to make a low to high and high to low transition respectively ttl gate 22 further comprises a diode 24 with its anode coupled to ground and its cathode coupled to node 26 a second diode 28 with its anode coupled to resistor 18 and its cathode coupled to node 26 an npn transistor 30 with its base coupled to node 26 and its emitter coupled to the collector of upper output transistor 14 and a resistor 32 coupled between voltage source v cc and.