hv n well to reduce the mask count the n regions and p regions of the ldmos transistor are implanted step 1216 in one implementation during this step n and p regions associated with the cmos transistors are also implanted as shown in fig1 h a p region 1416 and an n region 1418 are implanted at the source of the ldmos transistor an n region 1420 is also implanted at the drain of the ldmos transistor further p regions 112 114 are implanted at the source and drain respectively of the conventional pmos transistor and n regions 128 130 are implanted at the source and drain regions respectively of the conventional nmos transistor as in process 600 formation of the p regions and the n regions can occur through a 3 step process as described above in connection with a sub micron cmos process the three way performance tradeoff between the on resistance r dson the drain to substrate breakdown voltage bv d u2014 s and the source to substrate punch through breakdown voltage bv s u2014 sub of an ldmos transistor can be improved by using a triple diffusion n n ld hv n well drain structure that can be fabricated through a process compatible with a typical sub micron cmos process ldmos transistors can be fabricated on a common hv n well a main design requirement of the common hv n well is to provide an optimized vertical doping profile to achieve the highest drain to substrate breakdown voltage bv d u2014 sub.