stack control signal bcl has the low level 34 l 34 as shown in fig2 the nmos transistor 189 is turned off off the output signal from the inverter 190 has the high level 34 h 34 and the pmos transistor 186 is in the off state off as a result a node 191 shown in fig2 is in a high impedance state in the present embodiment the row address signal is formed of two bits a2 and a3 so that the row address signal can identify a row address among four addresses each of the memory cell blocks 48 and 49 is provided with four row addresses corresponding to the row address signal as a result the block bit lines rbl 11 rbl 14 and rbl 21 rbl 24 of the memory cell blocks 48 and 49 are not usually in the floating state in the reading operation thus the memory cell blocks 48 and 49 are provided with no block bus driver stack circuit the main sense amplifier 64 shown in fig1 has buffer circuits 192 195 which are controlled by the column selecting signal a1 and a1 so as to be either active or inactive each of the buffer circuits 192 195 is formed in the same manner as each of those forming the block sense amplifiers 59 61 shown in fig1 in this case the column selecting signal substituted for the block selecting signal is supplied as a control signal to the buffer circuit the main bus driver stack circuit 65 shown in fig1 has inverters 196 199 and buffer circuits 200 203 which are controlled by the main bus driver stack circuit control signal mcl so.