invention with the conventional interconnect scheme of fig1 3 are illustrated in the drawings that is fig3 and 4 show details of a copper bump on the die of the conventional interconnect scheme of fig1 and 2 and the thin film ild region under the bump during heating and cooling the bare die the cte mismatch between the materials in the die cause stresses and strains in the thin film ild layers in the die as shown in fig5 in fig5 the ild layer represents a stress contour plot showing that the region 12 of highest stresses is at the edge of the copper bump when the die is subjected to a thermal transient the area under consideration is represented by the line b b 1 on the ild layer in fig4 0019 fig6 compares the modeled stresses in the ild layer along the line b b 1 marked in fig4 for different die bump materials when they are subjected to the same u03b4t since the bump materials are electroplated at room temperature room temperature is the stress free state for the die heating and cooling induces cte mismatch stresses on the die thin film layers due to the bump as shown in fig6 the peeling stress at the edge of the bump is markedly lower with the lead tin and silver tin solder materials used in accordance with the present invention as compared with the copper die bump of the conventional interconnect scheme since ild delamination is the key failure mode only the normal component of stress peeling.