connection between the blocks started out longer than the d path delays then the skew improves performance in a hierarchical design blocks can be built and timing analyzed first and then the parent level clock distribution adjusted to delay clocks going to the receiving blocks of the longest paths the amount of useful delay added between each block pair is half of the difference between the longest path traveling towards the delayed clock block and the longest path traveling away from the delayed clock towards the other block in the pair thus after the clock delay is added the data paths will then have equal minimum cycle time maximum chip clock frequency as noted above another design technique is to bound delay calculations by minimum and maximum values rather than hopelessly seeking to find a single u201c exact u201d value an example of this approach is to map cross coupling capacitance into bounded u201c effective u201d capacitance fig5 shows the possibilities of aggressors switching in either the opposite or same direction as the victim signal under analysis while it is possible for a fast opposite direction aggressor to have an effective capacitance of 3 or more times the actual nominal cross coupling it is a reasonable approximation to just set the effective cross coupling capacitance to 2 times the nominal capacitance which is still much more conservative than just neglecting the capacitance multiplying effect of the switching likewise while it is possible for a fast same.