input terminal 15 is changed as indicated by a curve 15a in fig2 in accordance with a time constant u03c4 11 u2243 r 11 c 12 because r 12 gt r 12 if time t in fig2 is sufficiently close to 0 the power supply voltage v cc is applied to the fet 18 at the same time a 34 low 34 logic level signal having a voltage sufficiently close to 0 v is input to the reset input terminal 15 therefore the internal state of the ic 11 is reliably reset immediately after the switch s is closed to apply the power supply voltage after the reset operation is completed the reset is canceled with this operation initialization of the main circuit 10 of the ic 11 is completed in other words initialization of the main circuit 10 or the ic 11 is completed only after the reset input terminal 15 undergoes a state change from 34 low 34 level to 34 high 34 level reset to reset cancellation when the switch s is closed i e a new battery is mounted the reset circuit 12 is required to cause the above mentioned state change in contrast to this when the switch s is opened t t b a voltage applied to the power supply voltage input terminal 14 is.