times smaller than the gate width of the p channel mos transistor the surface of an npn transistor of the type illustrated in fig1 for example ranges between 2 and 25 u03bc 2 for example being on the order of 4 u03bcm 2 tests have shown that in the case where a laser attack is performed with a beam having a diameter of approximately 5 u03bcm a detection device using such npn transistors having an n type buried layer enables to detect this attack over a radius for example ranging between 300 and 500 u03bcm around the impact point of the beam on the rear surface of the chip for example over a radius on the order of 400 u03bcm around the impact point of the beam an integrated circuit chip used for the processing or the storage of critical data for example has a surface area ranging between 2 and 3 mm 2 to be able to detect a laser attack whatever its impact point on the chip the present inventors provide integrating several npn transistors having an n type buried layer of the above described type in the chip an array of 20 npn transistors having n type buried layers distributed in rows and in columns and spaced apart by a distance between 150 and 250 u03bcm for example on the order of 200 u03bcm is for example formed an advantage of a laser attack detection device of the type described in relation with fig1 2 a and 2 b is that it can be formed by only using components commonly provided in integrated circuit.