and 57 fig3 g step 8 u2014 select and test die 8 10 22 28 36 46 50 and 64 fig3 h the above described parallel testing of die on wafer can reduce wafer test time as compared to individual sequential testing of die on wafer the present invention is also applicable to iddq testing of each die on the wafer iddq testing is the monitoring of current to an ic die during the application of test patterns a higher than expected current at a particular test pattern may indicate a defect the wv and wg bussing arrangement of fig1 a is adequate when performing iddq testing in the one die at a time arrangement of fig2 26 because any unexpected current on wv and or wg can be attributed to the one die that is in functional mode as to the parallel die testing arrangement of fig3 31 row specific v and g bussing of the type shown in fig2 permits unexpected v and g current to be attributed to the correct die of the diagonal grouping being tested if this capability is not desired in the test arrangement of fig3 31 then the wv and wg bussing of the type shown in fig1 a can be used in fig3 31 for example an additional probe access area could be provided for power supply bussing in which case palrn and parrn need not provide power.