the n channel transistors 104 and 110 have a w l ratio of 5 1 to better drive the latch and improve the symmetric aspect of the duty cycle in operation the differential amplifier 32 will have a voltage differential on the output nodes 102 and 108 that is a function of the voltage differential on the inputs to the gates of transistors 80 and 82 when the latch signal is not present the switches 112 and 116 will conduct connecting node 102 to the latch node 114 and output node 108 to the latch node 118 whenever the respective voltages on the output nodes 102 and 108 rises above or below the switching threshold of the input transistors not shown of the inverters 120 and 128 the outputs thereof will change state to either a logic 34 1 34 or a logic 34 0 34 these inverters 120 and 128 typically utilize a two transistor cmos configuration whenever it is desirable to sample the comparator output the latch signal is raised high turning off switches 112 and 116 and turning on switches 124 and 130 this will effective 34 latch 34 the logic state therein it is noted that this operation does not effect the differential amplifiers 32 of fig3 in summary there has been provided a random noise.