is set when first color data is input and holds the set data until it is reset by next signal fe in this manner color data to be used in display of one frame are latched in register 12 since data color 14 13 02 and 00 are used in display of one frame data csr 14 13 02 and 00 are set shift register 13 loads data csr15 0 in accordance with signal fe and outputs loaded data csr15 00 from the msb in a bit serial manner as data sft in accordance with signal clock as shown in fig5 c at this time csr14 13 02 and 00 are set at logic 1 register 13 repeatedly performs similar processing until next data csr15 00 is loaded in accordance with signal fe data sft is output to controller 18 and converter 15 and at the same time fed back to itself as a serial input controller 18 detects colors and the number of colors to be used in display of one frame in accordance with signal sft in accordance with the detected number of colors controller 18 outputs a rotation instruction representing the number of bits of rotation to converter 15 in addition in accordance with signals clock and fe controller 18 generates and outputs.