a clocked regenerative buffer 232 or 234 that can latch the output of that pgmux topologically the mux latch circuit 230 can be considered an extension of a cmos latch using a clocked passgate d 1 or d 2 for input isolation and a clocked regenerative buffer 232 or 234 for latching this means that the new latching mux circuit 230 has a latency close to that of a single cmos latch thus bringing the overall latency of circuit 200 to that of a two stage circuit u2014 a master slave latch this is to be compared to the topology of the original cml circuit shown in fig1 that has three distinct cml stages a master latch a mux and a slave latch so the cmos implementation advantageously eliminates one stage out of three from the direct signal path which is a part of the latency critical analog feedback loop such latency reduction in the cmos version is achieved by placing some logic functions associated with the pgmux operation select gating circuitry d 1 or d 2 onto the digital feedback path 211 select path in one embodiment the associated circuits are single stage dual rail domino buffers p and n type d 1 d 2 that pass the select.