a time interval between the rising edge of the clock signal clk and the rising edge of the word line word and td is a time interval between the development of the potential difference between the pair of bit lines and the determination of the output data dout by sufficient amplification of the pair of read output lines sa 0 and sa 1 by the sense amplifier 30 from the comparison with the read time period t0 equation i of the conventional sram it is apparent that tb1 tb2 gt td the speeding up of the read operation is achieved by eliminating the wait time between the activation of the word line word and the activation of the sense amplifier 30 the address line is inactivated simultaneously with the falling edge of the clock signal clk and the word line word and the bit line selection signal rd en are inactivated slightly later the sense signal sense falls in response to the inactivation of the bit line selection signal rd en to inactivate the sense amplifier 30 in the read circuit 2 after the end of the read time period the precharge time period starts again during which the pair of read output lines sa 0 and sa 1 of the sense amplifier 30 are predischarged to the ground potential by the nmos transistors nprc 0 and nprc 1 thus if the read output line sa 0 or sa 1 in the initial state starts being charged by mistake due to the unbalanced transistor performances in the sense amplifier 30 during the read operation the potential of the output line sa 0 or sa 1 rises only slightly from the ground potential and the above described complementary operation functions insuring the provision of the correct output data dout.