nand gate 17 inputted with the output signals of the nand gate 15 and the nand gate 16 then the second logic circuit 132 comprises a nand gate 19 inputted with the output signal h of the nor gate 122 and the q output signal j of the counter 9 and an inverter 20 for inverting the output signal of the nand gate 19 then the third logic circuit 133 comprises a nand gate 21 inputted with the output signal g of the and gate 121 and the q output signal i of the counter 9 and an inverter 22 for inverting the output signal of the nand gate 21 the output signal k of the first logic circuit 131 is inputted to the cp terminals of the presettable counter 9 the output signal l of the second logic circuit 132 is inputted to the cl terminal of the counter 9 and further the output signal m of the third logic circuit 133 is inputted to the pr terminal of the counter 9 the q output signal i and the q output signal j of the counter 9 are connected to terminals 23 24 which are connected to the detection output circuit 8 not illustrated refer to fig1 the presettable counter 9 is constituted as shown in fig4 four flip flops 91 92 93 94 are connected in series to form a 16 step counter the output signal k of.