an electronic device computes a compensation factor using the first 32 bits of known synchronization word step 190 this compensation factor can be expressed as at some point that electronic device receives an rf signal including the synchronization word step 195 this rf signal is then demodulated and downconverted to a baseband signal which is in turn converted from analog to digital form steps 200 and 205 samples of the first 34 bits of the synchronization word are then taken and stored step 190 next the dc sum is calculated using 32 u00d7 n samples although the first 34 u00d7 n n being the number of oversampling as compared to the nominal symbol rate running samples from the a d converter can be stored hardware complexity can be reduced by using only 32 u00d7 n samples in the calculations the dc sum can be estimated by d u2062 u2062 c s u2062 u2062 u u2062 u2062 m u2061 k u2211 i k 32 u2062 x u2062 u2062 n 1 k u2062 y u2061 i where k is the sample time index and y i is the output from the a d converter 135 using this dc sum a dc avg can be estimated step 215 dc avg can be represented as finally the compensated dc average can be calculated step 220 by next the received data as dc adjusted and bit sliced can be compared against the known synchronization word to determine if there is a correlation step 225 when the number of matched bits between the bit sliced data and the known synchronization word is greater than or equal to a threshold.