a selection signal to the selector 12 the output terminal of tee flip flop 14 is also connected to the other input terminal of the and gate 17 the input terminal of an inverter 18 and one input terminal of an or gate 19 the other input terminal of the or gate 19 receives the write instruction signal 10 the output terminal of the or gate 19 is connected to the write terminal we of the memory 1 the output from the inverter 18 and the data signal 102 are input to an and gate 16 and the output from the and gate 16 is connected to the data input terminal d of the memory 1 the initialization instruction validity control circuit 8 as the characteristic feature of the present invention comprises a flip flop 22 for validating or invalidating an initialization instruction an inverter 22 for inverting the output signal from the flip flop 21 and an and gate 23 for calculating a logical product between the output from the inverter 22 and the initialization instruction signal 71 from the initialization instruction generator 7 and for supplying its output to the flip flop 14 of the memory initialization circuit 4 the operation of the system shown in fig2 will now be described when the flip flop 21 of the initialization instruction validity control circuit 8 is set at level 34 0 34 since the and gate 23 is enabled by the output from the inverter.