instruction for the memory and or i o a counter for counting the number of times a read write control signal is generated and a timing controller for generating various timing control signals when the word transfer instruction for the memory and or i o is executed when the microprocessor performs the word transfer instruction for the memory and or i o the read write control signal is enabled and disabled to perform two access cycles the word transfer instruction can be automatically converted to two 1 2 transfer instructions application_number US 19675288 A description the present invention will be described in detail with reference to a preferred embodiment fig3 is a block diagram of a microprocessor system configured by connecting a memory and or i o 17 having an 8 bit data bus width to a 16 bit microprocessor 11 at first the architecture of the system will be described with reference to fig3 the microprocessor system comprises the microprocessor 11 a read write controller 12 an address latch counter 13 a timing generator 14 a bus converter 15 a 16 bit memory and or i o 16 the 8 bit memory and or i o 17 and a system bus 18 the timing generator 14 comprises a detector 19 a counter 20 and a timing controller 21 the microprocessor 11 receives a clock clk and a wait control signal wait from the controller 21 and supplies status data sts1 to the controller 12 and an address adr 19 0 to the counter 13 the controller 12 comprises a decoder 31 a pulser 32 a latch 33 and a gate 34 as.