circuit to begin a load cycle in one of the 4 memory buffers the memory buffer in which the load cycle is occurring is selected by a low level signal on its r w enable line a load cycle required 1 4 of a revolution of the head wheel and begins with buffer 1 the sequence of buffers followed is then 2 3 4 1 2 etc until the recording is complete a load cycle is begun by a high to low signal transition on the track clock delayed tcd which initiates pulse synchronizer a6 the input to a6 is the load clock which is 1 4 of the system clock the output the pixel clock is counted up by a8 a9 and a17 and when binary 4095 is reached the circuit is reset by the reset load signal and awaits another high to low signal transition on the tcd the number n of pixels in each track is determined by 2 u00d7 4096 n where n is the number preloaded into the counters by sa lsb sl msb the remaining sets of outputs are generated by dividing the pixel clock by 2 the input data clocks go to the comparator circuit and load the data on data flip flops the memory chip enables cea1 cea4 ceb1 ceb4 are the chip enables for the 8 rams the deskew logic provides the unload clock for the memory the deskew circuit is shown in fig1 the output trigger generates a delayed pulse which is used to initiate.