can produce local non uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features application_number US 29943402 A description fig2 a 2 f show structures formed during processing in accordance with a preferred embodiment fig2 a shows a semiconductor substrate 10 on which is formed a silicon oxide gate insulating layer 12 and a polysilicon gate conductive layer 14 formed over the gate conductive layer 14 are an amorphous carbon lower hardmask layer 16 a sion upper hardmask or capping layer 18 and a photoresist mask 20 that defines a pattern to be transferred to the polysilicon gate conductive layer 14 to form a mosfet gate line the geometry of the photoresist mask may be reduced by isotropic trimming prior to any patterning of underlying layers this enables the patterning of features that are smaller than the feature size originally formed in the photoresist mask thus for example a feature patterned in the polysilicon layer 14 may be made narrower than the narrowest feature size that can be provided in a photoresist mask fig2 b shows the structure of fig2 a after etching of the sion upper hardmask layer using a fluorine or fluorine chlorine etch chemistry to pattern the sion layer to form.