processing system the controller 208 enforces ordering constraints on memory operations based on information it receives from the decoder 204 the information may include the attribute for each bus transaction which may be stored in a first input register 302 the information may also include data that identifies each memory device other than the target memory device that the originating processor is capable of accessing the particular memory devices accessible by each processor are preconfigured during the design stage and therefore can be programmed or hardwired into the decoder 204 in any event a second input register 304 may be used to store this information the first and second input registers 302 304 may be separate registers as shown in fig3 or alternatively a single register in some embodiments of the controller 208 the information from the decoder 204 may be stored in registers shared with other bus interconnect functions each register may be a fifo or any other suitable storage medium the controller 208 enforces ordering constraints on data transfer operations by controlling the timing of data transfer bus transactions released from the bus register 202 the process will first be described in connection with an attribute which indicates that a strongly ordered memory data transfer bus transaction is ready to be released from the bus register 202 in this case the attribute is provided from the first input register 302 to a memory barrier generator.