a certain thickness of the latter oxidation then produces a film 3 u2032 of oxidized electrically insulating poly crystalline silicon on a sub layer 3 u2033 of non oxidized doped p poly crystalline silicon the sub layer of poly crystalline silicon 3 u2033 and the implanted regions 19 form the gate of the transistor the film of oxidized poly crystalline silicon 3 u2032 electrically insulates this gate of the source of the transistor done in a later step of the method during this oxidation step the poly crystalline silicon is consumed and tends to disappear this consumption of the poly crystalline silicon occurs mainly at the level of the large surfaces of the layer of poly crystalline silicon and therefore mainly in the secondary trench 111 of the substrate 1 advantageously the thickness of the layer of poly crystalline silicon deposited initially i e prior to oxidation is provided such that the remaining thickness of oxidized poly crystalline silicon i e after the oxidation step is substantially equal to 1 5 u03bcm corresponding around a 2 3 ratio of the depth of the trenches 12 and 13 apart from the dimensions of the trenches the threshold voltage and the specific resistance of the jfet transistor obtained on completion of the method depend also on the thickness of the layer of poly crystalline silicon as well as the value of its doping therefore the electrical characteristics of the jfet transistor depend on easily controlled parameters i e width and depth of trenches thickness and doping of the layer of poly crystalline silicon of the manufacturing method illustrated in fig3 in the event where the layer of oxidized poly crystalline silicon is not completely consumed at the level of the secondary trench 111 the method can comprise an extra etching step.