a high read signal applied to pin 96 then turns on nmos read transistor 98 to output a voltage on pin 99 approximately equal to that at the source of transistor 102 the voltage at the output pin 99 connected to a column line may be applied to an analog to digital converter without any conversion of charge into voltage in contrast to the circuit of fig2 the difference between the output voltage at reset and the output voltage after integration is used in one embodiment to generate the light information using the difference provides offset cancellation and first order cancellation of variations in the source followers that form the output buffer of each pixel after the voltage at pin 99 is read by conventional circuitry typically pursuant to row and column addressing operations the reset signal and shutter signal are pulled low to charge lines 76 85 and 86 for a new detection cycle a voltage other than vdd may be used to charge the lines 76 85 and 86 additional integrating capacitance may be added to line 86 for any reason such as for gain control such capacitance may be provided as parasitic capacitance fet capacitors or other types of capacitors 1 a small integrating capacitor can be used resulting in increased light sensitivity of the pixel and a smaller pixel area 2 the source follower isolates the integrating capacitor from other circuitry reducing noise and increasing design freedom 4 decoupling the capacitance of the light sensitive device e g phototransistor 60 from the integrating capacitance by transistor 64 allows the use of either a phototransistor or photodiode as the light gathering device it also allows the detector to be made larger to.