so as to select one memory cell the row address decoders are activated by a word line driver clock signal of a word line driver the word line driver clock signal is generated only during a predetermined time period after the change of address information and accordingly the selection time period of the word line is small application_number US 50850583 A description in fig1 which is one embodiment of the present invention known static type memory cells c ij i j 0 1 n 1 are arranged in an n row n column matrix each memory cell is conducted to one word line and a pair of bit lines for example a memory cell c 00 is connected to a word line wl 0 and to bit lines bl 0 and bl 0 selection of the word lines wl 0 wl 1 wl n 1 is performed by the row selection signals x 0 x 1 x n 1 of row address decoders rd in this case the row address decoders rd decode the address signals a 0 a 0 a 1 a 1 a l 1 a l 1 2 l n however the generation of the above mentioned row selection signals x 0 x 1 x n 1 requires the generation of a word line driver clock signal u03c6 w of a word line driver wd in addition the bit lines bl 0 bl 0 bl 1 bl 1 bl n 1 bl n 1 are connected to column selection gates q b0 q b0 39 q b1 q b1 39 q b n 1 q b n 1 39 respectively and each gate pair is controlled by column selection signals y 0 y 1 y n 1 that is the selection of the bit line pairs is.