the processing of a next frame only in case the actual time interval is equal to or larger than this minimum value the local controllers ctr 1 and ctr 2 power down the corresponding coprocessor at the moment the processing of a next video frame should start the local controllers ctr 1 and ctr 2 power up the coprocessors cop 1 and cop 2 respectively in an alternative embodiment the coprocessors cop 1 and cop 2 are powered up by the central processing unit cpu when it requests for processing a next block of data in another embodiment of the invention the central processing unit cpu can be further programmed to implement stall cycles for coprocessors cop 1 and cop 2 interspersed between clock cycles of the sequence of clock cycles used for processing of data by the coprocessors during a stall cycle the coprocessors cop 1 and cop 1 still receive a clock signal but do not respond due to stall cycles generated by their corresponding local controller the usage of stall cycles for lowering the actual data transfer rate is further described in u s copending application ser no 09 920 042 attorney docket phnl010506 also assigned to the present assignee herein incorporated by reference in distributed data processing data may be presented to or may be required from the system bus sb on short notice and or in high intensity bursts when such transfers would occur within short time frames overall system bus capacity would readily and frequently be exceeded which would then lead to a stall situation for the component requesting.