most of the residual area is made of the first layer of polycrystalline silicon on the oxide layer whereby the collection of electrons generated by u03b1 rays is reduced so that erroneous operation is not easily caused fig5 a and 5 b are respectively a plane view of an other embodiment of the semiconductor memory device of the present invention and a sectional view taken along the c c 39 line thereof in fig5 the references 12 and 13 respectively designate n region added junction capacitors which are connected to expand the region for the memory capacity c s2 beyond the region shown in fig4 thus the junction capacity between the n region and the p type semiconductor substrate can be added in parallel to the mis capacitors m and m 1 to increase the memory capacity c s2 thus the distance between the first layer of polycrystalline silicon 5 and the first layer polycrystal silicon for the m th bit line or the first layer polycrystal silicon for the m 1 th bit line 11 can not by reduced less than a constant distance given depending upon the condition of preparation fig6 a and 6 b are respectively a plane view of an other embodiment of the semiconductor memory device of the present invention and a sectional view taken along the d d 39 line thereof in this case the second layer of polycrystalline silicon used for the switching transistors l and l 1 partially covers the first layer of polycrystalline silicon 10 used for the m th bit line.