bits or all of the bits of the bank refresh indicator register 212 to a low level thus the command sequence programs the bank refresh indicator register 212 and declares the contents of the respective memory banks 208 as relevant and without necessity to be refreshed the self refresh circuit 210 monitors the contents of the bank refresh indicator register 212 and starts the activate precharge sequence only for those banks where the respective bit b i of the bank refresh indicator register 212 is set to the high level for those banks where the respective bit b i is low the self refresh circuit 210 suppresses the refresh of wordlines of those banks thus the circuit 210 avoids unnecessary power consumption for refreshing banks which are defined to not require to be refreshed by a low level of the respective bit b i in the bank refresh indicator register 212 the circuit 210 can be altered in such a way that it either checks the bank refresh indicator register 212 1 only in case of self refresh mode or 2 both in self refresh and auto refresh mode as shown in fig3 two parallel processes are controlling the self refresh u2014 and with respective implementation also autorefresh u2014 process 300 the two processes are performed by a global control circuit that includes the command decoder 216 the sub process 302 controls the contents of the bank refresh indicator register 212 at power up of the memory device step 304 all bits b i of the register get reset to low level equal to logical 0 per step 306 whenever a command is detected at the memory device 204 by the command decoder 216 the command is checked if it is an.