12 of the active fet 10 and to ground through a bypass capacitor 25 the source terminal 26 of the second fet 22 is coupled to the first terminal of a source resistor rs with the second terminal of rs coupled to ground the first terminal of rs is also coupled to the gate terminal 28 of the second fet through a capacitor 30 the gate voltage of the second fet is set by a compensating voltage divider 32 including resistor r3 and r4 coupled at an output node 33 a first terminal of the compensating voltage divider 32 is coupled to the first terminal of the drain resistor rd and the second terminal of the voltage divider 32 is coupled to ground the output node 33 is coupled to the gate terminal 28 of the second fet 22 a bias generating voltage divider 34 is formed of resistors ri and r2 and provide the bias voltage for the first fet 10 the operation of the circuit depicted in fig1 will now be described the dc gate voltages of the active and second fets 10 and 22 are determined by the bias and compensating voltage dividers the values of r1 r2 r3 and r4 are selected generate bias voltages to set the steady state of i ds to a selected value however as described above process dependent variations of i dss will cause the value of the actual i ds to vary from the selected value as is well known the voltage drop across rd is proportional to the i ds flowing through the active fet 10 and the i ds of both.