required since eeprom memory uses a higher voltage for writing than the rom or ram memory further due to the slower speed of a writing operation on eeprom than on either rom or ram a control logic must be used interrupt logic is activated when the eerom has been written in for a period of approximately 10 milliseconds an interrupt is generated at that time to notify the system controller that the eerom byte writing operation has been performed fig3 shows a typical group controller with its processor and memories accessible to the processor over a group address and data bus shown are a program memory scratchpad memory shared and unshared memory time slot interchanger and additional circuits the additional circuits serve to interface between the group and the ports of the system as interface and as latches and codec control the latter is required since a codec is employed at each port to code information to the system in suitable pcm format as mentioned previously call processing information necessary for use by the system controller is stored in shared memory of the group controller for transfer to the system memory over the system bus when indicated data from the system bus also is transferred to the group control through the shared memory to determine whether data should be sent from the shared memory of the group controller to the system controller or from the system controller to the shared memory of the group controller a shared memory arbitrator is used a similar arbitrator for a like function is disclosed in the cited ahmed u s pat no 4 379 950 in fig4 the maintenance procedures and diagnostic procedures of the system are shown in block.