the first internal bus 30 is coupled to a synchronism character register 26 a transmitter 27 a receiver 28 and a modem control circuit 29 the transmitter 27 the receiver 28 and the modem control circuit 29 are coupled to the status register 25 and the control circuit 21 by a status bus 32 the control word register 22 receives control words from the host processor 1 the transferring data buffer 23 receives data from the host processor 1 in parallel and sends them to the first internal bus 30 according to a control signal of the control circuit 21 the data of the buffer 23 is entered into the transmitter 27 and is transferred to the modem 11 in series through a terminal 40 td on the other hand data from the modem 11 are serially entered into the receiver 28 through a terminal 44 rd and are sent in parallel to the receiving buffer 24 via the first internal bus 30 thereafter the data set in the buffer 24 is transferred to the host processor 1 through the bus 33 and the external bus 13 the synchronism character register 26 is used to detect the start of data the modem control circuit 29 receives a clear to send signal cts and a data set ready signal dsr from the modem 11.