fig2 n channel devices mn 6 and mn 7 are high voltage high threshold devices also p channel devices mp 6 and mp 7 provide a current to charge capacitors c 3 and c 4 which couple the voltage changes on the non overlapping clock inputs clka and clkb respectively to the gates of p channel transistors mp 4 and mp 5 respectively to turn the same off when the respective clock signal is high and to turn the same on when the respective clock signal is low in operation when clock signal clka is high and the opposite clock signal clkb is low devices mn 4 and mp 5 will be turned on and devices mn 5 and mp 4 will be turned off this connects node 1 to the source of tail current devices mn 2 etc through device mn 4 with device mp 5 pulling node 2 to the power supply voltage v dd at this time node 4 will be pushed above voltage v dd by the voltage on capacitor c 2 turning device mn 6 on so that capacitor c 1 will charge at a rate set by the tail current for the differential pair mn 4 mn 5 because device mn 6 is on node 3 will be at voltage v dd holding device mn 7 off to allow node 4 to go above v dd as previously described with node.