the incoming input control information from the plurality of input ports and compresses the information in a form which allows an easy association with a respective output port to which an individual input port is temporarily mapped application_number US 42513303 A description with general reference to the figures and with special reference now to fig1 a prior art switch chip 10 comprises an actual switching core 12 having some memory and control logic in order to switch data packets from a number of m input ports to a number of n output ports each packet 14 comprises a section 16 for the payload i e the use data and a header section 18 which comprises any control data in order to enable correct routing of a packet a shell 19 comprises some application based logic and links in order to embed the core according to the specific requirements in a particular location of the switching network or according to a particular application for which the switching network is actually in use this switching network may now be improved by the inventive principles illustrated in more detail with reference to fig1 a and 2 to fig5 with additional reference to fig1 a a possible implementation of the switching core 12 is represented introducing the present invention and comprises a buffer crossbar for which the present invention is particularly applicable in this.