12 and the mount region tr 4 is disposed between the semiconductor chip m 15 and the external terminal 20 meanwhile on the second principal surface 12 the mount regions tr 5 to tr 8 are disposed at the positions overlapped with the mount regions tr 1 to tr 4 in the planar view since the termination resistors rterm include extremely small sized chip parts the joint strength thereof with respect to the module substrate 10 is lower than that of the semiconductor chips m 1 to m 36 and the risk of detachment is high in a case of contact upon handling etc such a problem is particularly notable at the termination resistors rterm in the upper level which are readily contacted upon handling however since the mount regions tr 1 tr 3 tr 5 and tr 7 positioned in the upper level are positioned not at ends of the module substrate 10 but at the parts sandwiched by the two semiconductor chips the risk of contact with the chip parts upon handling is low this is for a reason that the heights of the chip parts of the termination resistors rterm are lower than the heights of the semiconductor chips in addition to the fact that they are distant from the vicinities of the short sides which mainly serve as contact parts upon handling fig2 is a circuit diagram for explaining the connections of the register chip rb and the semiconductor chips m 1 to m 10 and m 19 to.