a across the terminals 11 12 will cause current flow through series connected resistors 20 22 28 a turn on retarding capacitor 23 is connected across the second voltage divider resistor 22 as illustrated a first npn type transistor 30 a second pnp type transistor 31 and a third npn type transistor 32 are interconnected to provide a very high gain compound transistor having a current input 34 a current output 35 and a control input 36 the emitters of transistors 30 32 are tied together to the current output 35 while the collector of transistor 31 and the base of transistor 32 are tied together and in turn connected to the current output 35 via a first temperature compensation resistor 26 the emitter of transistor 31 and the collector of transistor 32 are tied together to the current input 34 of the compound transistor while the base of transistor 31 and the collector of transistor 30 are tied together and connected to the current input 34 via a second temperature compensation resistor 24 the current input 34 of the compound transistor is electrically connected to the positive voltage buss 13 while the current output 35 of the compound transistor is connected to the high side of the proportioning resistor 28 the compound transistor control input 36 constituted by the base lead of transistor 30 is connected to the junction of the collector of current diverter transistor 16 and the bias current providing resistor 18 as a current limit fold back.