peripheral circuit region thereby finally completing a dram as in the above first embodiment the gate electrode sidewall film thickness in the memory cell array region and that in the peripheral circuit region are different this improves the data holding characteristic in the memory cell array region and increases the operating speed in the peripheral circuit region by forming the source drain structure as a shallow junction also a self alignment contact formation process can be applied when the gate electrodes are formed this achieves high applicability to a device having a high integration degree such as a general purpose dram memory cell in the first and second embodiments described above the gate electrode has a stacked structure including a conductive layer and insulating layer in this embodiment the gate electrode has only a conductive layer as shown in fig1 to form an element region in a surface portion of a semiconductor substrate 1 through steps similar to those of the first embodiment an element isolation groove 2 about 3 000 u00e5 deep is formed by photolithography and rie after a thermal oxide film is formed by thermal oxidation on the side surfaces of the element isolation groove 2 a silicon oxide film such as teos is buried as an element isolation buried oxide film 3 in the element isolation groove 2 an element region and element isolation region are then formed through a planarizing process such as cmp in addition a trench capacitor 18 is formed in a memory cell array region on the surface of the semiconductor substrate 1 a sacrificial oxide film 17 about 70 u00e5 thick is formed by thermal oxidation after that a well channel impurity.