signal variation in node 23 in fact the second ota 104 may have a maximum output current which is almost double the operating point supply current n 1 i d229 2 giving a sr value of the entire second ota 104 may be biased by the drain current of nmos transistor 229 which has a gate connected to a biasn node 230 which is available within the bandgap reference 14 fig2 both bias nodes biasp 212 and biasn 230 may impose proportional to absolute temperature ptat supply currents for the first ota 102 and the second ota 104 which reduces the loop gain dependence on temperature in one embodiment the current flowing through the voltage divider resistors 30 and 32 is chosen to be about 5 u03bca which is higher than the maximum estimated leakage current of the power pmos 24 a selected value of the compensation capacitor 106 may depend on a selected value of the resistor 30 the compensation capacitor 106 and the resistor 30 together produce a zero located at about 500 khz to about 1 mhz which enhances the phase margin for high load currents the configuration of the power pmos transistor 24 in fig3 may be selected in view of the targeted.