type shift register according to the prior art arrangement and to the arrangement of this invention respectively through the cas terminal for cascade connection the fbo terminal and the gldo terminal for generating gold codes in fig3 a sr i designates the flipflop selected by the multiplexer mux1 the signal propagation path according to the arrangement of this invention is reduced than that required by the prior art arrangement wherein the signal passes through the multiplexer and therefore it is possible to reduce the propagation delay time furthermore it is possible to construct a gold code generating device as indicated in fig4 by using a pseudo random noise code generator of this invention as indicated in fig2 in fig4 png1 and png2 represent pseudo random noise code generators having the same structure as indicated in fig2 fig5 a and 5 b show the signal propagation paths hereinbelow called a critical path wherein the propagation delay time become maximum in a case that prior art pseudo random noise code generator and a pseudo random noise code generator of this invention are used in the gold code generating device indicated in fig4 the signal propagation path in the device of this invention indicated in fig5 b is reduced in comparison with that required by the prior.