bytes of data on data bus 8 are reformatted into a single 32 bit data word by data packer 10 the output of which appears on data bus 9 in the preferred embodiment data packer 10 was constructed of four 8 bit emitter coupled logic or ecl as it is known in the art latches specifically four 8 bit ecl latches are used to form the 32 bit word data is latched into the appropriate 8 bit latch on each clock pulse which in fig2 is delivered on line 11 the 8 bit words are written into the latches in a circular fashion with a new 32 bit word being produced for every 4 clock pulses a clock signal shown in fig2 as a pulse train labelled clock in fig2 having at least the same frequency as the original data stream of 8 bit data words on data bus 8 data must be delivered to data packer 10 after data on bus 8 is valid see datain in fig2 for timing the formation of a 32 bit word four clock cycles t 1 through t 4 as shown in fig2 are required by data packer 10 to generate a single 32 bit data word from four 8 bit datain data words d1 d2 d3 and d4 in fig1 clock pulses from the data source or derived from the data stream itself are delivered to 34 fifo 34 control 13 on.