c illustrates only one possibility of offsetting capacitive imbalances provided by the core cells 112 and 112 u2033 and other arrangements will also work so long as the additive capacitive imbalances of core cells 112 are offset by the additive capacitive imbalances of core cells 112 u2033 fig3 a shows an exemplary six transistor core cell 112 in accordance with one embodiment of the present invention core cell 112 is a standard six transistor core cell having cross coupled inverters defined by transistors 310 312 314 and 316 in addition a pair of passgate transistors 313 and 315 are shown having their gates coupled to a wordline that is used to access a particular row of core cells 112 passgate transistors 313 and 315 are also respectively coupled between the bitline bl and the complimentary bitline bl as mentioned above because this standard core cell is symmetric the flipping of the core cell 112 to produce core cell 112 u2033 will not change the data latching ability of the circuit accordingly the operability of the core cell 112 u2033 will be functionally the same as that of core cell 112 when data is either written in or read out by accessing the global bitlines gbl and the global complimentary bitlines gbl 0047 fig3 b shows a circuit diagram of the core cell 112 once it has been fabricated on a semiconductor substrate in accordance with one embodiment of the present invention of course it should be understood that the layout geometries of the core cell 112 of fig3 b.