counter 2 a is reset and the output signal of the and gate 2 b returns to a low level 0049 fig6 is a circuit diagram of the 4 bit register section 4 shown in fig3 an output signal 4 bit data of a 4 bit up down counter 3 is supplied to a negative signal input terminal of a comparator 4 b a positive signal input terminal of a comparator 4 c and a data input terminal of a register 4 e the 4 bit data representing an upper limit value is supplied to a positive signal input terminal of the comparator 4 b the comparator 4 b outputs a high level comparison result signal 1 bit data while the output of the 4 bit up down counter 3 is equal to or smaller than the upper limit value on the other hand the 4 bit data representing an lower limit value is supplied to a negative signal input terminal of the comparator 4 c the comparator 4 c outputs a high level comparison result signal 1 bit data while the output of the 4 bit up down counter 3 is equal to or greater than the lower limit value the set signal 1 bit data of the 4 bit counter section 1 is supplied to one of signal input terminals of the 2 input and gate 4 a the remaining signal input terminal of the and gate 4 a is connected to an output terminal of the 2 input and gate 4 d a signal output terminal of the comparator 4 b is connected one of signal input terminals of the 2 input and gate 4 d and also connected to an enable terminal e of a counter 4 f additionally a signal output terminal of the comparator.