is regarded as the designation of the above described operation mode when a bit designating signal to be applied to each of data input output terminals dq1 dq4 at that time is at a low level read of the bit is allowed while when the signal is at a high level read of the bit is inhibited fig3 is a block diagram showing the read control circuit 9 and the output buffer 7 of fig1 with reference to fig3 read control circuit 9 includes a mask enable signal generation circuit 9a mask data registers 9b1 9b2 9b3 and 9b4 and or gates 9c1 9c2 9c3 and 9c4 output buffer 7 includes data output buffers 71 72 73 and 74 j is given to a corresponding bit number in the following description mask enable signal generation circuit 9a determines an existence of an operation mode designating signal wb at a fall of an internal ras signal when the circuit determines the existence of operation mode designating signal wb the circuit 9a generates a mask enable signal for activating mask registers 9b1 9b4 each of mask data registers 9b1 9b4 is connected to the corresponding bit data input output terminal dqj to hold a bit designating signal applied to the corresponding data input output terminal dgj in response to the mask enable signal each of or gates 9c1 9c4 has two input terminals and one output terminal one input terminal being connected to receive 0e signal and the other input terminal being connected to receive a bit designating signal held by the corresponding mask data register 9bj the respective or gates 9c1 9c4 generate read control signals rc1 rc2 rc3 and rc4 for controlling read of each bit.