transfer gate transistor includes source drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions a buried strap electrically connects the capacitor to one of the source drain regions of the transfer gate transistor a portion of the buried strap includes recrystallized silicon application_number US 64398396 A description the present invention will be described in detail with reference to fig4 a 4h as shown in fig4 a a buried n type well 100 is formed in a p type semiconductor substrate 10 by implanting phosphorous below the intended p well for a memory cell array a buried n type well may also be formed by other methods e g p well implantation into an n type semiconductor substrate or by epitaxy and the invention is not limited in this respect a silicon nitride layer 102 of about 0 2 micrometers is formed by chemical vapor deposition for example on the surface of a thin oxide layer 101 e g about 10 nanometers which is thermally grown on semiconductor substrate 10 oxide layer 101 and silicon nitride layer 102 are patterned and etched to provide a mask for etching a trench 103 trench 103 is etched using an anisotropic etching process to a depth of about 8 micrometers as shown in fig4 b after storage node trench 103 is etched an n type capacitor plate 104 is formed by outdiffusing arsenic from the lower portion of.