sa e in the sense amplifier array saa between the two sub mats sm n and sm 1 on the left side in fig4 operation waveforms of corresponding local bit lines lbl e 1 and lbl e 2 in the two sub mats sm n and sm 1 that are adjacent to each other in the memory mat m n and operation waveforms of other related signals the operation shown in fig6 is assumed to be for example a read operation to read data of a memory mc selected in the sub mat sm 1 initially when the normal operation of the dram is started in fig6 the bit line equalizing signal bleq is at the high level and the pair of global bit lines gbl e and gbl e and the local bit lines lbl e 1 and lbl e 2 have been respectively precharged to the predetermined precharge voltage vpre at this point the precharge voltages vblpe and vblpo of fig4 and 5 are controlled to satisfy vblpe vblpo vpre vref by the precharge voltage generating circuit 20 subsequently an active command act is issued and at the same time a row address a 1 for designating an access target is received thereby the row control signal rcnt fig3 is activated to the.