the dn bits for the next print cycle 39 s dot 1 1281 2561 and 3841 the second srclk1 pulse will transfer the dn bits for the next print cycle 39 s dot 5121 6401 7681 and 8961 after 1280g srclk pulses 1280 to each of srclk0 and srclk1 the entire line has been loaded into the printhead and the common lsyncl pulse can be given at the appropriate time as described above the nozzles for a given chip 3 do not all print out on the same line within each color there are d nozzles on a given line with the odd and even nozzles of the group separated by d 2 dot lines there are d 1 lines between corresponding nozzles of different colors d 1 and d 2 parameters are further described in section and section the line differences must be taken into account when loading data into the printhead considering only a single chip group table 2 shows the dots transferred to chip n of a printhead during the a number of pulses of the shared srclk with regards to printing we print 10c nozzles from each chip in the lowest speed printing mode and 80c nozzles from each chip in the highest speed printing mode while it is certainly possible to wire up chips in any way this document only considers the situation where all chips fire simultaneously this is because the low speed printing mode allows low power printing for small printheads e g 2 inch and 4 inch and the controller chip design assumes there is sufficient power available for.