in fig4 a the time frame has been greatly reduced so as to provide a frame that will permit the disclosure of the signals shown in fig4 b through 4f as discussed previously the spacing between adjacent horizontal lines of the test pattern appearing on screen 35 is one inch this in turn requires that counter 19 be preset to count to thirty five and then provide at the output thereof a logic 34 1 34 pulse thus when the signal of fig4 a is supplied to the input of counter 19 counter 19 provides at the output thereof a pulse signal similar to that depicted in fig4 b the pulse signal of fig4 b is then supplied to nand gate 21 which inverts the signal so as to provide at the output thereof a signal similar to that depicted in fig4 c when the signal of fig4 c changes from a logic 34 1 34 state to a logic 34 0 34 state the q output of flip flop 23 will change from a logic 34 0 34 state to a logic 34 1 34 state as shown in the signal waveform of fig4 d this in turn opens nand gate 25 so as to allow the thirty sixth clock pulse of the signal of fig4 a to pass therethrough and be inverted thereby as shown in the signal waveform of fig4 e when the signal of fig4 e changes from a logic 34 1 34 state to a logic 34 0 34 state the q output of flip flop 23 will change from a logic 34 1 34 state to a logic 34 0 34 state as shown in the signal waveform of fig4 d the signal.