precharged to a logic high voltage v dd and the access transistors of the corresponding sram cell are turned on by activating the corresponding word line under these conditions the one of the storage nodes of the sram cell will pull the corresponding bit line down toward ground and the other one of the storage nodes of the sram cell will pull the corresponding bit line up toward v dd as a result a voltage difference is created across the bit line pair b b this voltage difference is detected by a sense amplifier not shown in accordance with the present embodiment if the tcam cell being read is above the bit line twist location 302 i e in the upper half of column 301 then the first bit line polarity is used to identify the read data value that is a logic high voltage on bit line b and a logic low voltage on complementary bit line b is recognized and reported as a logic u2018 1 u2019 data value and a logic low voltage on bit line b and a logic high voltage on complementary bit line b is recognized and reported as a logic u2018 0 u2019 data value conversely if the tcam cell being read is below the bit line twist location 302 i e in the lower half of column.