c3 5 6 7 8 1 2 3 4 b 1 2 3 4 1 2 3 4 6 a c3 c4 c4 c1 c1 c2 c2 c3 6 7 8 1 2 3 4 5 b 2 3 4 1 2 3 4 1 7 a c4 c1 c1 c2 c2 c3 c3 c4 7 8 1 2 3 4 5 6 b 3 4 1 2 3 4 1 2 8 a c4 c1 c1 c2 c2 c3 c3 c4 8 1 2 3 4 5 6 7 b 4 1 2 3 4 1 2 3______________________________________ a data areas of data registers a a pair of column select lines selected b rwd lines connected to registers the mode in which 3 address bits representative of the 8 bit series data are accessed by repeating 34 0 34 and 34 1 34 in sequence irrespective of the carry bit from the least significant bit will be next explained in this access sequence the least significant bit repeats 34 0 34 and 34 1 34 alternately for each cycle the second bit repeats 34 0 34 and 34 1 34 for each two cycles as 34 00110011 34 and the third bit repeats 34 0 34 or 34 1 34 for each four cycles as 34 0000111100001111 34 table 2 lists the similar relationship among the eight serial and cyclic access modes classified according to the eight head address a pair of select lines c1 to c4.