receive the signal nclk an output pcnt of the first counter 902 is interconnected with an input of the control logic 910 an output ncnt of the second counter 904 is interconnected with another input of the control logic 910 counters 902 and 904 each have an input to permit a predetermined number m and n respectively to be loaded as in the embodiment described in connection with fig6 8 the counters 902 and 904 can be count up or count down counters and the signals pcnt and ncnt will indicate the passage of m or n cycles of the clock signal pclk or nclk respectively also as illustrated in fig6 8 the sector counter 907 and the slip enable latch 909 are loaded with the distance in sectors to the band boundary to allow the signal ena to disable clock slipping at the end of the last sector in band n 1 outputs ld1 and ld2 of the control logic 910 are interconnected with inputs of the counters 902 and 904 respectively to activate the load process of each the control logic 906 also has clear and enable inputs clr and ena respectively and another output sel interconnected with a third input of the switch 906 an input of the gate 908 is coupled to receive the output signal swclk from the switch 906 a second input of the gate 908 is interconnected with a fourth output of the control logic 910 an output bndclk of the gate 908 carries either the pure clock signal pclk or.