type flip flop dff 17 which receives the output signal v6 of the comparator 16 at its d input and the pulse s h2 at its clock input and which provides a q output swq for controlling the selecting switch 12 and a cpu 25 which differs in function from the cpu 24 of fig4 the cpu 25 generates from the signal sw30 the pulses s h1 and s h2 show n in the timing chart of fig1 in fig9 when the pulse s h2 changes from the low level to the high level if the signal f2 gt the signal f1 the signal swq is latched at its high level whereas if the signal f2 lt the signal f1 the output signal swq of the dff 17 goes to its low level if the signal swq is at the high level the selecting switch 12 is connected to the terminal c whereas if the signal swq is at the low level the selecting switch 12 is connected to the terminal d fig1 shows a track pattern in which tracks are discontinuously recorded fig1 shows waveforms which respectively appear at the relevant portions when the tracks of fig1 are continuously reproduced by means of the embodiment shown in.