include in the order listed 1 forming plating base layer 285 2 forming dielectric layer 350 3 photolithographically defining the extent of dielectric layer 350 and then etching dielectric layer 350 and 4 forming additional plating base layer 355 fig7 is a top layout view of an integrated circuit chip containing structures according to the embodiments of the present invention fig7 illustrates interconnects 310 ultra fat wire 330 and capacitor 335 in fig7 interconnects 310 are spaced apart a distance s 1 in a first direction and a distance s 2 in a second direction orthogonal to the first direction in one example s 1 s 2 in one example s 1 s 2 w while all structures are laid out on the interconnect grid center to center spacing of s 1 w 2 s 2 w 2 other layouts are possible interconnects 310 may be replaced by copper interconnects 310 a of fig2 f 310 b of fig4 b 310 c of fig6 325 of fig3 a 325 a of fig3 b or copper block 300 of fig2 d fig8 a and 8b illustrate bonding of interconnect structures according to the present invention to higher level of packaging in fig8 a an integrated circuit chip module 365 includes a substrate 370 which may be a ceramic substrate and which may.