insulator 25 from underlying substrate 32 is thus formed fig5 is a cross section view drawn along a plane iii iii u2032 fig2 parallel to the extension direction of gate 21 perpendicular to the cross section axis of fig4 a to 4f as illustrated in fig5 gate 21 extends above active region 32 and bears on either side of active region 32 on insulation regions 34 gate 21 is insulated from underlying channel 40 by an insulator 22 channel 40 is separated from active region 32 by insulator 25 as illustrated in fig4 f and 5 channel 40 and insulator 25 exhibit according to the present invention constant thicknesses the resulting transistor then no longer exhibits the malfunctions of known devices this is obtained due to the elimination according to the present invention of the forming of the peripheral facets conventionally obtained on growth of thin single crystal layers such that sige layer 38 and si layer 40 on single crystal wafer 30 the present invention enables obtaining one or several thin single crystal semiconductor layers on a substrate with no facets the absence of facets enables keeping for the successive layers a planar surface area equal to the initial surface area of the substrate this enables decreasing the integration surface areas of the guards conventionally intended to compensate for the forming of facets it is.