information in command length control register 400 to determine accesses to either an optimum burst length of 4 bytes or 8 bytes state 1 idle corresponds to the idle state of memory controller state machine 401 when in idle state memory controller 202 is not performing a read or write command memory controller state machine 401 transitions to state 2 rd0 when a read or write cycle is initiated by processor 204 memory controller state machine 401 then transitions through the next three states 3 u2013 5 or rd1 rd2 and rd3 by the time memory controller state machine 401 transitions to state 5 rd3 memory controller 202 has accumulated 4 bytes of data if the optimum burst length l stored in bytes 1 0 402 of command length control register 400 is 4 then memory controller state machine 401 transitions back to the idle state 1 if the optimum burst length l stored in command length control register 400 is 8 then memory controller state machine 401 transitions to state 7 rd4 and through the next three states 8 u2013 10 or rd5 rd6 and rd7 once in state 10 rd7 memory controller 202 which has accumulated 8 bytes of data corresponding to the optimum burst length of 8 transitions back to the idle state.