have been checked against the stored id code the operation proceeds to step 9h in step 9h the cpu 410 supplies a low frequency setting signal to the system clock controller 440 in response to this signal the controller 440 outputs an oscillation start stop signal ssp to the clock generator 420 hence only the low frequency clock generator 42l operates outputting a low frequency clock signal ckl to the timing generator 430 the timing generator 430 generates a low frequency system clock signal from the clock signal ckl and supplies the system clock signal to the cpu 410 therefore the cpu 410 then operates at a low speed in step 9i the cpu 410 outputs a battery saving control signal to the battery saving circuit 11 in order not to supply power to the receiver circuit 10 upon receipt of this control signal the circuit 11 stops supplying power from the battery 12 to the circuit 10 as a result both the radio circuit 2 and the demodulation circuit 3 are rendered in operative as can be understood from fig8 that is the pager receiver is brought into a battery saving condition in which only the cpu 410 performs its function in step 9j the cpu 410 determines whether or not the time set to the timer not shown has elapsed if yes the cpu 410 detects that the pager receiver has just started receiving the next frame in this case the operation returns to step 9b steps 9b to 9o are then executed as has been explained.