doped drift region 11 the connection 9 of the resistive layer 8 is formed by the source contact which as shown in the drawing is also connected to the back gate region 17 via a highly doped p type contact zone the drain contact is formed by the other connection 10 of the resistive layer 8 the transistor comprises a gate 18 of polycrystalline silicon which is separated from the channel in the back gate region by thin gate oxide and which extends beyond the channel and over a part of the thick oxide 6 in this example the oxide layer 6 is obtained by a locos process the dielectric layer 7 extending over the gate 18 is formed by an oxide layer obtained by deposition contact windows are formed in the oxide layer 7 via which contact windows the metal connections 9 and 10 contact respectively the zones 4 17 and 5 in accordance with the invention a number in this example two electroconductive regions 12 and 13 are provided between the connections 9 and 10 and are distributed in such a manner that when a voltage is applied between the connections 9 and 10 for a sufficiently long period of time a non linear potential distribution is obtained in the resistive layer 8 in a stationary state the conductive regions or field plates 12 and 13 can be formed at the same time as the connections 9 and 10 and hence do not require additional process steps the semi insulating resistive layer 8 is provided as a passivating silicon nitride layer which is enriched by silicon to obtain some electric conduction in the layer the thickness of the layer is for example 800 nm a second sub layer of the passivating layer.