always temporarily reversed until a high speed in the other direction can be built up at low speeds however the occurring pulse distortions are smaller so that the sign can be evaluated correctly again when passing through low speeds it can therefore be assumed that memory 7 always contains the correct sign examination of the pulse combination a 39 b 39 shows that while it contains only two of the four possible combinations information regarding the missing signal combinations is available because a 1 state must be located between the numbers 0 and 2 and a 3 state between 2 and 0 as will be described this is evaluated in the evaluation circuit for reconstructing the correct pulse train it is first assumed that the number a 34 b 34 as well as the number c d are both zero so that comparator circuit 6b has a logical 34 1 34 state present which blocks clock pulses via and gate 4 if now the number a 34 b 34 jumps to 2 the deviation from the number c d is 2 and the logical 34 1 34 signal at output terminal 6d disappears so that the clock pulses are passed again counter 5 now also reaches the number 2 after two clock pulses so that comparator output terminal 6b again goes to logic state 34 1 34 and blocks the clock pulses if the number a 34 b 34 jumps to zero again two clock pulses are released which bring the counter 5 likewise to the count 0 the count of counter 5 thus follows with a certain amount of delay the.