the present invention in one embodiment several parallel inputs 400 401 402 403 are provided fig4 depicts a four bit input for each stage of the represented pipeline for each input bit 400 401 402 403 there is a latch 410 generally in one embodiment a clocking sequence is provided for input enablement this allows for latching writing the appropriate input bit sequence 400 401 402 403 at the appropriate time by the correct series of latches 410 this input enablement sequencer 420 operates as the input pointer for the fifo in one embodiment for each stage of the represented pipeline for each output bit 430 431 432 433 there is a latch 410 a clocking sequence is provided for output enablement this allows for outputting reading the appropriate output bit sequence 430 431 432 433 at the appropriate time from the correct series of latches 410 this output enable sequencer 422 operates as the output pointer for the fifo 0019 fig5 provides a chart illustrative of the flow of data through a static fifo which is used as a substitute for a dynamic pipeline of the same parameters as provided for fig1 d 5 w 4 over a span of time under principles of the present invention in one embodiment the fifo 506 a is u2018 initialized u2019 by causing the input pointer 502 a and output pointer 504 a to point to the u2018 0 u2019 position of the queue 506 a in one embodiment over the next four clock ticks 511 512 513 514 the four bit data items x1 x2 x3 x4 are.