voltage of the inverter 25 is set at a low level thus the inverter 25 and nor circuits 23 24 jointly constitute the schmitt circuit fig9 a illustrates the waveforms of signals appearing when the power source voltage v dd sharply rises a broken line a14 represents the rise of a signal denoting the power source voltage v dd a one dot dash line a15 denotes the waveform of a voltage signal at the output point e of the delay circuit 15 a solid line a16 shows the waveform of a voltage signal appearing at the output terminal 22 of the autoclear circuit of fig8 where the switch 12 is closed then a voltage signal a15 appearing at the output point e of the delay circuit 15 rises later than the rise of a signal denoting the source voltage a14 therefore a signal appearing at the output terminal 22 is kept at a high level only while the voltage signal a15 appearing at the output point e of the delay circuit 15 remains at a low level causing a reset signal a16 to be sent forth from the output terminal 22 fig9 b shows the waveform of signals appearing when the source voltage signal v dd rises slowly a broken line a17 represents the waveform of the rising source voltage v dd a one dot dash line a18 shows the waveform of a voltage signal appearing at the output point f of an inverter 25 a solid line a19 indicates the waveform of a voltage signal appearing at the output terminal 22.