these n bit wide words are each allocated to one of a plurality of outgoing bitstreams in the fig4 embodiment 2 bit streams are available bit 1 bit 0 accordingly in a typical application according to fig4 the relationship between the widths of lines 430 r and 354 n would be r 2 u00d7 n proceeding along the bit 0 data path data is then transferred in n bit wide words over line 354 to the output fifo buffer 358 which stores the data it receives as words of width n a clock signal is provided by the fic circuit at its clock output 360 to the output fifo buffer 358 under the control of this clock signal the output fifo buffer 358 transfers data in n bit words to the serializer 368 the serializer receives the data in n bit wide words at a given clock rate and outputs the data at a clock rate n times faster in a one bit wide stream concurrently along the bit 1 data path data is passed out of the fic circuit 340 in n bit wide words buffered in fifo 396 and serialized into a one bit wide output signal by serializer 398 output amplifiers 374 and 400 each amplify respective one bit wide data signals and send the signals out over their respective t lines 288 290 of a media segment 102 coupled to node a 150 at.