the buffer tree such devices can include for example cell type modification insertion of one buffer insertion of several buffers interchange of two grandchildren making a grandchild into a child making a child a grandchild interchanging a child and a grandchild eliminating two inverters removing one buffer removing more than one buffer and removing two inverters application_number US 67847800 A description the purpose of the dynamic buffer and inverter tree optimization procedure is to optimize buffer and inverter trees with the three cost functions remove ramptime violation reduce the path delays and minimize the cell area this procedure can be applied as part of the timing driven resynthesis procedure described in section 2 herein the timing driven resynthesis procedure described herein resynthesizes a chip netlist in order to minimize path delays eliminate ramptime violations and minimize the total cell area it can be applied at different points during the chip design process for example it can be applied after cell placement or after clock buffer insertion the timing driven resynthesis procedure starts with a chip that has a preliminary cell placement some of the cells are declared as fixed a lattice covering the chip area is then created with a typical distance between neighboring lattice points being 15 grids each nonfixed cell is then.