while the first transistor q 1 and the second transistor q 2 are n channel metal oxide semiconductor field effect transistors nmosfet 39 s the first transistor q 1 and the third transistor q 3 the second transistor q 2 and the fourth transistor q 4 form cmos inverters respectively the gates of the first transistor q 1 and the third transistor q 3 are connected to the drains of the second transistor q 2 and the fifth transistor q 5 the gates of the second transistor q 2 and the fourth transistor q 4 are connected to the drains of the first transistor q 1 and the third transistor q 3 the sources of the third transistor q 3 and the fourth transistor q 4 are connected to a power supply vcc the sources of the first transistor q 1 and the second transistor q 2 are connected to the ground vss when data 14 are latched in the sram cell 10 the second transistor q 2 is on the first transistor q 2 is off the memory node n 1 has the voltage vcc the memory node n 2 has the voltage 0 when the first transistor q 1 is off while the second transistor is on it represents that there are data 1 stored in the sram cell 10 the gates of the fifth transistor q 5 and.