sw 3 and sw 4 between the reference voltage vop and the power supply voltage vdd this configuration makes it possible to suppress leakage current from the connection point fb to the connection point vg as well as to hold the connection point fb at the reference voltage vop for a certain period of time thus minimizing the output voltage offset note that the aforementioned embodiment employed a p channel fet as a switching element however an n channel fet can also be used when an n channel fet is used as a switching element the substrate of each of the switching element sw 3 and the switching element sw 4 is supplied with the ground potential vss instead of the power supply voltage vdd during the transition period in which the voltage vdac varies in level furthermore when the voltage vdac varies in level the period the aforementioned predetermined time in which the switching element sw 7 is turned off and the switching element sw 8 is turned on may be the time that is required for the output voltage of the output amplifier or the voltage vdac to finish varying alternatively that period can also be a detected period required for the output voltage of the output amplifier or the voltage vdac to reach the threshold value that is determined corresponding to the voltage to which the output voltage or the voltage vdac changes fig1 shows another embodiment of the present invention the offset cancel output circuit of fig1 is configured to eliminate the switching element sw 3 in the output circuit of fig5 this configuration is the same as that of the circuit shown in fig1 of patent literature 1 in the.