compensate for the properties of the physical connection between the test device and the dut application_number US 49028109 A description in the following referring to fig1 a test array 100 will be described the test array 100 comprises a workstation 101 and a test device 102 the workstation 101 is connected to the test device 102 via a connection 103 further an integrated circuit 104 as a device under test dut is provided the integrated circuit 104 comprises a plurality of pins 105 which are connected via connection elements 106 to the test device 102 in the case of the test array 100 the all active test functions and corresponding test data are stored centrally on the workstation 101 and are provided to the test device 102 using a bus architecture according to a test sequence which is provided solely by the workstation 101 the pins 105 of the integrated circuit 104 are accessed or activated sequentially that is to say one after the other so that the processing time for testing the integrated circuit 104 is relatively long the test device 102 acts simply as a slave and passively carries out the test commands provided by the workstation 101 without influencing or actively controlling the test no test data or test sequences are stored in the test device and all the test intelligence is included in the workstation in the following referring to fig2 a test array 200 according to an exemplary embodiment of the invention will be described the test array 200 comprises a workstation 201 a test device 202 and an integrated circuit 104 as a device under test dut the test device 202 comprises a first interface 203 connected.