28 the high signal turns off transistor q 111 isolating v ccp from the main output node 24 the high signal from node a combines with the high signal from the first inverter 10 at the second nand gate 30 the low signal from the nand gate 30 is changed by the fifth inverter 32 and the high signal from the fifth inverter 32 turns on q 112 grounding any signals that reach the main output node 24 thus the low signal in causes a low signal out as the in signal changes from a low to a high signal the first inverter 10 outputs a low signal and hence the second inverter 12 outputs a high signal the first nand gate 14 receives this high signal as a first input however the new high signal is held up by the delaying element 16 and as a result the third inverter 18 temporarily continues to output a high signal to the second input of the first nand gate 14 receiving two high signals the first nand gate 14 transmits a low signal to the first circuit portion 20 this low signal turns off transistor q 102 further the low signal passes through the fourth.