the clock tree circuit 6 the buffers 17 18 19 and 20 are connected in series in that order an output of the buffer 20 is connected to a clock input c of the read address counter 13 and the clock output terminal 4 the clock output terminal 4 is connected to a clock input c of the logic circuit 7 fig2 is a block diagram for explaining the operation principle and fig3 is a time chart thereof referring to fig2 and 3 the operation principle is described below in a circuit in which two d ffs 31 and 32 are connected in series as shown in fig2 the d ff 32 can confidently latch output data of the d ff 31 in a case where a clock b input to the latter d ff 32 is in advance from a clock a input to the former d ff 31 by a phase sufficiently smaller than one period for example equal to a delay in one stage of the buffer as shown in fig3 the relationship between the d ffs 31 and 32 in fig2 correspond to those between the read address counter 13 and the d ff 16 between the d ffs 16 and 15 between the d ffs 15 and 14 and between the d ff 14 and the write address counter 12 in fig1 and the latter circuit can thus confidently latch the output data of the former one in other words the count value of the read address counter 13 can be confidently transmitted to the write.