foregoing three input signals being anded with the phase 1 pulse an up level output is simultaneously received from each of the flip flops 48 50 and 52 once in every eight phase 1 pulses resulting in the desired output from and circuit 38 when both inputs to exclusive or circuit 40 are at an up level phase a is maintained at a down level at all other times the output of the and circuit is at a down level so that the phase 1 pulse is passed through exclusive or circuit 40 it is noted that the phase b pulse is quite similar to the phase a pulse except for the phase thus the phase b pulse is identical to the phase 2 pulse except that once in every eight bits the phase b pulse is blocked for this reason the phase b pulse is obtainable from exclusive or circuit 46 in a manner similar to the obtaining of the phase a pulse from exclusive or circuit 40 and circuit 44 receives an input from jk flip flops 50 52 and 54 and these three signals are anded with the phase 2 clock input when all four inputs are up and circuit 44 provides an output 0y once in every eight cycles thus once in every eight cycles the exclusive or circuit 46 inhibits the passage of the phase 2 clock pulse causing phase b to remain at a down level for that particular bit position the output of or circuit 36 provides the phase 1 39 clock pulse thus phase 1 39 will be at an up level when either phase 1 or the indicated output of any one.