the two selection circuits 1604 a 1604 b are output by calculating the frequency of the selection of the unit cell by the selection signals at this time each of the plus side selection device 1604 a and the minus side selection device 1604 b operate so that unit cells are selected in order from the smallest frequency of selection in addition a control signal 1621 is input to the conversion table circuit 1602 from the sequential control circuit 1620 in this way by inputting the plus side and minus side of a second digital selection signal fn to separate selection circuits it is possible to independently stabilize an operation for smoothing errors in the case where a plus side cell is selected and an operation for smoothing errors in the case where a minus side cell is selected by this operation it is possible to optimize the length of time for smoothing errors and power consumption an example of a selection circuit 1700 used in one embodiment of the present invention is shown in fig1 a plurality of second digital selection signals fn 1701 from a conversion table circuit is provided and the second digital selection signal fn is input to a selection circuit 1702 3 value selection signals sn 1705 output by the selection circuit is input to a circuit having at least two or more integration circuits configured with a delay element and an adder an output signal 1707 from a first integration circuit 1705 is input to a second integration circuit 1706 and the selection signal sn 1705 is accumulated the usage frequency of a unit cell is represented by the result of this accumulation by inputting an output signal 1708.