2 in the register identified by the instruction fig5 is a block diagram of a computer system including multiple levels of hierarchical memory executing the improved method of fetching instructions and data according to the present invention the computer processing system shown includes a processor unit 500 and an associated memory unit 100 the memory unit 100 holds program data and instructions intended for execution on the processor unit 500 the memory unit consists of one or more levels of memory hierarchy 100 1 100 2 100 i 100 m where m represents the highest level i e main storage the smallest in terms of size and the fastest in terms of access time memory level is typically referred to as cache and is incorporated on processor 500 at the lowest level level 1 100 1 the successive memory levels are each larger and slower than the preceding lower memory level in other words the memory at some level say i is smaller and faster than that at the next level i 1 although any item instruction or data is available at the highest main storage level level m frequently used instruction and data portions of the memory unit are typically kept in an instruction cache unit 101 1 and a data cache unit 103 1 respectively alternatively the instruction and data caches can be merged into a single unified cache the higher level memory units may also be split into instruction and data units or kept unified as is conventional the instructions data stored in the instruction cache 101 1 and data cache 103 1 respectively are divided into lines or blocks an instruction fetch unit 104 fetches one.