of their counterparts in the 39 623 patent when the non op signal from ballast lamp control and half bridge driver circuitry 60 is high pfc circuitry 130 is generally disabled so that the pfc control circuitry does not operate during fault mode and under voltage lockout mode when the non op signal goes low at the beginning of preheat mode circuitry 130 is generally enabled and begins to boost voltage by providing signals through the pfc pin in a manner that can be understood from the 39 614 patent because circuitry 130 has been enabled however the preheat mode begins with the dc bus at a non operating voltage that is lower than the voltage at which the lamp ignites the signals through the pfc pin bring the dc bus voltage to its nominal running level only after the first few initial switching cycles of the half bridge driver section during the initial half bridge switching the voltage appearing across the capacitance in the load circuit and also across the lamp is therefore too low to ignite the lamp the dc bus rises to its nominal running level while circuitry 60 is in preheat mode and thereafter is regulated and held constant by circuitry 130 the non op mode signal is received by nor gate 140 or gate 142 the r 2 reset lead of latches 144 and 146 and the r.