120 b than the vertical routing channels 134 shown in fig2 this allows the horizontal routing channels 132 to provide more interconnectivity both between the udbs 120 a and 120 b in udb pair 122 and also provides more interconnectivity between different udb pairs 122 in the same rows of interconnect matrix 130 thus the interconnect matrix 130 in fig1 and 2 more effectively uses chip space by providing more traces and connectivity for the shorter higher performance horizontal routing channels 132 than the relatively longer lower performance vertical routing channels 134 fig4 shows switching elements 145 that connect the different i o signals 127 and 128 for the udbs 120 a and 120 b in fig3 to the horizontal routing channel 132 in this example an output 127 a from the upper udb 120 a in the udb pair 122 drives an input 128 a in the lower udb 120 b a buffer 138 is connected to the udb output 127 a and a buffer 140 is connected to the udb input 128 a the output 127 a and input 128 a are connected to vertical wires 146 and 148 respectively that intersect the horizontal routing channel wire 132 a with a regular pattern at the switch points ram bits operate ram cells 136 and 138 which in turn control complementary metal oxide semi conductor cmos transmission gate switches 142 and 144 respectively the switches 142 and 144 when activated connect the udb output 127 a and the udb input 128 a to horizontal routing channel wire 132 a the ram cells 136 and 137 are programmably selectable by.