at the output terminals of the respective buffer inverters 206 208 are passed through respective pmos pass transistors 210 212 to provide voltages to the drain terminals of the pmos transistors 210 212 which are required during read program and erase modes of operation for a selected word line in the read mode of operation the x decoder voltage at the drain terminal of a pmos pass transistor is 5 volts and the gate terminals of a pmos pass transistor is at 2 volts in the program mode the x decoder voltage at the drain terminal of a pmos pass transistor is also 5 volts and the gate terminals of the pmos pass transistor is at 12 volts for a selected word line in the erase mode of operation the x decoder voltage at the drain terminal of a selected pmos pass transistor is 0 volts and the gate terminals of a pmos pass transistor is at 0 volts which turns off the pmos pass transistor this permits 12 volts to be on the word lines of a respective selected word line 220 222 for an unselected word line in the read mode the x decoder voltage at the drain terminal of a pmos pass transistor is 0 volts and the gate terminals is at 2 volts in the program mode.