in the meantime according to the present invention the number of wiring layers and the thicknesses of the respective wiring layers are common to the ip core ip 3 shown in fig1 and 20 and the ip core ip 4 shown in fig2 and 24 accordingly as shown in for example fig2 and 28 even if the ip core ip 3 and the ip core ip 4 are mounted on one semiconductor chip to constitute one system the layouts of the respective ip cores can be utilized as they are due to this design efficiency can be enhanced and semiconductor device development period can be thereby shortened 0093 fig2 shows the relationship between the thicknesses of the respective wiring layers of the semiconductor device according to the present invention and those of the respective wiring layers of the semiconductor device in the reference example it is assumed for example that the ip core is constituted out of m where m is a natural number wiring layers and a semiconductor device using this ip core is constituted out of n where n is a natural number satisfying n gt m wiring layers in this case the thick wiring layer is always formed on the lowermost thick wiring layer in the reference example according to the present invention by contrast a thin wiring layer can be formed on the lowermost thick wiring layer as required 0095 fig3 shows an example in which four ip cores are mounted on.