h level output of the frequency dividing counter 15 and the output q falls to l level since the output q of d ff 14 is imparted to the reset input terminal r of the counter 16 the counter 16 starts to count the clock pulses clk after m clock pulses have entered the frequency dividing counter 15 this is a contrivance for making the number of bits of the counter not great the counter 16 produces a counter output which increases as shown at the digital step in fig2 the height of this digital step represents the counter output t m in fig2 is a period of time corresponding to m pulses clk the count output of this counter 16 is latched by the latch circuit 17 at the rising of the output pulse of mm 13 the time when the counter 16 is reset is a little later than the time when the output pulse of mm 13 rises and therefore the latch circuit 17 puts out to the microcomputer 18 a count value corresponding to the number of clock pulses clk generated during the period of time from the rising of the output pulse of mm 13 till the next rising of the.