l is also fed to delay circuit 46 so that when the load signal s l becomes 34 0 34 the output signal s dh of delay circuit 46 is forced to a 34 0 34 state from its 34 1 34 state a hold signal generator 90 is further provided which consists of a flip flop 91 a monostable multivibrator 92 a nand circuit 3 and an inverter 94 an output signal s r from the nand circuit 93 is supplied to a reset terminal of the flip flop 91 through the inverter 94 in which the output signal s r is inverted to form signal s r if signal s r is 34 1 34 when the window pulse signal s w from pulse signal generator 50 is fed to flip flop 91 at its t terminal flip flop 91 is triggered by the window pulse s w at its negative going edge and hence an output s f of flip flop 91 becomes 34 0 34 on the other hand when flip flop 91 is triggered by the negative going edge of the window pulse s w while the signal s r is 34 0 34 the output s f of flip flop 91 becomes 34 1 34 the monostable multivibrator 92 is triggered by the pulse s ok from detecting circuit.