transferred to the main integrator 501 the voltage at node v cap of the main integrator 501 is then shifted up by an amount proportional to the t delay pulse duration logic 504 delays v ref switching as described below and extracts the two t delay pulses per period fig5 a and 5b are comparative illustrations of the capacitor voltage and comparator output as a function of time for the circuit of fig5 in fig5 a v ref switching and current switching using switches sw 1 sw 2 sw 4 and sw 5 are synchronous transitions in capacitor voltage v cap and v ref input occur concurrently to cancel comparator propagation delay v ref switching is delayed relative to transitions in the capacitor voltage by at least 2 t delay fig6 is a set of timing diagrams for simulated operation of the circuit of fig5 plot 610 illustrates the output of comparator 500 including the 2 t delay pulses plot 612 illustrates both the capacitor voltage v cap generally sawtooth waveform and v ref switching square waveform at the end of the t delay pulse the charge accumulated on the duplicate integrator 502 is transferred to the main integrator 501 with the result that the capacitor voltage v cap is shifted by an amount proportional to t delay plot 614 illustrates voltage v cap2 on capacitor c 2 of.