163 each receiving at least one input signal 34 0 34 both release the output signal 34 0 34 in this manner the signals stored in the flip flops 150 155 are converted from 1 1 1 1 1 0 to 0 0 1 1 1 0 thus achieving the conversion from 5 bits to 3 bits similarly a black run of 7 bits is converted into a black run of 6 bits by the output signal 34 0 34 from the and gate 162 and a black run of 8 bits is converted into a black run of 6 bits by the output signals 34 0 34 from the and gates 162 and 164 also a black run of 10 bits is converted into a black run of 9 bits by the signal 34 0 34 from the and gate 162 and a black run of 11 bits is converted into a black run of 9 bits by the signals 34 0 34 from the and gates 162 and 165 in the foregoing procedures the input port g2 of the decoder 168 always receives a signal 34 0 34 for a black run of 16 bits or more upon counting 15 the 4 bit counter 167 supplied a signal 34 1 34 from the output port cr to the input port j of the flip flop 169 upon counting of 16 a signal 34 1 34 is supplied to the input port j of the flip flop 169 the output port q thereof releases a signal 34 1 34 whereby the input ports g1 and g2 of the decoder 168 both receive the signals 34 1 34 thereby releasing the signals 34 1 34 from.