main memory u201c ram u201d 10 e also interfaces to computer bus 10 h to provide cpu 10 a with access to memory storage when executing stored computer executable process steps from storage media 10 g cpu 10 a stores and executes the process steps out of ram 10 e read only memory u201c rom u201d 10 d is provided to store invariant instruction sequences such as start up instruction sequences or basic input output operating system bios sequences network interface 10 b allows computing system 10 to connect for example using tcp ip link 50 a fig1 a with other systems via a network it is noteworthy that the foregoing systems are merely to illustrate the adaptive aspects of the resent invention the architecture and block diagrams may have fewer or more components to execute the process steps described below before describing the adaptive aspects of the present invention the undesirable propagation of x 39 s is described with respect to fig1 c after simulation is started logic values are propagated throughout the asic design flip flop 102 samples input data 101 at the transition of the input clock 104 and at the assertion of the input write enable 103 if the output 105 of the flip flop.