operational functions using the address but which is independent of bit slicing fig3 shows as an example the arrangement of the frame buffer memory which uses part of the address signals for specifying operational functions symbol dj denotes a 1 bit signal in the 16 bit data signals to the graphic display data processor a23 a1 are address signals to the data processor we is the write control signal to the data processor fs is the data setting control signal for the operational function specifying register 3 and write mask register 26 doj is a bit of data read out of the memory device 2 dij is a bit of data produced by the operation unit 1 and wj is the write control signal to the memory device 2 fig3 shows as an example the arrangement of the write mask register which includes a write mask data register 61 and a gate 62 for disabling the write control signal we fig3 shows the arrangement of the frame buffer constructed by using the memory circuit shown in fig3 the figure shows a 4 bit arrangement for clarifying the connection to each memory circuit fig3 shows the memory circuit of this embodiment applied to a graphic display system with the intention of explaining the setting of the operation code reference number 20 denotes a data processor and 23 denotes a.