device to have reduced isolation edge leakage current four different types of pmos transistors were fabricated in one experiment the characteristics of each type of pmos transistor employed in the experiment are listed in table 1 all of the pmos transistors in the experiment received a two step buried channel implant in table 1 the u201c blocked isolation edge u201d column indicates whether the pmos transistor received a second buried channel implant i e bci 2 where the isolation edge is blocked e g see fig1 b as shown in table 1 type 1 and type 3 pmos transistors did not receive a second buried channel implant where the isolation edge is blocked the type 2 and type 4 pmos transistors received a second buried channel implant with blocked isolation edge for the type 2 and type 4 pmos transistors the distance between an edge of an opening of the blocking implant mask and an edge of the isolation trench e g see dimension d 1202 of fig1 is about 0 28 u03bcm the u201c width length u201d column shows the width of the active region of the pmos transistor e g see dimension d 704 of fig1 and the length of its gate e g see dimension d 1362 of fig1 for example a type 1 pmos transistor did not receive a buried channel implant with blocked isolation edge has an active region width of 25 u03bcm and has a gate.