pulse bd is detected by the trailing edge detecting circuit 8a the counters 40 and 50 are then stopped the counted value is reset and the counting by the pulse bml is restarted in this condition the counter 50 is stopped and reset before its counted value bdsycnt reaches 34 m 34 which is smaller than 34 n 34 so that the count up output mc is not generated by the counter 50 the leading edge signal bdh is transmitted to the flip flop 51 and the delay circuit 60 the leading edge signal bdh transmitted to the delay circuit 60 is delayed by time td and the readout enable signal reade is output therefrom the address counter 61 is actuated by the readout enable signal reade and the address signal from the address counter 61 is input to the video data memory 70 the video data memory 70 then outputs one line of parallel video data d 0 to d n and the video data d 0 to d n are converted to a serial video signal ds at the video buffer 71 the video signal ds is transmitted to the aom 11 through the or circuit 72 to operate the aom 11 and carry out one line of modularion in this way.