create the processor clock signal pclk 230 from the first system clock clkin 215 pclkin 240 is used as the feedback clock signal for the pll 225 thus the system clock 210 may provide two clock signals to each of the processor 110 a and the bridge 130 in one embodiment rstclk 220 has a clock rate of 50 mhz in this embodiment clkin 215 has a clock rate 100 mhz pll 225 of processor 110 a operates to generate a processor clock 230 with a clock rate of 500 mez the division element divides the processor clock 230 by 5 to generate pclkout 235 at 100 mhz pclkin 240 also has a clock rate of 100 mhz it is noted that bridge 130 may operate according to the 50 mhz rstclk 220 the 100 mhz clock clkin 215 or may implement a pll such as pll 225 of processor 110 a to generate for example an internal clock at almost any frequency turning now to fig2 b a block diagram of an alternative embodiment of the system clocking of fig2 a is shown in this embodiment the system clock 210 provides a single clock signal over more than one clock line as shown system clock 210 b outputs a system clock 215 that is routed as both clkin 215 and rstclk 220 b thus in one embodiment both rstclk 220 b and clkin 215 have a clock rate of 100 mhz it is noted that the ratio between clkin 215 and rstclk 220 is preferably an integer greater than or equal to one thus the ratio between clkin 215 and rstclk 220 may be 1 2 3 etc it is also noted that in a preferred embodiment.