embedded array blocks of logic 34 eabs 34 as well as multiple logic array blocks 34 labs 34 each lab includes multiple logic elements 34 les 34 which are selectively interconnected to one another via local interconnect lines in turn each of the labs is selectively interconnected to one or more other labs via row or global horizontal 34 gh 34 interconnect lines and column or global vertical 34 gv 34 interconnect lines in accordance with well known techniques such interconnections are programmed using programmable switches e g pass transistors at intersections of the les and their associated local interconnect lines intersections of local interconnect lines and row interconnect lines intersections of local interconnect lines and column interconnect lines and intersections of row and column interconnect lines the new technique models interconnect wires with arbitrary load distributions as an electrical circuit with a flexible structure of varying size and configuration a regular ladder network of resistors and capacitors models the interconnect wire itself the wire model but arbitrary load models can be attached to the wire model at any point to simulate the positions of various loads on the interconnect wire the wire model is shown in fig2 the load models labeled z l in fig2 are shown in more detail in fig3 each load model z l represents the interconnections matrix up to a signal buffer the interconnect model shown in fig2 consists of l load sections each with a c row and a z l and two termination sections c pad when modeling a gh line each load section corresponds to one lab the signal source a step function is connected to.