the circuit schematic diagram of fig3 which gives a preferred circuit design for incorporation in a control system for a fluidically driven shear mechanism in accordance with u s pat no 4 467 431 this circuit supercedes portions of the set up circuit 18 of fig8 and 9 from the 39 431 patent as described below and carries out the former functions of these circuits of initializing the start delay time and adjusting such time during operation of the shears fig2 shows a modified start delay timer circuit which is designed to interface with the circuit of fig3 as further described below while the mechanism is not running the run signal is high for the data terminal of flip flop u1 this signal goes low once shear operation commences the start signals comprise conditioned high pulses obtained while the feeder is running at the cycling rate of the feeder circuits for generating both signals are disclosed in u s pat no 4 467 431 the set up sequence operates as follows a start pulse sets ff u1 and q goes low which acts on nand gate u8 via differentiator c2 r2 to create a preset signal for the start delay register 312 see fig2 the low state of u1 39 s q output holds the ce count enable output low via u9 and u10 the up dn output of nand gate u11 is held high by the same signal q of ff u1 which causes the start delay register up down counter 312 fig2 to count up the up down counter 312 fig2 provides a low shear response est output only during a predetermined variable time period.