line sbi is interposed between the activation signal line sseni and the main bit line mb and a series circuit of an n channel mos transistor q t2 which is driven by the sub sense amplifier selection signal tgi and an n channel mos transistor q s2 whose gate is connected to the sub bit line sbi is interposed between the activation signal line sseni and the main bit line mb the sub sense amplifier 2i is composed of these four transistors q t1 q t2 q s1 and q s2 next the operation of the circuit of this embodiment will be explained with reference to fig6 in the initial stage at a time point t 1 the mos transistors q y are cut off to separate i o buses i o i o from the main bit line pair mb mb since the pre charge balance signal pdl the sub bit line selection signal such as ssi for each sub bit line and the sub sense amplifier selection signal tgi are at the high level at this time the mos transistors q p q b q t1 q t2 q 11 and q 12 are all turned on and each sub bit line pair sbi sbi is at the predetermined pre charge level all the activation signals sseni msep and msen too are at the high level at this time the mos transistors q s1 q s2.