see fig4 b and 4 c in order to produce a second layer l 2 undoped polysilicon is deposited to a thickness of approximately 100 nm see fig4 a b c with the aid of a third mask not illustrated which is in strip form in the first region of the substrate 1 and whose strips run parallel to the y axis y and cover the depressions v the second layer l 2 is etched using hbr for example in a highly selective manner with respect to sio 2 the ono layer ono acting as an etching stop in this case control gate electrodes gk are produced from the second layer l 2 which electrodes form word lines running parallel to the y axis y with the aid of the third mask the ono layer ono is patterned using e g hf see fig5 a in this case second dielectrics d 2 are produced from the ono layer ono see fig5 d a gate electrode ga 1 of the transistor of the periphery and a gate electrode ga 2 of the high voltage transistor of the periphery are likewise produced with the aid of the third mask see fig5 b and c in order to reduce inter alia the risk of short circuits between word lines and the substrate 1 a so called post oxide p is grown by thermal oxidation see fig5 a 5 b 5 c first parts ldd having a depth of approximately 200 nm of source drain regions s d of the transistors of the memory cells first parts ldd 1 having a depth of approximately 100 nm of source drain regions s.