the modulation signal input 12 in this way the q output 26 o of the first d elay flipflop unit 26 supplies the first modulation signal m 1 while the q output 26 o follows the signal of the d input 26 m parallel thereto the control stage 10 comprises a second delay unit 34 which is connected to the output 32 o of the second logic gate circuit 32 and delays the second clock signal c 2 by a second time interval u03b4t 2 fig1 the first time interval u03b4t 1 and the second time interval u03b4t 2 have approximately equal temporal lengths fig2 while the first temporal delays u03b4t 1 generated in the first delay unit 24 and the second temporal delays u03b4t 2 generated in the second delay unit 34 can be built up inter alia with gate delay times this second delay unit 34 is connected to a second d elay flipflop unit 36 whose clock input 36 c is connected to the output 34 o of the second delay unit 34 and whose d input 36 m is connected to the modulation signal input 12 in this way the q output 36 o of the second d elay flipflop unit 36 supplies the second modulation signal m 2 in which the q output 36 o follows the signal of the d input 36 m the second modulation signal m 2 is temporally shifted with respect to the first modulation signal.