a 0 13 u03bcm process as shown in fig5 during the read out period output data signals d and d settles at its final signal values for those eeprom cells with low threshold voltage i e high electrical conductance within several nanoseconds see waveforms 501 in fig5 fig6 shows circuit schematic for a nand type flash eeprom array 600 in accordance with one embodiment of the present invention as shown in fig6 flash eeprom array 600 includes an array of eeprom cells selected by word lines each word line activating a row of eeprom cells at a time the eeprom cells are also organized in columns as memory strings with each memory string including a number of serially connected eeprom cells served by one of local bit lines 602 1 to 602 n each selected eeprom cell controls the discharge of the corresponding one of local bit lines 602 1 to 602 n to ground through nvm cells in its memory string the unselected eeprom cells are each biased to a high voltage to pass the bit line voltage and the ground voltage respectively to the drain terminal and the source terminal of the selected eeprom cell therefore if the selected eeprom is high conductance i e low threshold voltage that eeprom cell discharges its associated bit line conversely if the selected eeprom is low conductance i e high threshold voltage that eeprom cell does not discharge its associated bit line switch structure 601 connects one of the local bit lines 601 1 to 601 n to a global bit line 603 which is read by readout circuit 620 readout circuit 620 operates in substantially the same manner as read out circuit 200 discussed above fig7 shows circuit schematic for a nor type rom array 700.