circuit determines the minimum euclidean distance for a single symbol without decoding the symbol a delay circuit is placed in series with the quick decision circuit to compensate for the traceback delay in the viterbi decoder if the difference in the output signals of viterbi decoder and the quick decision circuit is greater than a predetermined threshold the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter a synchronization loss detector may also be used to prevent the phase error signal from updating the phase lock loop filter if synchronization loss is detected application_number US 10742202 A description with reference to the drawings like numerals represent like components throughout the several drawings fig1 a depicts a typical simple block diagram of a prior art phase lock loop a received signal 9 comprising carrier and data is input into the phase differential detector 10 the phase differential detector determines the difference in frequency between the received signal 9 and the vco output signal 31 and produces therefrom a phase error signal 11 which is input to the phase loop filter 20 the phase loop filter produces a control signal 21 which is input to the vco 30 the vco produces the vco output signal 31 the frequency of which is determined by the vco as a function of some parameter of the control signal 21 typically the voltage level of the control signal with reference to fig1 b a typical prior art phase lock loop for a receiver in a communication system is shown in block diagram form fig1 b is the same as fig1 a with the addition of the components in block 100 a received signal 109 comprising carrier and data.