u12 are connected to the respective inputs of a three input nand gate u23 the output of u23 is connected to the data strobe input pin 11 of latch u8 the oe pin 1 of latch u5 is connected to ground potential the output of u23 is further connected to the input of inverter u15 the output of inverter u15 is connected to the clock input of a flip flop u7 the data input and the set input of flip flop u7 are connected to the 5 volt supply the inverted q output of flip flop u7 is connected to the interrupt line int 1 pin 13 of microprocessor u3 a second interrupt pin 12 is unused and is connected to the 5 volt supply the reset input pin 1 of flip flop u7 is connected to an output of microprocessor u3 on pin 14 the system reset signal on pin 21 of connectors u18 and u12 is connected through inverter u1 to the reset input of microprocessor u3 on pin 9 the power source for the spelling check module is provided by the power available on the connectors 18 and 12 specifically a 5 volt source is provided on pin 1 and a.