using for example polycrystal silicon continuing on as shown in fig4 d the gate electrode film 23 a is patterned and removed by etching to form a transistor gate electrode film 23 b and a mos transistor comprising a transistor source drain 24 an interlayer insulating film 25 a contact hole 26 and metal wiring 27 is formed by the following well known technique a fourth embodiment of the present invention being the third embodiment applied to an eeprom cell will now be described first of all as shown in fig5 a an element separation film is formed on a silicon semiconductor substrate 28 as required and a gate insulation film 29 is formed to a thickness of 200 700 u00e5 by for example thermal oxidation of the silicon semiconductor substrate after that a tunnel drain 30 constituting a drain section of a cell transistor of the eeprom cell is formed by for example an ion injection method a tunnel window section is formed using a well known technique and then a tunnel insulation film 31 is formed to a thickness of 15 120 u00e5 by for example thermal oxidation next as shown in fig5 b nitriding is carried out for the gate insulation film at the same time as for the tunnel insulating film as a result of this processing a boundary level trap and unbonded crystal atoms of the boundary of the tunnel insulation film and the gate insulation film are filled with nitrogen and the resistance to overwriting resistance to hot electrons and reliability of each of the insulation films is improved this process is carried out using rta rapid thermal annealing such as ramp annealing.