516 and a second counter adder 520 the first counter adder 516 handles 32 bit transfers and subtracts the number of bytes transferred in one data phase four bytes from the number of bytes remaining to be transferred given by rem size the second counter adder 520 handles 64 bit transfers and subtracts the number of bytes transferred in one data phase of a 64 bit transfer eight bytes from the number of bytes remaining to be transferred given by rem size which adder output represents the remaining bytes to be transferred next state rem size is selected by counter multiplexer 504 the counter multiplexer output is based on whether a 32 bit transfer or a 64 bit transfer is occurring as specified by signal xfr 64 which is asserted in a 64 bit transfer and deasserted in 32 bit transfers the output signal rem size is input into the dual adder circuits 300 and 400 in the event a disconnect makes it necessary to restart the circuits fig6 is a state machine diagram 600 of a supporting circuit which supports the adder and counter circuits shown in fig4 6 the supporting circuit outputs which are input into the dual adder and counter circuits 300 400 500 are shown in boxes the values listed in the boxes are signals which are asserted inputs into the supporting circuit which result in different actions taken by the supporting circuit are shown in diamonds in the address phase 604 start sel a and b mux ctrl are asserted 608 until the address phase is completed 612 once the address phase is completed and through the transfer of the first phase of data 616 start.