as a chip 10 is shown incorporated into a digital processing apparatus such as a computer 12 the chip 10 is made in accordance with the below disclosure now referring to fig2 and 3 as indicated at block 14 in fig2 and as shown in fig3 prior to ion implantation areas 16 sought to be masked from ion implantation are covered with respective photoresist mask regions 18 in accordance with photoresist deposition processes known in the art the areas 16 sought to be masked can be e g transistor gates implantation regions 20 which can be portions of a semiconductor substrate are established between adjacent areas 16 sought to be masked after ion implantation the implantation regions 20 can establish e g transistor source and drain regions it is to be understood however that the present principles apply to masking selected areas from high aspect ratio ion implantation in general as shown in fig3 the mask regions 1 8 are rectangular in cross section with each mask region 18 defining square left and right top shoulders 22 24 it is the object of the present invention to alter the top shoulders 22 24 of the mask regions 18 to facilitate high aspect ratio ion implantation accordingly proceeding to block 26 in fig2 the top shoulders 22 24 of the mask regions 18 are gently shaped preferably by directing plasma etchant represented by arrows 28.