insulator wafers 602 and 610 includes three layers a u201c device u201d layer of silicon a buried oxide u201c box u201d layer of silicon dioxide and a u201c substrate u201d or u201c handle u201d layer of silicon in wafer 602 those layers are layer 608 device layer layer 606 box layer and layer 604 handle layer in wafer 610 those layers are layer 616 device layer layer 614 box layer and layer 612 handle layer typically the device layer is single crystal silicon about 10 2000 nanometers in thickness the box layer is sio 2 about 0 5 to 4 microns in thickness and the handle layer is single crystal silicon gt 250 microns in thickness as discussed later in further detail in some embodiments layer 608 of wafer 602 comprises high resistivity silicon that is doped appropriately during processing as depicted in fig6 b a portion of device layer 608 of wafer 602 is patterned to form micro platform 626 the portion of layer 606 immediately surrounding micro platform 626 is patterned to create structures 630 referred to herein as u201c nanowires u201d which will ultimately function as electrically conductive wires for conducting electrical signals to and from micro platform 626 they are referred to as u201c nanowires u201d because at least the controlled dimension thereof is less than 1 micron such as the width of nanowire 630 the portion of handle.