layers other subsequently deposited high tensile stress layers and cracks that result from other post bpsg deposition high temperature processes application_number US 42150899 A description the present invention is method for capping with a high compressive stress oxide layer a re flowed bpsg inter layer dielectric gapfill deposited on a topographic silicon substrate so that subsequent high temperature processing such as the formation of a low pressure silicon nitride lp sin layer annealing deposition of other high tensile stress layers or rapid thermal oxidations rto will not cause the formation of cracks referring now to fig1 fig2 fig3 and fig4 there is shown a series of schematic cross sectional diagrams illustrating the results of forming two successive topographic layers such as might occur in a ulsi fabrication using the method of self aligned contacts sac and not using the methods of the present invention fig1 shows a silicon substrate 10 over which has been fabricated a topology consisting of polysilicon structures 12 and metal structures 11 separated by narrow spaces 13 a typical such fabrication is composed of structures whose heights are between 3000 angstroms and 5000 angstroms whose widths are between 1500 angstroms and 3000 angstroms and which are separated by spaces of between 1500 angstroms and 3000 angstroms fig2 shows the topographic substrate of fig1 over which a bpsg dielectric gapfill layer 23 has been deposited re flowed and smoothed by cmp to a thickness of between 4000 angstroms and 8000 angstroms the diagram depicts the excellent gapfill and smooth re flow qualities of bpsg for complex topographies and small dimensions fig3.