representing the same numerical value e g constant but in different architected states i e binary and hex located in storage as addressed by the second operand including a combination of a base address according to a value located in a register identified b 2 and an offset specified by d 2 being placed in the first operand location r 1 which identifies a floating point register 206 in accordance with an embodiment of the present invention the first of the pair is chosen if the current fp mode is hfp and the second is chosen if the current mode is bfp the mode being indicated by the fp mode bit in psw register 202 more particularly in this implementation the first of the pair of storage operands is located at address a and the second at a 8 where a is the second operand address designated by the instruction the operation is performed without inspecting the contents of the second operand no arithmetic exceptions are recognized access exceptions may or may not be recognized for the storage location of the operand that is not selected it may be appreciated therefore that the instruction load modal constant simplifies writing mode independent programs it selects one of a pair of storage operands depending on whether the fp mode is hfp or bfp thus if the first of the pair is a constant in the hfp format and the second is the same number in the bfp format the instruction will load the value appropriate for the current mode so.