by the prefetch counter 11 is returned to the loop beginning address in addition in this prefetch a bite fetch and a word fetch are determined in dependence upon a value of the loop end register lsb step s3 and if lsb 0 the bus interface unit 2 abandons one bite from a prefetch q step s4 after the prefetch of this loop end address when the instruction execution step arrives at the loop end address in short the program counter 6 coincides with the loop end address register 8 in contents to activate an output of the and array 9 step s5 the present instruction is finished by the reset logic 10 and then the program counter 6 is reset at the contents of the loop beginning address register 7 step s6 the program counter 6 is also reset at the contents of the loop beginning address register 7 similarly by the execution of the continue instruction furthermore the execution of the break instruction resets the program counter 6 at the contents of the loop end address register 8 whereby achieving a high speed loop processing in which the instruction execution and the prefetch are carried out along the loop in a hardware like manner please pay attention to that the program counter always indicates a instruction address immediately after a instruction address which is being executed in the above described operation furthermore in this preferred embodiment the expression of the algorithm shown in table 1 is expressed in table 4 table 4______________________________________ centigrade fahrnheit temperaturecorrespondence table printing programlower 0 are assumed to be stored in memoryupper 300 or register and initializedstep 20 fahr is assumed to be stored in memory mov fahr lowerwhile loop endcmp fahr upperjb endmain portion of centigrade fahrenheit conversionprogram written.