example of the present invention the first conductive layer 104 is approximately 1000 u00e5 furthermore a patterned photoresist layer 112 is formed on the first conductive layer 104 subsequently the first conductive layer 104 is etched and then the layer of photoresist 112 is removed as shown in fig4 h next as shown in fig4 i and 4j a second dielectric layer 105 is formed on the patterned first conductive layer 104 and a second conductive layer 106 is formed on the second dielectric layer 105 the second conductive layer 106 forms the control gates of the memory cells which may comprise poly silicon and be approximately 1350 1550 u00e5 thick the second dielectric layer 105 may comprise silicon oxide or oxide nitride oxide ono layer and have a thickness between 125 to 155 u00e5 according to an example of the present invention the thickness of the second dielectric layer 105 and the second conductive layer 106 are approximately 140 and 1500 u00e5 respectively following which a third dielectric layer 107 is formed over the second conductive layer 106 the thickness of the third dielectric layer 107 may comprise silicon oxide and be approximately 2000 to 2500 u00e5 thick according to an.