signal from the clock generator circuit 170 fig4 shows a detail configuration of another embodiment of the logic circuit 142 of fig1 in accordance with embodiments of the present invention more specifically in one embodiment the logic circuit 142 comprises a fast logic circuit 142 a a slow logic circuit 142 b a mux circuit 142 c and a mux circuit 142 d which are electrically coupled together as shown it should be noted that the mux circuits 142 c and 142 d receive control signals not shown from the controller circuit 160 in one embodiment the fast logic circuit 142 a and the slow logic circuit 142 b perform the same function but the fast logic circuit 142 a is faster than the slow logic circuit 142 b in performing the function however the fast logic circuit 142 a consumes more energy than the slow logic circuit 142 b in one embodiment the other logic circuits of the digital system 100 have similar structure as the logic circuit 142 of fig4 in one embodiment in each particular clock cycle one of the fast logic circuit 142 a and the slow logic circuit 142 b is selected by the controller circuit 160 to obtain data from the registers 111 through 116 of register bank 110 via the mux circuit 142 c processes the obtained data and sends the processed data to the registers 121 and 122 of register bank 120 via the mux circuit 142 d the non selected circuit of the fast logic circuit 142 a and the slow logic circuit 142 b does not operate does not consume energy in the embodiments described above with reference to fig1 and 4 in the first clock cycle the controller circuit 160 can select the fast logic circuit 142.