should be provided for multi phase devices such that one phase of the clock must be kept high for a single phase and dc devices this consideration is not necessary the respective tracks can be multiplexed such that in a two phase device the data rate is twice the clock frequency to this end logic circuitry for the organization of fig4 is illustrated in fig1 a together with a truth table in fig1 b in this logic circuitry multiplexing of data is used and refresh enable re control is provided so that burst mode refreshing can be performed although a two phase structure is used single phase three phase or four phase structures can easily be implemented in a similar manner in fig1 a data is stored in shift registers 130a and 130b which are driven by two phase clock signals u03c6 1 and u03c6 2 the respective registers are provided with refresh amplifiers 131a and 131b the data is returned from the refresh amplifiers to write gates 135 a and 135b via or gate 134 and gate 133 and or gate 132 when there is no write signal presented to and gate 144 data may be entered into either of the shift registers via data in and gate 143 and or gate 134 when a write signal is presented to and gate 144 this action can only occur when a chip enable signal is applied to and.