ssram 30 an auto sequence processor and ram asp 32 a program operation contoller poc 34 a merged sequencing switch mss 36 and a fail detection network fdn 38 the tsp 28 is a ttl central processing unit cpu which is coupled with working memory such as a 2048 word ram the stored sequence ram 30 is a 240 u00d7 2048 bit ram the asp 32 is a psuedo random digital signal synthesizer capable of generating dynamic test sequences under either internal or external clock control one such digital signal synthesizer is incorporated into the model 3010 circuit board tester manufactured and sold by the assignee of the present invention the poc 34 and the mss 36 form together a multi channel time division data multiplexer the mss 36 is a digitally implemented equivalent of 4 240 gauged 3 position switches which operate under control of the poc 34 the poc 34 includes a 4 u00d7 2 u00d7 2048 bit ram subject to external override control the fdn 38 may be a multiple channel input go no go test network a preferred embodiment is a parallel cyclic redundancy check network such as a parallel crc generator used to detect errors in data transmission systems one such detecting network is described in an article by k m helness computer design march 1974 p 91 the off line controller 16 comprises an off line cpu 40 mass storage 42 such as a floppy disk and a manual input unit 44 including a.