of which are connected in series fig4 shows the example of the connection formed by one 7 bits linear feedback shift register lfsr and one 1 bit flip flop dff 6 for the structure of the first address generator it is connected by several linear feedback shift registers lfsr 14 in series to generate the address signals required by various memory the number of linear feedback shift registers 14 is determined by the number of addresses of the memory to be tested i e if there are n memories with different sizes and the address is arranged in the increasing order of ram 1 r 1 ram 2 r 2 ram 3 r 3 ramn rn the number of the relative addresses are k 1 k 2 k 3 k_ kn therefore the first set of linear feedback shift register 15 of the address generator is used to generate the address k 1 the second set of linear feedback shift register 16 is used to generate the address k 2 u2212 k 1 the third set of linear feedback shift register is used to generate the address k 3 u2212 k 2 and so on when the data of the first set of linear feedback shift register completes a cycle the output signal ram 1 _end r 1 will be logic u201c.