2 domain u2014 a clock derived from clk through a predetermined delay element the potential propagation delay associated with application of clk 302 to ck 212 input of memory component 220 is represented by accumulated phase variance 308 accumulated phase variance 308 represents the accumulated effect of various sources of signal delay that will result in dqs being out of phase with clk exemplary contributing elements include but are not limited to clk clock jitter output pad delay output pad thermal variation in delay pc board loading termination resister quality clk u2192 dqs variance through dram input pad delay input pad thermal variance dll non linearity etc dqs 210 is applied to delay line 330 and also to delay line 328 via the inverter 326 those of ordinary skill in the art will recognize that in a double data rate ddr sdram component data is available on both the rising and falling edge of strobe dqs 210 delay lines 328 and 330 therefore serve to delay the corresponding falling or rising edge of data strobe dqs 210 for application as a clock signal to register flip flops 322 and 324 as is known in the art memory controller 300 must skew dqs 210 to capture data on dq 208 in the center.