hold circuit 30 similarly second readout output 24 is connected to the input of a second sample and hold circuit 32 both first sample and hold circuit 30 and second sample and hold circuit 32 have a trigger input provided by a digital signal processor further details about trigger input 34 and signal processor 40 will be disclosed at a later point in the present application connected to the output of first sample and hold circuit 30 is a first flash analog to digital converter a d converter 44 similarly connected to an output of second sample and hold circuit 32 is a second flash a d converter 46 both first flash a d converter 44 and second flash a d converter 46 receive an analog input and produce a digital signal indicative of the analog input at an a d converter output more specifically first flash a d converter 44 provides a digital signal at a first digital interface 48 while second flash a d converter 46 provides a digital signal indicative of the analog signal at its input at second a d digital interface 50 both first a d digital interface 48 and second a d digital interface 50 are connected.