selection of the gate material wherein both a predominantly standard n polysilicon or a policide or a silicide as well as high melting point metals can be employed a cmos process having an n well will be described below only the n channel transistor is fashioned as an ldd transistor referring to fig5 there is shown a p doped substrate 1 having an n well formation 14 therein and including active transistor zones defined by the field oxide regions 2 then gate oxidation is carried out as described in connection with fig1 the gates 15 and 16 and the gate interconnects 17 and 18 which serve as connections are then simultaneously structured the implantation with arsenic or phosphorous ions for producing a shallow diffusion region 7 then occurs as described in conjunction with fig1 and is shown by the arrows 6 referring to fig6 after the n implantation in the zones 6 and 7 the gate interconnects 15 16 17 and 18 are surrounded with an insulating layer 19 composed for example of sio 2 in the manner described in fig2 also the contact hole regions b 39 and b 34 are opened for forming the buried contacts in fig7 which is analogous to the method described in fig3 a spacer layer structure 20 composed for example of tantalum disilicide tasi 2 is produced by chemical vapor deposition the anisotropic etching of tantalum silicide is possible in various forms for example a reactive ion etching in sf 6 can take place in the pressure range of a few pascal or in a similar pressure range the etching can take place.