210 fig3 a through 3e are cross sectional views illustrating process steps for fabricating an interconnect structure according to the second embodiment of the present invention fig3 a continues from fig1 h in fig3 a a dielectric liner 245 is formed on all exposed surfaces of liner 190 in one example dielectric liner 245 may comprise for example silicon dioxide sio 2 silicon nitride si 3 n 4 silicon carbide sic silicon oxy nitride sion silicon oxy carbide sioc hydrogen doped silica glass sicoh plasma enhanced silicon nitride psin x or nblok sic n h or combinations thereof in one example dielectric liner 245 is about 5 nm to about 100 nm thick dielectric liner 245 may be formed for example by cvd or ald in fig3 b a directional etch process such as an rie is performed to remove dielectric liner 245 from horizontal surfaces of liner 190 disposed on bottom surfaces of trenches 160 175 and 180 the directional etch process may be followed by a simultaneous sputter etch and liner deposition as metal neutrals process as described supra in reference to fig1 h in fig3 c core conductor 210 is formed as described supra ion reference to fig2 a the thickness of core conductor 210 is sufficient to completely fill trenches 160 175 and 180 in fig3 d a cmp process is performed to co planarize top surface 145 a of dielectric layer 135 top surface 215 of liner 190 top surface 220 of core conductor 210 and a top surface 250 of dielectric liner 245 after the cmp process a damascene wire 255 and a dual damascene wire 260 having with an integral damascene via 265 are formed in fig3 e caps 240 are selectively formed on top surface 220 of core conductor 210.