34 i 34 is fed to an and gate 44 which responds to the timing pulse 34 a 34 applying a trigger pulse for rendering a timer 43 operative thus timer 43 generates a pulse 34 j 34 after a time period selected so that the pager receiver can detect the message codes the pulse 34 j 34 resets flip flop 42 timer 43 and battery saver control circuit 52 fig7 is a circuit diagram showing one example of the switch 10 or the loudspeaker driver 6 fig3 which comprises two transistors 56 58 and two resistors 57 59 all of which are coupled as shown to the base of the transistor 58 is applied the control signal b from the decoder 4 signal b controls the transistor 58 which in turn controls the switch over of transistor 56 for selective power supply to the circuits connected to its collector viz front end 2 and wave shaper 3 for the clock 47 a multivibrator is available timers 28 37 43 counter 36 and battery saver control 52 can be realized by using for example pd4020 manufactured by nec and a plurality of logic gates coupled thereto to provide the prom 5 pb487r available from nec is suitable the decoder 4 can be replaced by a cpu as can be understood from the foregoing the battery saver circuit according to the present invention is able to effectively detect a valid incoming signal a preamble and or subsequent message codes thereby enabling the battery saving operation to be terminated for continuous energization of a pager receiver the foregoing description shows.