line of image data has been completely transmitted upon the reception of either of the end of line eol 1 eol 2 control words additional state machines not shown will operate once either of the expose line exp 1 exp 2 control words are detected so that receiver fpga 94 will send the stop receiving data signal 88 upon reception of either of the expose line exp 1 exp 2 control words the state machines shown in fig8 are identical to those discussed above in fig7 except for the value use to initialize counter 84 a 84 b employs different presets values the end of line eol 1 eol 2 and expose line exp 1 exp 2 control words are different control words from the start of line sol 1 sol 2 control words and have initialization values as previously discussed if eol 1 83 a returns a positive result after detection by control word 82 a then idle 81 a stops and initialize a counter 84 a presets a counter with a predetermined value decrement eol 1 counter 85 a runs until counter is zero 86 a is true set eol 1 flag 87 a indicates that the receiver fpga 94 knows the end image data is 5 characters back in the ram buffer if the end of line eol 1 control word was not received and the end of line.