may be changed for example in the case where data should be considered valid only when judgement proves that correction cannot be made in c 1 correction such a circuit as shown in fig1 may be used in fig1 the circuit includes an and circuit 118 a c 1 parity 35 is added in performing coding to the region of the ram 207 in which the id data 50 and the flag data 51 have been stored accordingly it is necessary to read out the id data 50 and the flag data 51 before coding is carried out in order to read out those data prior to the coding however it is necessary to provide another storage circuit if the id data 50 and the flag data 51 are rewritten to an unused region in the ram 207 by using ram access for parity generation by controlling the coding address generation circuit 211 and the higher rank address generation circuit 218 the additional provision of the storage circuit can be avoided fig2 is a timing chart in the coding operation performed in the coding circuit 205 data exchange between the coding circuit 205 and the ram 207 is executed at timings on a time belt 140 while coding processing is executed at an operation time belt 141 data d l of one system and 32 words is.