unit groups register file 76 is constructed of 2 banks of sixteen 32 bit registers each there are 12 read ports and 6 write ports in order to supply the many execute resources in the datapath while conserving read write ports the two read ports for base and offset of d unit group 72 are shared with source 3 and 4 of s unit group 82 in other words the lower 16 registers 0 15 only go to d unit group 72 and the upper 16 registers 16 31 only go to s unit group 82 similarly the write port for the address result from d unit group 72 is shared with the adder result from m unit group 84 the lower 16 registers only go to d unit group 72 and the upper 16 registers only go to m unit group 84 there are 3 classes of operation in the execute stages single cycle 3 cycle and load store multi cycle all operations in a unit group 78 c unit group 80 and s unit group 82 the add functional unit in m unit group 82 and address generation in d unit group 72 are single cycle multiply functions in m unit group 84 take 3 cycles load and store operations take 6 and 5 cycles respectively in case of cache hit cycle counts are longer and variable in.