an integer part and a fraction part and may be either a constant value or a variable if the oversample rate is an exact multiple of the sample hold rate the fraction part will be zero for an asynchronous sample rate converter the rate value is variable and is controlled by a dpll or its equivalent fig4 illustrates one hardware embodiment of my invention an oversample clock keeps each part synchronized to the output sample rate an accumulator determines when new input data is needed based on the supplied rate value which can be a constant or a variable for asynchronous sample rate conversion the rate value is varied to keep the need for input data synchronized with the supply of input data the accumulator has both an integer u201c i u201d and a fraction u201c f u201d part and is decremented by 1 each cycle except that when the integer part is zero the rate value minus 1 is added instead comparators determine when the integer part is one or zero so that control can control the accumulator a digital signal processor u201c dsp u201d and the output data value path optionally the output data values developed by the dsp can be serially stored in a memory and retrieved as needed by a direct memory access u201c dma u201d facility for output to an output data bus via an output register u201c option a u201d or forwarded via an output queue directly to the output data bus u201c option b u201d the fraction part of the accumulator can only change when the integer part of the accumulator is zero at the time the rate value is.