threshold bt the voltage vdd has not changed whereby count a progresses at the same speed as during the previous clock cycle count a reaches value bt 12 in the middle of the clock cycle fig6 is a circuit diagram of an exemplary oscillator structure common to both oscillators 30 32 that may be designed to offer a linearly proportional voltage to frequency response the oscillator comprises an odd number of cmos inverters 44 here three connected in a ring each inverter 44 is supplied from line vdd by a controlled current source in the form of a p mos transistor 46 the p mos transistors 46 are connected in parallel in a current mirror configuration to copy the current from a common p mos transistor 48 the transistor 48 is connected in a voltage follower configuration with an operational amplifier 50 the gate of transistor 48 is controlled by the output of amplifier 50 the source of transistor 48 is connected to line vdd and the drain of the transistor is fed back to the non inverting input of the amplifier 50 the inverting input of the amplifier 50 receives the corresponding voltage to follow vdd or vl for instance attenuated by a factor k through a divider bridge 52 with this configuration the amplifier 50 controls the transistor 48 so that its drain voltage equals the voltage at the inverting input of the amplifier this voltage k u00b7 vdd or k u00b7 vref is applied to a resistor r 0 connected to line vss the resistor r 0 thus draws a current io equal to k u00b7 vdd r0 or k u00b7 vref r0 through transistor 48.