a desired value particularly in the distal zone fig3 depicts a method 300 for fabricating the fet in accordance with an embodiment of the invention this method includes the step of providing a substrate typically planarized and without strained layers step 302 the substrate can include relaxed sige on a compositionally graded sige layer relaxed sige on a si substrate relaxed sige on si or other compounds such as gaas or inp the substrate can also contain a buried insulating layer next initial vlsi processing steps are performed such as for example surface cleaning sacrificial oxidation deep well drive in and isolation processes like shallow trench isolation with liner oxidation or locos step 304 any number of these steps may include high temperatures or surface material consumption features defined during step 304 can include deep isolation wells and trench etch refill isolation structures typically these isolation trenches will be refilled with sio 2 or another insulating material examples of which are described above next the channel region is doped by techniques such as shallow ion implantation or outdiffusion from a solid source step 306 for example a dopant source from glass such as bsg or psg may be deposited step 308 followed by a high temperature step to outdiffuse dopants from the glass step 310 the glass can then be etched away leaving a sharp dopant spike.