of the compare to the match lines 205 if the value of the mask register indicates that the data bit is valid for comparison the cell 206 is arrayed w times to form a row of width w 207 and the row is arrayed 2 n times to form the table since multiple rows may match a given input a priority circuit 208 is used to select one of the match lines the block diagram of fig3 a illustrates a cam 300 with a capacity of n u00d7 n entries according to one embodiment of the present invention there are n blocks block 1 320 through block n 321 within each block there is a specification memory 301 which can store up to n entries the entry bit select circuit 302 selects certain bits from the input word 303 of width w the entry select circuit 305 uses the selected bits 304 of width sw to select one of the n entries from the specification memory the selected entry output on 306 is optionally modified by the interpretation circuit 307 and output on 308 the input 303 is optionally modified by the compare gate and modify circuit 316 and output on 310 the compare circuit 309 compares 308 against 310 and indicates whether the input matched the selected entry on match line 311 the address of the selected entry within the block is output as addr 312 there are n match indicators one from each of the n blocks one of which is selected by the priority circuit 313 whose output match 315 is set if at least one of the blocks indicates.