the potential of the node n2 become high due to the function of a flip flop 17 at this time the transistor t10 is turned off the level of the potential of the test signal u03c6 output from the node n2 is maintained at a high level due to the above condition being maintained by the flip flop 17 even after the transistor t11 is turned off as described above in the present invention the test mode can be maintained by only applying a brief high potential to the input terminal of the high potential detection circuit 16 to latch the level of the potential of the test signal u03c6 at a high level due to the function of the flip flop 17 provided in this circuit as mentioned above and thus the flexibility of the test of the memory circuit can be improved since one of the input terminals to which the address signal is always input for example can be used as the input terminal for the high potential detection circuit 16 fig1 b shows a specific embodiment of the construction of the high potential detection circuit 16 as mentioned above and in which an address signal about 0 v to 5 v for example is usually input to the input terminal thereof.