a plurality of memory modules 16 in the following discussion the number of memory modules will be denoted by m to simplify the following discussion it will be assumed that m is a power of two i e m 2 m cpu 14 requests data stored in memory 14 by sending an address a to hash circuit 18 on address bus 22 hash circuit 18 converts address a to a module address b specifying which of the m memory modules is used to store the data specified by a and an offset c within said memory module which specifies the location of the memory cell in said memory module in which the data is stored offset c is then transmitted to memory module b which in turn either reads the data from bus 20 and stores said data in memory location c or places the data stored in memory location c onto bus 20 for simplicity the read write control lines and various buffers needed to overcome the delays in providing the mapping of a into b c have been omitted from the drawing the manner in which hash circuit 18 provides the mapping in question can be divided into two parts as will be discussed in more detail below the most important part of the present invention relates to.