layer 1216 a e g comprising oxide is deposited with a differential fill so that a thicker oxide is formed over gate electrode 1212 in the trench than over the adjacent mesa in fig1 c dielectric layer 1216 a is uniformly etched whereby a thin layer of dielectric 1216 b remains in the trench over gate electrode 1212 in fig1 c trench 1205 is filled with doped polysilicon 1217 conventional techniques are then used to form the heavy body region no shown the source interconnect not shown and other regions and layers in order to complete the cell structure source plug 1217 may be incorporated in the trench gate fet 100 in fig1 by integrating the process module represented by fig1 a 12d in conventional process sequences for forming the trench gate fet 100 in a similar manner fig7 shows a cross section view of a composite dual gate trench mosfet 700 wherein the advantageous features of the structures in fig4 6 have been combined as shown n type channel enhancement regions 726 source plug 730 and locos shield dielectric 722 are incorporate in mosfet 700 note that any two of the three features may be combined rather than all three depending on the design goals and performance requirements the alternate embodiments of each of the mosfets 400 500 600 discussed above also apply to mosfet 700 the modifications that need to be made to the process flow in fig1 a 13l to form mosfet 700 would be.