problems with rbc can include access being scattered across all banks so when there is access across multiple pages multiple banks need to be accessed which may make partial bank refreshes self refreshes difficult it will be appreciated that while brc and rbc memory mapping modes are discussed herein with respect to some embodiments in certain embodiments other known memory mapping modes may be used including for example variations of rbc and brc throughout this disclosure the examples and figures discussed assume a single 128 megabyte mb double data rate ddr sdram device with a 32 bit interface though it will be understood by those of skill in the art that larger or smaller memory devices with varying specifications may be supported including devices that use other sdram standards such as ddr2 ddr3 etc a ddr device with a 32 bit interface may have eight banks 8192 rows per bank and 512 columns per row given that the examples used throughout this disclosure assume a 128 mb ddr device each of the 8192 rows corresponds to 2 kilobytes kb of memory i e a 2 kb page size thus each of the eight banks corresponds to 16 mb of memory accordingly in brc memory mapping mode there may be a latency penalty when crossing the 2 kb boundary whereas with rbc there is no latency penalty when crossing the 2 kb boundary also with brc 16 mb of memory may be accessed before a bank switch is required but with rbc just 2 kb of memory may be accessed before a bank switch is required given the exemplary constraints outlined above i e a 128 mb ddr device with eight banks 8192 rows per bank and 512 columns per row the memory may be partitioned into.