dq 3 dq 4 through a plurality of data input output signal lines therefore the designated number u201c 0 u201d is stored in all the dynamic semiconductor memory devices m 1 m 2 m 3 m 4 in the memory module mm 1 further the controller transmits the inverted chip selection signal csb 2 and the designated number u201c 1 u201d as the data to the memory module mm 2 therefore the designated number u201c 1 u201d can be stored in the dynamic semiconductor memory devices m 1 m 2 m 3 m 4 in the memory module mm 2 in the same way the designated number u201c 2 u201d is stored in dynamic semiconductor memory devices m 1 m 2 m 3 m 4 in the memory module mm 3 and the designated number u201c 3 u201d is stored in dynamic semiconductor memory devices m 1 m 2 m 3 m 4 in the memory module mm 4 0041 fig5 is a block diagram of a system in accordance with another exemplary embodiment of the present invention signals are connected and associated with each other in the same way of fig2 however each of dynamic semiconductor memory devices m 1 m 2 m 3 m 4 in memory modules mm 1 mm 2 mm 3 mm 4 stores its own designated number designating an order for performing the refresh operation the number being designated by the controller in fig5 numbers in round brackets are the designated numbers.