be realized that other process parameters may be changed and the present invention is not limited by the above referenced process parameters which are provided as some examples also profile engineering in any situation deposition etching or none may be performed for high surface concentration or a deep profile tail an initial deposition may be performed to reduce channeling open and closed loop control may be utilized for bias ramping in situ and ex situ deposition measurements may be used in these control loops as shown in fig4 the bias voltage increases during plasma implantation as indicated by the arrow length the energy gain for each ion is equivalent to energy loss through the deposition layer so that ion distribution within the substrate remains largely the same as described above the increase of bias voltage can be linear or non linear with time depending on the deposition rate which can also be linear or non linear with time accordingly the retained dose is maximized without a deep dopant profile fig5 a 5 b and 5 c illustrate bias ramping combined with duty cycle ramping for achieving a higher duty cycle at lower ramping bias for improving wafer throughput and photo resist conditioning of the wafers the bias voltage is applied only during the u201c on u201d period as shown in fig5 a however the amplitude of the bias voltage may be controlled separated by the controller 50 also the bias voltage may start with a lower duty cycle as shown in fig5 b and end with a higher duty cycle as shown in fig5 c or the bias.