signal cv 2 increases also the resistance of the second load device pl 2 which is controlled by the second control signal cv 2 increases and a capacity of current flowing from the supply voltage vcc to the complementary data line giob may decrease that is if the voltage level of the complementary data line giob decreases the resistance of the second load device pl 2 between the supply voltage vcc and the supplementary data line giob increases so that a capacity of current flowing into the complementary data line giob from the supply voltage vcc through the second load device pl 2 may decrease therefore the changes in the current signal of the complementary data line giob are reflected in the current signal i 2 that is transmitted to the current sense amplifier 240 with reduced loss of data on changes in the current signal as described above in the active load circuit 230 according to embodiments of the present invention the small current signal loaded to the pairs of data lines gio and giob from the bit line sense amplifier 220 can be transmitted to the current sense amplifier with reduced loss of data on the small current signal so that the current sense amplifier 240 can adequately sense the data fig3 is a circuit diagram of an active load circuit 300 according to second embodiments of the present invention referring to fig3 the active load circuit 300 further includes a precharge device 310 in addition to the active load circuit 230 of the first embodiments of the present invention accordingly.