19 is a sub sampling and spatial filter for performing sub sampling and spatial filtering fig7 is a block diagram showing the details of the structure of the sub sampling and spatial filter 19 this circuit of fig7 also in view of the spatial filtering function carries out processing according to the computation of the equation 1 and uses the same reference characters as those in fig4 in fig7 a digital signal output from the a d converter 18 enters at an input terminal 100 the input data series is parallelized by a parallelizing circuit 101 delay circuits 102 104 and 106 each delay an input signal by 1 h where h is a horizontal scanning period delay circuits 108 109 110 111 112 113 114 115 and 116 each delay an input signal by one picture element 2 fs obtained after sub sampling 118 120 122 124 126 128 and 130 are adders 132 is a subtractor 134 136 138 140 and 142 are multipliers having coefficients k 1 k 5 respectively 144 is a divider having a divisor a 146 is a changeover switch for alternating two original picture element data parallelized by the parallelizing circuit 101 in every one line 148 150 and 152 are compensation switches for compensating for the delay of a picture element which are changed over in association with the changeover switch 146 the changeover switch 146 and the compensation switches 148 150 and 152 are changed over together.