an interpolation frequency rate signal and a signal fed back from the output thereof the frequency register 35 receives an interpolation frequency signal a frequency register summing device 33 b receives the signal fed back from the output of the frequency rate register 34 along with a signal fed back from the output of the frequency register 35 and outputs a signal that is input to the frequency register 35 a phase register summing device 33 b receives the signal fed back from the output of the frequency register 35 along with a signal fed back from the output of the phase register 36 and outputs a signal that is input to the phase register 36 the output clock is input to the phase register 36 the phase register 36 outputs an interpolation control signal that is applied to the interpolation filter 21 see fig3 the interpolation control generator 50 is driven by the output clock at each output clock tick the phase of the phase register 36 is stepped by one phase step from the frequency register 35 a preferred implementation reduces the sample rate at the output of the interpolation filter 21 for example the output sample rate of the interpolation filter 21 might be 60 of the input rate one phase step for the interpolation filter output clock will be more than one cycle of the input clock for some of the input clocks the output phase will be in the next cycle of the input clock for others the phase step will cause the.