memory a3 and then another two images images number 10 and 11 in the first temporary memory a2 thus the first temporary memory a2 is obviously not complete and the last complete summation in the second temporary memory a2 is used as the secondary mask the study is started with the image number 12 which is stored in the first storage location b1 of the second memory the number n of images is limited by the bit depth of the memory and then digitized word length of the image care must be taken to prevent overflows in the addition process in fig6 an embodiment of a control unit controlling the automatic secondary mask generation with summation of image signals is illustrated in fig7 the timing sequence of major signals applied in the control unit of fig6 is shown the embodiment illustrated in fig6 is based on the basic design shown in fig3 the first memory 34 contains a first memory unit a1 or 101 a second memory unit a2 or 102 and a thrid memory unit a3 or 103 in order to form summed up image signals each data input of the memories 101 102 and 103 is associated with a sum logic circuit 101a 102a and 103a respectively the control circuitry for generating the primary and the secondary mask contains a memory and control logic 104 a first flip flop ff1 or 105 a second flip flop ff2 or 106 and a third flip flop ff3 or 107 the clock inputs of these flip flops 105 106 and 107 are controlled by an and gate 105a an or gate 106a and an and gate 107a respectively an analog to digital converter adc or 108.