a and 3 b show two esd protection circuits each having an esd protection trigger circuit according to the invention and connected between power lines vcc and gnd as shown in fig3 a and 3 b diode string s 7 connects with resistor r 0 to form an esd protection trigger circuit connected between power lines vcc and gnd the connection node between diode string s 7 and resistor r 0 can be connected to a trigger node of a primary esd protection device the primary esd protection device is not limited to the bipolar junction transistor bjt b 0 shown in fig3 a or a field effect transistor such as the metal oxide semiconductor transistor mos m 0 shown in fig3 b in fig3 a the trigger node is the base of bjt b 0 and in fig3 b the trigger node is the gate of mos m 0 when a pulse relatively positive to power line gnd occurs on power line vcc the voltage at the trigger node temporarily rises to trigger the primary esd protection device and release esd stress depending on process technology and layout arrangement a diode string according to the present invention may differ from the embodiment shown in fig1 a fig4 to 6 show cross sections of three diode strings further embodying the present invention the diode string in fig4 can be fabricated by triple well cmos process unlike to the single deep n well 112 in fig1 a there are several deep n wells 112 together with n wells 110 n wells 110 and deep n wells 112 have substantially the same.