which the expectation value is applied respectively and the outputs of the comparators are sent to a discriminator in the system of fig1 two clock signals having different delay times are supplied to the input side flip flop circuit and to the output side flip flop circuit through the terminal pin pin a and through the terminal pin pin b respectively a test system for a ram according to an embodiment of the present invention will now be described with reference to fig2 in fig2 a clock pulse is sent to a clock pulse width varying portion 2 where a delay control signal is delivered to vary the width of the clock pulse the output of the clock pulse width varying portion 2 is sent to an address latch 4 and an output latch 6 simultaneously the address latch 4 samples new address signals by a leading edge of the clock pulse and the output latch 6 is latched by a trailing edge of the clock pulse sample is carried out also from the leading edge timing thus comparing the output of the ram 1 with the output expectation value responsive to the address access time of the ram 1 by a comparator 5 or exclusive or circuit the exclusive or gate will provide an output logic 1 only when the two inputs are not alike this means that the two inputs must have a different logic level in order for a logic 1 output to occur note that for the exclusive or gate an output logic 1 results only in steps when two inputs are 34 0 34 34 1 34 or 34 1 34 34 0 34 i e where the inputs have a different logic state the exclusive or gate is used in binary word detection.