4 b are inserted to distribute and route the latch data buses 4 originating from various lut sram latches 2 these latch data buses may be routed to nearby or remote regions of the device using a programmable bus routing network 4 the routing network 4 in no way introduces any extra delays in the final circuit implementation as static logic data resides on these latch data lines thus the latch data buses 4 can traverse long distances and use any number of programmable switches 4 b and 4 c without affecting circuit performance as all the nets in a bus are being routed at a time configuration latch count is also low it is of course possible to alter the multiplexer connectivity to the latch data bus and even include flexibility at the decoding multiplexer inputs 1 a sixteen here inputs to the multiplexer 1 x delineate such possibilities to include more flexibility programmable switches 4 c are inserted to couple latch data bus 4 to the multiplexer inputs 1 a as desired the present invention thus provides a look up table with a plurality of read ports capable of performing functions that are identical or logically equivalent with other variants the area saved by using this approach is appreciable and without significant delay overhead in conclusion the concept of sharing sram latches of luts reduces the number of sram latches and improves chip density while exemplary embodiments of the present invention have been described above it is possible to use various.