interface unit 14 are designated by the channel 16 incoming data which is transmitted to the cpu by way of interface unit 14 is designated by the channel 18 a decoding logic circuit 20 which monitors the outgoing command traffic in channel 6 is coupled to the latter by means of a channel 22 and the input terminals of unit 20 similarly a decoding logic unit 24 has its input terminals connected by way of a channel 26 to channel 18 in order to monitor the incoming data traffic in the latter the monitoring circuit of the present invention further includes an indicating unit 28 which is seen to consist of a plurality of flip flops each having a set and reset input each flip flop further includes a single output e g adapted to provide a 34 1 34 signal when the flip flop is in its set state the circuit also includes a counter 30 having an incrementing input designated 1 and a decrementing input designated 1 the signal provided on a plurality of counter outputs indicates the count decoding unit 20 provides four read command signals and a write command signal respectively on five outputs these have been shown as a pair of outputs for case of illustration as shown in fig1 read command i output is coupled to the set inputs of the i th flip flops of indicating unit 28 the write command output is coupled to the incrementing input of counter 30 decoding logic unit 24 provides four read data signals as well as a write status data signal on five outputs read data output i is coupled to the reset inputs of the i th flip flops of unit 28 and the write status data output is coupled to the decrementing.