to the data line 50 the source of the transistor 52 and the drain of the transistor 54 have a common connection the sources of the transistors 54 and 56 are common with the ground line 42 the gate of the transistor 52 receives the binary indication representing the row in which the particular cell is disposed and the gate of the transistor 54 receives the binary indication representing the column in which the particular cell is disposed a binary indication representing the next column is introduced to the gate of the transistor 56 when binary indications of 0 are introduced to the gates of the transistors 44 46 and 48 these transistors become conductive as a result a high voltage is produced on the line 50 to indicate a binary value of u201c 0 u201d for a cell when high voltages are introduced to the gates of the transistors 52 54 and 56 all of these transistors become conductive this cause a low voltage to be produced on the line 50 to indicate a binary u201c 1 u201d the voltage on the line 50 in fig3 is introduced to a pair of lines 60 and 62 in fig5 which shows a current source generally indicated at 63 of the prior art these lines are respectively designated as u201c lan u201d and u201c lap u201d where the u201c n u201d in u201c lan u201d indicates u201c negative u201d and the u201c p u201d in u201c lap u201d indicates u201c positive u201d the lines 60 and 62 in fig5 are respectively introduced to the gates of a pair of transistors 64 and 66 both preferably cmos transistor of the n type the drains of the transistors 64.