in the u03bc th output vector m i sup u03bc 1 is the i th output of network 10 in the next u03bc 1 th output vector and m is the length of the sequence i e the number of different m vectors created to achieve a cyclic sequence the summation of equation 3 is performed in modulo m in other words m m 1 m 1 network 50 is able to disconnect the feedback path from delay averaging network 30 to interconnection network 40 by action of the control port causing the fig1 circuit to settle to a quiescent state gate network 50 can also be endowed with the ability to add a 34 kicker 34 signal vector to the fed back voltage under control of an enabling signal at the control port which could drive the fig1 circuit from one cyclic sequence to a second cyclic sequence both of which are designed into the q ij interconnection values the output of the fig1 circuit can be obtained from the output of amplifier network 10 or alternatively from the output of delay averaging network 30 the structure of delay averaging network 30 can be quite simple in fig1 it is shown as a simple rc network which produces a delay related to the rc time constant to avoid diminution of the signal because of the series resistor in the rc network and to insure.