layer 26 to the insulating oxide layer 22 isolate the active region 18 of fet 10 from other devices not shown that may be formed in the silicon device layer 26 a gate oxide layer 30 is on the top surface of the active region 18 and isolates the active region 18 from a gate 32 the gate 32 includes a polysilicon base gate region 34 adjacent to the gate oxide layer 30 and a tungsten damascene wide cap region 36 the tungsten damascene wide cap region 36 is positioned to the top and sides of the base gate region 34 and forms a contact coupling the base gate region to the metal layers 38 a thin titanium nitride diffusion barrier 40 prevents diffusion between the tungsten damascene cap region 36 and the base gate region 34 the channel region 16 includes an upper region 42 adjacent to the gate oxide layer 30 and a lower region 44 adjacent to the insulating oxide layer 22 in the preferred embodiment the upper region 42 has a width of less than 20 nm and the lower region 44 has a width of approximately 50 nm the silicon device layer 26 has a thickness of 20 30 nm and the insulating oxide layer is approximately 30 70 nm thick it should be appreciated that the upper region 42 has a width less than the thickness of the silicon device layer 26 while the lower region 44 has a width greater than the thickness of the silicon device layer 26 as such fet 10 is a combination of both a short channel and a long channel device while in the u201c on u201d state e.