and the switches sw 2 and sw 4 can be p type transistors or vice versa if the switches sw 1 and sw 3 are n type transistors and the switches sw 2 and sw 4 are p type transistors the switches sw 1 and sw 3 are turned on closed circuit and the switches sw 2 and sw 4 are turned off open circuit when receiving a control signal of u201c 1 u201d high voltage level and the switches sw 1 and sw 3 are turned off and the switches sw 2 and sw 4 are turned on when receiving a control signal of u201c 0 u201d low voltage level with reference to fig4 the operation of the integrated reference voltage generating circuit 30 will be described in fig4 u03c6 1 u03c6 4 represent control pulses each with two states high and low for ease of explanation only reference voltages v 0 v 1 v 62 and v 63 are shown for illustrating the operation of the integrated reference voltage generating circuit 30 during the normal mode and the power saving modes to prevent electroplating of ion impurity and image retention of the liquid crystal lc material the polarity of the lc cell voltage is reversed on alternative intervals the reference voltage v 0 and v 63 are both produced by coupling node c of the resistor circuit 32 to the power supply vcc and node d of the resistor circuit 32 to the power supply vss in a first driving period and by coupling node c of the resistor circuit 32 to the power supply vss and node d of the resistor circuit 32 to the power supply vcc in a second driving period each such driving period alternates in a fixed.