transistor of the slave flip flop t 14 is coupled into the opposite leg of the circuit of the slave flip flop 17 as is the multiple emitter transistor t 7 in the master flip flop circuit 15 as will be subsequently explained this will insure that the master and slave flip flops are maintained in opposite modes through the major portion of each clock cycle in the slave flip flop the base of transistor t 8 is coupled to the collector of transistor t 1 the emitter of t 8 forms the data intake switch by being coupled with the emitter of transistor t 11 the collector of transistor t 8 is coupled with d out and the ground rail through resistor r 3 the latch switch of the slave flip flop is formed by transistors t 9 and t 10 the emitters of t 9 and t 10 are coupled together with the collector of multi emitter transistor t 14 the base of t 9 is coupled to d out which is coupled to the ground rail through r 4 the base of t 10 is coupled to the ground rail through r 3 transistor t 11 has its collector coupled to d out and is coupled also with the ground rail through resistor r 4 the base of transistor t 11 is coupled to the collector of transistor t 4 transistor t 12 and the multi emitter transistor t 14 comprise the clock switch for the slave flip flop the base of t 12 is coupled to the dc bias v t the emitter of transistor.