can be used in order to realize the active area 2300 of fig2 additionally the second semiconductor layer 7005 can be used as a back gate for the transistors 1100 and 1200 as will be explained below although this embodiment is specifically related to an soi architecture the invention can also be realized with finfets or any other technology that allows at least the body of transistor 1200 to be floating the operation of floating body memory cell 1000 will now be described with reference fig7 through 10 with reference to the cut lines a a u2032 and b b u2032 of fig6 fig7 and 8 are taken along line a a u2032 while fig9 and 10 are taken along line b b u2032 fig7 schematically illustrates the operation of floating body memory cell 1000 during the writing of a logical value of 1 in particular by applying a negative voltage to the gate 1102 of pmos transistor 1100 that is connection 6901 the pmos transistor 1100 is turned on at the same time by applying a negative voltage to the contact 4701 positive charges from the body 1204 of nmos transistor 1200 are drawn away from the body 1202 of nmos transistor 1200 as illustrated by arrow 7001 in this manner the body 1204 contains no charges thereby storing a value of 1 in addition the gate 1202 of nmos transistor 1200 that is connection 6902 can also be set at a negative value so as to put transistor 1200 into inversion mode.