c of fig2 to accomplish the required pressure in the positive pressure side operation of the digital control circuit 5 is explained with reference to the wiring diagram shown in fig3 and the time chart shown in fig4 the binary counter 13 generates 34 0 34 level pulse at the 34 borrow 34 terminal at the time when it finishes counting 256 clock pulses applied to the 34 down 34 terminal this signal waveform at the point f is shown in f of fig4 the 34 borrow 34 output of the binary counter 13 is applied to the rsd flip flop 16 the output q of which is set to 34 1 34 level this signal waveform at the point h is shown in h of fig4 the preset counter 14 on the other hand starts downcounting at the time when signal level at the 34 load 34 terminal becomes 34 1 34 and generates 34 0 34 level pulse at the 34 borrow 34 terminal when the data becomes zero this signal waveform at the point g is shown in g of fig4 the 34 borrow 34 output of the preset counter 14 is applied to the 34 d 34 terminal of the rsd flip flop 16 and then fed to the output q to render the signal level to 34 0 34 in synchronization with the rising edge of the clock pulse d of fig4 which is earlier by one cycle period than the clock pulse e of fig4 applied to the binary counter 13 and the preset counter 14 after one.