the bit value and an unstable operating point as shown in fig9 the circuit can be relatively easily driven from the unstable state to a stable state by an external signal on the input or due to slight differences in the elements used to build the circuit here inverters this fact can be used in accordance with a second exemplary embodiment of the invention to build a puf where the circuit is initially at the unstable operating point and let to attain one of the two stable operating points without any external excitation we find that with a high probability the circuit goes more to one of the operating points based on small differences in the wire delays and the voltage transfer characteristics of the cross coupled element in this case an inverter different cross coupled devices can be built using different elements like nor gates or nand gates implementing a cross coupled element using combinational logic on fpga is not necessarily straightforward due to the inability to create combinational loops to overcome this problem a cross coupled combinational loop can be simulated using latches present in the fpga in one exemplary embodiment a butterfly structure may be created using the latches that allows for an unstable state by an excite signal and settles down to one of the two stable states after some time the structure of the circuit is as shown in fig1 it consists of two latches each with preset pre set q to 1 on high and clear clr set q to 0 on high input the data d is transferred on the output q when the clk.