the pad driver transistors this pad driver circuitry is capable of supporting any single ended signaling protocol fig5 shows the conventional lvds driver architecture pmos p 10 acts as a current source having its gate connected to a current reference voltage vbias_p and its source is connected to the supply voltage vddo vbias_p is generated from a bias cell and its value is so that it allows p 10 to source constant current 1 nmos n 10 acts as a current sink having its gate connected to a current reference voltage vbias_n and its source is connected to the ground terminal vsso vbias_n is also generated from the bias cell and its value is such that it allows nmos n 10 to sink a constant current 1 four transistors p 1 p 2 n 1 and n 2 form a current steering circuit the gates of p 1 and n 1 are controlled by an input signal in and gates of p 2 and n 2 are controlled by complementary signal in u02dc it is required that there should be no skew between the signals in and in u02dc the drains of p 1 and n 1 are connected together to the pad 20 and the drains of p 2 and n 2 are together connected to the pad 10 a 100 ohm resistance 30 is connected between pads 10 and 20 the resister is connected at the receiver end after the transmission lines which are not shown here when in.