control device at step 204 the television signal is coupled to a down converter or mixer for further processing in step 206 the microprocessor master signals the bus expander via a first iic command to set the bus expander output to a low state henceforth the phase lock loop may receive data transmission from the microprocessor via the scl and sda lines to start data transmission the microprocessor sets the sda line of the iic bus from a steady state high to a low transition while the scl is held in a steady state high such transition indicates a start condition for the exchange of data bits the high or low state of the data line sda may only change when the clock signal on the scl line is low at the next clock pulse from the microprocessor the serial clock line is set low causing the output clock line of the buffer i e first or gate of fig1 coupled to the clock input of the phase lock loop to a low state at each subsequent low clock pulse data may be transmitted over the sda line thereby permitting the phase lock loop ic to receive data transmissions over the iic bus from the microprocessor the data transmissions contain information necessary for the phase lock loop to generate a tone which facilitates demodulation of a television signal located at a particular channel as long as the microprocessor sends a repeated start signal prior to transmitting each byte the iic bus remains in a u201c busy u201d state when the microprocessor has completed.