410 u00b7 r 318 v ref u00b7 u03b1 u00b7 r 318 r 410 2 offset voltage v n generated from the current i n between both ends of the resistor 324 of the n channel driving circuit 308 is represented by equation 3 as follows v n i n u00b7 r n u03b1i 1 u00b7 r 324 u03b1 ue8a0 v ref r 410 u00b7 r 324 u03b1 u00b7 v ref u00b7 r 324 r 410 3 once the resistors 318 and 324 have the same resistance a prescribed offset voltage is generated because v n v p 0044 fig6 a is a diagram that shows a circuit for operational characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is lower than vdd 2 fig6 b is a diagram that shows a graph of voltage characteristics of the preferred embodiment of the comparator according to the present invention when a common voltage is lower than vdd 2 as shown in fig6 a and fig6 b operations of the preferred embodiment of the input stage circuit when a level of common voltage v com ranges 0 v to vdd 2 will now be described the common voltage detection signal s com outputted from the common voltage detector 500 becomes low level since v com lt v lt thus the pmos transistor 314 of the p channel.