the information of the relevant source and target registers are passed to the respective recovery blocks each recovery block then reads in via its respective read port from the source register named and writes via its respective write port to the target register named furthermore since it is known that the two sub instructions derived from this ldp instruction have sequential entries in the ex_fifo only the pointer for the first sub instruction need be passed to the recovery block 124 recovery block 124 then acts as the u201c master u201d recovery block to which recovery block 126 links itself as the u201c slave u201d recovery block so that it can simply increment the pointer used by recovery block 124 to access the required entry in the ex_fifo in another situation it may be the case that when it is determined that register recovery is required to be performed for an instruction in fifo 120 the recovery block 126 is not available i e its read write ports are indicated as being occupied in this case the instruction arbitration unit can just allocate the instruction to recovery block 124 however if the instruction is a multiple operation instruction that will take several iterations to process recovery block 126 may become available when more than one operation remains to be performed for example if an ldm instruction corresponding to four load operations is received in fifo 120 and recovery block 126 is currently busy with another recovery operation the instruction arbitration.