the second layer will be a capacitor as shown in fig5 one terminal of the second layer the capacitor will be connected to the output terminal of the first layer the transmission gate the other terminal of the second layer the capacitor will be grounded as shown in fig5 note that some pins are reserved for resistance testing purpose to determine the voltage level for example in some ips such as band gap for stable reference voltage those pins are not characterized and will be partially or totally burned in the final delivery the spice netlist should be clean up the transmission gate may be a cmos complementary metal oxide semiconductor circuit or just an nmos n channel metal oxide semiconductor or pmos p channel metal oxide semiconductor circuit only during the extraction the gate port on the transmission gate is set to logic high power if an nmos circuit and set to logic low ground if a pmos circuit however in cases where the input pin is disabled the gate port will be tied to high or ground in order to prevent dc path error caused by device floating the output of the second level device has to be disconnected and tied to high or low during the device extraction in the second level inverter if s source or d drain has the same name as the substrate b then the s or d has to be tied to high for pmos and tied to low for nmos fig6 shows the methodology flow for finding the input cap and max loading of an ip component the step of parsing spice s 62 adjusts.