influence upon the equilibrium signals s 3 and s 4 this can prevent the occurrence of pulse width distortion in a digital signal which is an output signal of this optical signal receiving circuit 50 incidentally in the operational circuit 76 in fig3 the resistance 62 in fig1 is designed to have half of the value of the resistance r 301 and the voltage at the node n 1 drops by half the amplitude of the voltage signal si but for example as shown in fig4 it is also possible that the current i 6 has half of the value of the current i 1 i 3 by designing the emitter size of the transistor q 306 to be double the emitter size of the transistor q 307 with the resistance 62 having substantially the same value as the resistance r 301 in other words if the resistance 62 the resistance r 301 the mirror ratio of the fourth current mirror circuit cm 4 may be 2 1 as described above according to the optical signal receiving circuit 50 according to this embodiment the voltage signal s 1 is shifted by almost half of its amplitude in an opposite direction to an oscillation direction which is the direction of change when the optical signal is detected by the photodiode 10 and becomes the voltage signal s 12 hence the voltage signal s 2 as the reference voltage is located in the central position of the amplitude of the voltage signal s 12 and consequently even if the.