address control unit 350 is provided with a plurality of address latches 510 and 520 the address latches 510 and 520 receive the refresh signal srefreq from the frequency selection generator 330 and output n bit address signals al 0 and al n the address signals al 0 and al n are transferred to the bank control unit 360 additionally the msb signal al n that is the n th bit signal of the address signals al 0 and al n is transferred to the double refresh frequency generator 380 fig6 a is a block diagram of the double refresh frequency generator 380 of fig3 as illustrated in fig6 a the double refresh frequency generator 380 is provided with a fuse selector 610 a generation unit 620 and a selection unit 660 the fuse selector 610 outputs four frequency selection signals select 1 select 2 select 3 and select 4 to the selection unit 660 the generation unit 620 receives the self refresh command signal self refresh and the msb signal al n from the address control unit 350 and transfers n pulse signals 2 tref 4 tref 8 tref 16 tref 2 n tref to the selection unit 660 the selection.