each of a non differential output type and each critical node 122 a 122 b is pre charged high further it should be recognized that while two dlgs 112 114 have been illustrated the invention may include any number of dlgs 112 114 feeding to interconnecting gate 116 each critical node 122 a 122 b is coupled to a respective input of interconnecting gate 116 in the form of a nor gate 128 combinatorial sections 118 a 118 b and pre charge sections 120 a 120 b are substantially identical to those described relative to fig1 except that the inverting gates have been removed and an output 134 of nor gate 128 is fed back to control keeper devices tk 2 of each pre charge section 120 a 120 b since the inverting gates of fig1 have been removed the embodiment of fig2 provides a density advantage over the fig1 embodiment the truth table indicating the possible outcomes for nor gate 128 of fig2 follows as indicated in the above table nor gate 128 of fig2 suppresses any negative fault that affects a single dlg 112 114 i e one that changes the charge from the normal pre charged high on one of critical nodes 122 a 122 b any fault that causes a single critical node 122 a 122 b to go low when it should be high is overcome by the combination of these nodes 122 a 122 b only when both dlg 112 and dlg 114 show a low output will system 110 output a high signal in addition.