describe the functionality and relationships of the embodiment shown in fig1 and 2 here timing circuit block 20 receives source clock signal clk and horizontal and vertical synchronization signal sync and distributes control signals to shift register 111 and scanning signal drive circuit 103 on the other hand image signal video is supplied to image signal processing circuit 30 timing circuit block 20 distributes horizontal scanning signals 1h 2h 3h to scanning signal drive circuit 103 during one vertical scanning term horizontal scaling signals 1h 2h 3h are sequentially distributed to row lines 117 and turn on a series of conventional pixel circuits containing thin film transistor 115 in a manner well known in the art during each horizontal scanning term h shift register 111 outputs a sampling signal based on control signal from timing circuit block 20 to sampling switches 112 sampling switches 112 sample image signal corresponding to each pixel unit 114 and output drive voltage of the image signals to column lines 113 which activates a pixel 116 in pixel unit 114 image signal v comprising a sequential train of pixel image signals e 1 e 2 e 3 e n shown in fig3 are distributed to video in input of inversion circuit 40 referring to fig2 image signal output circuit 41 in inversion circuit 40 generates two kinds of image signals based on input image signal v i e the normal positive polarity signal of input image signal and the negative polarity signals of inverted input image signal and distribute them to two selectors 42a and 42b selector 42a selects positive image signal vp and distributes it to phase expansion circuit 50 selector 42b selects negative image signal vn these selectors 42a and 42b are controlled by control.