many instructions can be consumed by the pipeline and how many instructions are valid within the trace traces are generated by following numerous rules that result in trace sizes that vary from small to large in an implementation of this invention shown in fig2 the trace size is a maximum of 24 instructions therefore when a trace cache t cache hit is detected the data read out of the array can be any size from 1 instruction up to 24 the data is always left justified and therefore the end of the trace can be easily determined if the size of the trace is known fig3 shows a typical cache structure of a directory and data arrays in this implementation the trace size is stored within the directory when a cache hit is detected the trace size is used to save power by reading only the data associated with valid instruction entries it has been shown that large arrays dissipate the majority of power in processor designs and therefore limiting array accesses is a key to reducing overall power by dividing the logical trace cache into multiple physical arrays this invention is able to save the power of entire physical array accesses by enabling only the arrays that contain the instructions we.