ck 1 2 represents a phase 90 degrees i e q phase if the first clock ck 1 contains two differential signals ck 1 1 ck 1 2 then the first clock ck 1 1 represents the phases 0 degree along with 180 degrees i e i phase and the first clock ck 1 2 represents phases 90 degrees along with 270 degrees i e q phase in this case the composition of the controller is shown in fig1 since the operations of components are substantially similar as those in fig9 we do not repeat their descriptions with reference to fig1 when the incoming data data enters the cdr circuit samples it based on the second clock ck 2 to obtain recovered data not shown suppose the input frequency of the incoming data data is fd i e the first frequency then the cdr circuit produces the second clock ck 2 with a second frequency which is fnom fbb when fd is smaller than fnom fbb the sampling point is shifted to the left therefore in order to cover the sampling edge of the second clock ck 2 the first clock ck 1 with multiple phases i phase q phase can form a sampling region w which is smaller.