shown for full adders 114 and 115 in fig4 for purposes of illustration fig4 assumes that the fifo array 100 comprises seven fifos 101 in such an arrangement each synchronizing mechanism 110 or 111 comprises two full adder circuits 114 and 115 of fig2 an output terminal of each of the fifos 101 is connected to the circuits 114 and 115 at any of the input terminals c0 and a1 a4 of the one circuit 114 and at any of the input terminals a1 a4 of the other circuit 115 the unused of these input terminals are connected to one or more of the used of these input terminals in the manner described for fig3 the output terminal c4 of the one circuit 114 is connected to the input terminal c0 of the other circuit 115 and the external terminals b1 b4 of both circuits 114 and 115 are connected together and to the output terminal c4 of the circuit 115 the terminal c4 of the circuit 115 then connects to an input terminal of each of the fifos 101 should ten or more fifos 101 be utilized in the fifo array 100 further circuits of fig2 may be cascaded in the manner shown in fig4 to provide.