is received from one of the i o buses 14 a u2013 14 n and stored by one of the processors 12 a u2013 12 n in one of the buffers 18 a u2013 18 n of the first memory 18 the processor e g processor 12 a identifies one of a set of i o buffers 16 a u2013 16 n for transmitting the packet from the data buffer 18 a u2013 18 n out of system 10 each of the i o buffers 16 a u2013 16 n is associated with one of the i o buses 14 a u2013 14 n often the i o port chosen for transmitting a packet stored in an i o buffer is busy receiving or sending packets for other i o buffers in this case the system 10 includes a second memory 20 for storing the packet the second memory 20 stores a queue array 24 the queue array 24 has buffer descriptor addresses bdas for packets that are stored in data buffers 18 a u2013 18 n of the first memory 18 and are waiting for an assigned i o buffer 16 a u2013 16 n to become available each data packet received may vary in size therefore the size of each data buffer 18 a u2013 18 n may also vary in size furthermore each data buffer 18 a u2013 18 n may be logically partitioned by a processor 12 a u2013 12 n into one or more u201c cells u201d each cell partition represents a maximum size of a data packet that may be transmitted by an i o buffer 16 a u2013 16 n for example data buffer 18 a is partitioned into two cells data buffer 18 b includes one cell and data.