is a burst interface 16 will continue to drive data onto bus 12 by fetching it from register 24 if however this transaction is a single cycle write interface 16 will close the transaction on bus 12 and load an acknowledgment into register 20 since this acknowledgment need not carry data or address information a unique code may be placed into register 20 so that encoder 28 can appropriately tag this line before parsing it into frames for transmission over link 46 upon receipt decoder 30 will produce a unique code that is loaded into register 22 and eventually forwarded to interface 14 which sends an acknowledgment to the device on bus 10 that the write has 10 succeeded if the initiator instead sets its control bits during the address cycle to indicate a read request interface 14 would also accept this cycle if it has jurisdiction interface 14 will also signal the initiator on bus 10 that it is not ready to return data e g a retry signal which may be the stop signal as defined under the pci standard the initiator can still start but not finish a data cycle by driving its signaling lines on bus 10 with byte enable information using the same technique the address information followed by the byte enable information will be accepted by interface 14 and loaded with tags into register 18 these two lines of information will be then encoded and transmitted serially 20 over link 40 upon receipt this information will be loaded into the stack of register 24 eventually interface 16 will notice the first item as a read request.