hole cl 1 in the fuse area fu and opening o 2 corresponds to the second contact hole cl 2 in the pad area pa the etching of the first and second contact holes cl 1 ci 2 is simultaneously performed like in the first embodiment and particular stops on the second cap layer c 2 u2032 arranged on the contact pad p 1 in the pad region pa in the fuse region fu the etching proceeds to the above mentioned desired remaining depth of the second insulating layer i 2 above said fuses f 1 f 2 f 3 in contrast to the first embodiment the second cap layer c 2 u2032 is conductive therefore the selectively formed second cap layer c 2 u2032 may be used as protection layer during wafer testing on the other hand the second cap layer c 2 u2032 may also be removed or partially removed from the second contact hole cl 2 as depicted in fig2 d if the second cap layer c 2 u2032 is left on the contact pad p 1 it may still be intact after wafer probing and provide oxidation corrosion protection of the contact pad p 1 until packaging whether this is the case depends on.