strained channel layers preferably by a cvd process step 318 the channel may be si ge sige or a combination of multiple layers of si ge or sige above the device isolation trenches or regions the deposited channel material typically will be polycrystalline alternatively the device channels may be deposited selectively i e only in the device active area and not on top of the isolation regions typically the remaining steps in the transistor fabrication sequence will involve lower thermal budgets and little or no surface material consumption next the transistor fabrication sequence is continued with the growth or deposition of a gate dielectric step 320 and the deposition of a gate electrode material step 322 examples of gate electrode material include doped or undoped polysilicon doped or undoped poly sige or metal this material stack is then etched step 324 forming the gate of the transistor typically this etch removes the gate electrode material by a process such as reactive ion etching u201c rie u201d and stops on the gate dielectric which is then generally removed by wet etching after this the deposited channel material typically is still present next the transistor spacers are formed by the traditional process of dielectric material deposition and anisotropic etching step 326 step 326 may be preceded by extension implantation or removal of the channel material in the regions not below the gate or both if the channel material is not removed before spacer material deposition the spacer etch may be tailored to remove the excess channel material in the regions not below the gate failure to remove the excess channel material above the.