voltage which in one aspect of the invention is approximately 6 25 volts because transistor 12b is in a conducting state it couples the second programming voltage to the drain of cl2 thus cl2 is programmed to a logic 1 state because transistor 12a is nonconducting transistor 20a remains in an unprogrammed state upon initial power up or upon the return from an interruption in the power supply the inputs to both inverters 10a and 10b are at a logic low thus switches 14a and 14b are in the closed or conducting state because cl1 is in an unprogrammed state as soon as the voltage v dd which is coupled to the gate of transistor 20a reaches a predetermined threshold voltage which in one aspect of the invention is approximately 2 0 2 4 volts transistor 20a conducts and through switch 14a drives the input or b1 to a logic 0 thus via transistor m2 cl1 drives the input b2 to a logic 1 and thus upon power up non volatile memory cells cl1 and cl2 serve to set the latch circuit in the desired state once the latch is set transistors m2 and m3 conduct while transistors m1 and m4 do not thus.