and the voltage across resistor rl is accurately referenced to a master voltage reference not shown each adc 18 is connected to the master voltage reference as will be described shortly the reference voltages swvr da and vrda though separate are automatically and continually referenced individually e g each within a mv against the master voltage reference not shown through a sequence of steps which are described below thus each adc 18 is automatically made very accurate within its own cycle of operation and the multiple operations of all of the adcs 18 in assembly 10 are tied together with equal automatically obtained accuracy from the single master voltage reference the clock pulses ck and the phases p 0 to p 15 produced by the timing unit 36 see fig1 during a cycle of operation of each adc 18 of fig1 each clock pulse ck is in the form of an asymmetrical square wave having a 34 high 34 state 60 a 34 low 34 state 62 and a duration period 64 this duration 64 may for example be 20 nanoseconds a clock pulse ck goes from low to high in voltage at a rising leading edge 66 occurring at the beginning of a clock period 64 and from high to low at a falling trailing edge 68 the zero 34 0.