material such as sio 2 or other high k dielectric materials such as any one of sion hfalon hftaon hfsion and al 2 o 3 etc according to an embodiment of the present disclosure the gate dielectric layer material 107 may be hfsion formed by any one of low pressure chemical vapor deposition metal organic chemical vapor deposition and atom layer deposition the gate dielectric may have an equivalent oxide thickness of about 5 100 u00e5 the gate electrode material 108 may be any one of refractory metals such as w ti ta mo metal nitrides such as tin tan hfn mon etc and other materials the gate electrode material may be formed by any one of low pressure chemical vapor deposition metal organic chemical vapor deposition and atom layer deposition etc the gate electrode material may have a thickness of about 2000 5000 u00e5 optionally after forming the gate stack structure the method may further comprise forming source drain extension regions in the fin by tilt angle ion implantation or forming halo implantation regions in the fin by tilt angle ion implantation next gate spacers may be formed at sidewalls of the gate stack in accordance with regular methods a detailed explanation thereof is omitted next source drain regions may be formed by ion implantation in the semiconductor substrate on both sides of the gate stack also source drain silicide is.