register 91 and p 3 is transferred as r 3 to the register 97 in a second cycle the adder 81 adds the content of the register 92 and that of the register 94 and multiples by 1 2 and the obtained result is stored as q 2 in the register 93 also the adder 83 adds the contents of the registers 94 and 96 and multiplies by 1 2 and the obtained result is stored as r 1 in the register 95 in a third cycle the adder 82 adds the contents of the register 93 and 95 and multiples by 1 2 and the obtained result is stored as q 3 r 0 in the register 94 at this point q 0 is stored in the register 91 q 1 in 92 q 2 in 93 q 3 r 0 in 94 r 1 in 95 r 2 in 96 and r 3 in 97 in this manner the 1 2 division as in fig2 can be executed within three clock cycles in a fourth cycle the convergence discrimination circuits 121 122 discriminate whether q 0 q 3 and r 0 r 3 are in the converged state and the process varies according to.