particular channel with a fixed timing in the control latch means the channel number is compared with the particular channel number to which the control latch means for control is connected and the latch circuit for demultiplexed signals is controlled in accordance with the difference between the channel numbers the first embodiment of the present invention is explained further with reference to the detail structure of fig5 in fig5 is a shift register 22 is a control latch part 23 is a counter circuit 24 is a frame synchronization multiplex channel number discriminating part 25 is a timing control part 26 is a latch part for demultiplexed signals fig6 is a timechart for multiplex isolation in the embodiment of fig5 a multiplexed input data is read into the shift register 21 in accordance with the clock and thereby the outputs sr1 sr2 srn which are each shifted by one bit sequentially are generated in parallel the control latch part 22 latches an output of a particular channel for instance srn in accordance with a fixed timing signal ph1 of the counter circuit 23 which counts up the clock and generates an output the frame synchronization multiplexing channel number discriminating part 24 establishes frame synchronization for the output of control latch part 22 and discriminates its multiplexing channel number if the discrimination result is a multiplexing channel number k it is shifted by k n bits for the multiplexing channel number in the sending side therefore the timing control part 25 generates the demultiplex timing signal phc which is shifted by k n bits from the write clock in.