performed to implant a heavy dosage of dopants into the semiconductor substrate 302 conventionally a step of annealing would be performed immediately following the ion implantation however the present invention suggests performing the annealing several steps later for benefiting a formation of a resist protect layer the detail will be explained below note that while performing ion implantation and annealing in a consecutive order is not suggested it is still an option for the present invention and therefore falls in the scope of the same referring to fig6 an original nitride layer 311 is blanketly deposited over the gate electrode 305 source drain regions 310 isolation 301 and resistor 307 by using the term u201c original u201d it suggests that the original nitride layer 311 will be further processed as a resist protect layer in the following steps the etch rate of the original nitride layer for a certain etching solution can be adjusted by optimizing process conditions such as temperature pressure flow precursor and deposition methods it is understood that the etch rate increases when the temperature decreases and the pressure as well as flow increases thus by performing a deposition in a relatively low temperature with other process conditions properly adjusted the original nitride layer 311 can achieve a high etch rate in this embodiment the composition of the original nitride layer 311 includes but not limited to silicon nitride oxynitride and a nitride layer doped with carbon boron ge as etc the step of deposition may be low pressure chemical vapor deposition lpcvd rapid thermal chemical vapor deposition rtcvd plasma enhanced.