be readily apparent to those skilled in the art and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention thus the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features disclosed herein fig1 illustrates an exemplary sequence of instructions which demonstrates the interaction of deferred queue 410 see fig4 and deferred sram 409 with architectural register file arf 412 and working register file wrf 413 for the purposes of this example deferred queue 410 and deferred sram 409 are initially assumed to be empty note that the progression of time is downward so that instructions that are issued later appear lower in the figure as fig1 shows there is a series of instructions which start with a load instruction 100 that is attempting to load from an address in processor register r 5 to processor register r 7 this load results in a miss since load instruction 100 misses and is hence subject to an unresolved data dependency load instruction 100 is deferred into deferred queue 410 and the processor enters execute ahead mode during execute ahead mode the following add instruction 101 which has a data dependency with load instruction 100 is also deferred to deferred queue 410 in an alternative implementation of the present invention the unresolved load instruction 100 is not deferred instead the processor waits until it encounters an instruction which has a data dependency on the unresolved load instruction 100 namely add instruction 101 at this point the processor defers add instruction 101 and enters execute ahead mode next the processor issues a large number of instructions in execute ahead mode some of.