this value is relatively small and the voltage difference vr is higher compared to the case with the resistor r in this way the comparator 120 is driven in a more advantageous way by a higher input voltage as explained in the following the abovementioned features can be observed referring to fig5 which illustrates the simulated evolutions in time of the potentials of the node yms and the output outdif 1 of the amplifier 110 in the sensing circuit 300 during both the precharge and the evaluation phases more in particular it can be seen that the voltage difference vr between the node yms and the output outdif 1 remains higher than in the case illustrated in fig2 for almost all the time during the evaluation phase when the selected memory cell mc begins draining the current ibl the potential of the node yms tends to lower in this way the transistor d 2 starts to turn off decoupling the output outdif 1 from the node yms in such a way to speed up the variation of the output outdif 1 in fact the evolution in time of the potential of the output outdif 1 in the proximity of the inversion time it is steeper than in the case illustrated in fig2 this feature makes the sensing circuit 300 less susceptible to disturbances and in particular less susceptible to spurious and unpredictable variations of the reference current iref in fact a different reference current iref would vary the potential assumed by the output outdif 1 at the end of the precharge phase varying in turn the inversion time it and consequently the switching instant.