gate pattern 220 thereby obtaining a source drain region 230 in order to prevent a hot carrier effect hce the source drain region 230 is neither deeply formed nor expanded to a lower portion of the gate pattern while the doping concentration is decreased by the ion implantation process referring to fig2 b a spacer 228 is formed at sidewalls of the gate pattern 220 after the spacer 228 is formed a local halo region 240 is formed in the bottom portion of the source drain region 230 located at the upper silicon layer 214 through an ion implantation process unlike the conventional art an ion tilt implantation process is not performed rather a vertical ion implantation process i e a process wherein the tilt angle is zero degrees is used to form the local halo region 240 as a result it is easy to form the local halo region 240 in the bottom portion of the source drain region 230 located between the neighboring gate patterns 220 even though the design rule is reduced referring to fig2 c after the ion implantation process forms the local halo region 240 a thermal treatment process is performed as a result the local halo region 240 is diffused vertically and thus is expanded into the lower insulating oxide layer 212 the local halo region 240 is also diffused horizontally to penetrate into the lower region of the spacer 228 formed at sidewalls of the gate pattern 220 referring to fig2 d an oxide film 250 that protects the gate pattern is formed the oxide film 250 is formed over the structure including the gate pattern and a self aligned etching process is performed thereby forming a cap type oxide film.