clock pad 147 are formed over the first substrate 110 in the non active area na the data pad 146 and the clock pad 147 are disposed at an outer portion of the seal pattern 180 the data line 128 is connected to the data pad 146 and the clock line 117 is connected to the clock pad 147 since the second substrate 150 has a sized smaller than the first substrate 110 the data pad 146 and the clock pad 147 are exposed through the second substrate 150 and signals are applied to the data pad 146 and the clock pad 147 for example a clock signal may supplied to the gate driving circuit through the clock pad 147 the clock line 117 and the connection line 135 and a data signal may be supplied to the source electrode 130 of the pixel tft tp through the data pad 146 and the data line 128 the gate driving circuit may generate a gate signal using the clock signal and may supply the gate signal to the gate electrode a data signal are supplied to the gate electrode 115 of the pixel tft tp a black matrix 153 is formed on an inner surface of.