polysilicon followed by an isotropic etching of the patterned photoresist to reduce linewidth and then an anisotropic etcing of the oxynitride plus polysilicon to form gates and gate level interconnects and lastly overlying metal interconnects are formed using patterned photoresist without linewidth reduction but using a differing composition silicon oxynitride as antireflective layer due to the differing underlying material reflectivity the index of refraction and the extinction coefficient real and imaginary parts of the square root of the dielectric constant of silicon oxynitride vary with the composition see fig2 thus essentially select the composition to have optical constants that adjust the reflected waves amplitudes according to the underlying material reflectivity and select the oxynitride layer thickness to provide quarter wave interference so the reflected waves cancel the resultant integrated circuit may include residual silicon oxynitride on the gates or interconnects or both or neither fig1 a m illustrate in cross sectional elevation views the steps of a first preferred embodiment fabrication methods for integrated circuits including field effect transistors e g cmos or bicmos the example is of lithography which has 0 25 u03bcm minimal linewidth and a circuit with 0 25 u03bcm minimal metal interconnect width together with 0 18 u03bcm minimal silicided polysilicon linewidth gate length the preferred embodiment includes the following steps 1 start with a silicon or silicon on insulator wafer 102 with locos or shallow trench isolation and twin wells for cmos devices optionally plus memory cell array.