with the clock equivalent to the speed of the original data sequences the read out branch metric signals are fed to a path metric calculator 75 via a d flip flop 741 the path metric calculator 75 a path memory 76 and a decoder output decision circuit 77 process error correction decoding with viterbi algorithm in a manner similar to the prior art maximum likelihood decoder and output decoded data to an output terminal 9 the second embodiment of this invention having a convolutional encoder 3 and a maximum likelihood decoder 7 corresponding thereto will now be described as having fig6 is a block diagram of a convolutional encoder in the second embodiment of this invention which corresponds to the convolutional encoder shown in fig1 an input terminal 1 is connected to a serial parallel converter 300 which distributes serial data sequences into 7 sequences to be outputted to shift registers of 2 bits 310 311 312 313 314 315 and 316 the input of a modulo 2 adder 320 is connected to the second bit of shift registers 310 311 313 314 and 316 the input of a modulo 2 adder 321 is connected to the second bit of shift registers 310 313 314.