and 26 are preferably doped to n type to a depth for use as a source drain the n type doping can be achieved using phosphorus or arsenic for p channel operation doped regions 22 24 and 26 can be doped to p type instead of n type shown in fig4 is storage device structure 10 after removal sidewall spacers 18 and the portion of oxide layer 14 between the nitride layers this can be achieved with a wet hf etch which is highly selective between nitride and oxide shown in fig5 is storage device structure 10 after forming a layer of a storage layer 28 which in this example comprises a nanocrystals in a dielectric shown in fig6 is storage device structure 10 after formation of a gate layer 30 this is shown as a planar layer but it may also be formed as a conformal layer gate layer 30 may also be a stack of different conductive layers gate layer 30 is preferably a metal that is deposited by plating but could be another material and could be deposited by another method for depositing a layer that can be useful as a gate in the case of plating a seed layer not separately shown would be formed before the plating of ultimate gate layer 30 in this example the metal is preferably tungsten shown in fig7 is storage device structure 10 after a planarizing process that removes gate metal layer 30 from over patterned nitride layer 16 this leaves control gates 32 34 36 and 38 between formed from gate layer 30 between patterned nitride layer 16 chemical mechanical polishing cmp using nitride as the etch stop is preferably used for the planarizing another etch back process may alternatively be used shown.