the new image being compared with the previous in this way the two pages of memory are continually being recycled and updated with the former page being updated with the most recent image a more thorough understanding of the image capture process can be obtained by examining fig6 which is a block diagram of image capture controller 12 the composite video from camera 6 contains both image information and scanning synchronization signals these signals can be separated from the video using sync separator 18 which may be a national semiconductor lm 1881 the output from sync separator 18 provides both horizontal sync signals and vertical sync signals hor and vert respectively these are combined with the sampling commands sc from computer 14 by image storage controller 20 to produce a sequence of memory addresses and a write command pw from pixel write image storage controller 20 consists of logic circuitry which generates addresses in the proper sequence for image storage addresses are generated and sequenced according to the input signal combinations of hor vert and sc each sampling command sc causes the next address to be generated in addition when hor is present the next address to be qenerated represents the beginning of a new line the presence of vert indicates.