rise from the 34 l 34 level and reach the 34 h 34 level at t 11 during the time interval t 9 t 11 when the voltage v 4 at the node n 4 drops below the threshold voltage of the fet 4 the fet 4 is driven into conduction in consequence the high level output signal v out at the node n 2 starts to fall at t 10 subsequent to the lapse of the delay time provided by the cmos inverter i 2 and it attains the 34 l 34 level at t 12 in comparing the time interval t 3 t 4 during which the voltage v 4 at the node n 4 falls from the 34 h 34 level to the 34 l 34 level with the time interval t 9 t 11 where the voltage v 4 rises from the 34 l 34 level to the 34 h 34 level it is obvious from fig5 b that the rising time interval t 9 t 11 is longer than the falling time interval t 3 t 4 this is chiefly because of the fact that the threshold voltage of the n channel mosfet 6 increases as its source to bulk voltage increases thus in a situation where the voltage v 3 at the.