data is first written via sdi and the circuit 23 to the selected register unit 22 i 1 u2266 i u2266 n and thereafter in response to each low level of scw the register units 22 i 1 22 i 1 22 i 2 are sequentially selected by the addressing circuit 21 and write data are written thereto from the circuit 23 one by one the data written into the register section 22 through this serial write cycle t sw are written into the respective digit lines of the memory array 10 at the subsequent write data transfer period t wd2 in response to a low level of wdt during a read data transfer period trd 1 and ras and rdt are changed low in level so that all the transfer gates in the transfer gate section 31 are enabled and data on the respective digit lines are written into the line buffer section 32 in parallel while also during this period t rd1 column address information ac is applied to the addressing circuit 33 for determining the initial column address to be accessed first in the subsequent serial read cycle t sr in the serial read cycle t sr data stored in the storage unit 32 i corresponding to the above initial column location is first selected by the addressing circuit 33 and outputted to s do via the output circuit 34 and thereafter data stored by the storage units 32 i 1 32 i 2 are sequentially selected by the addressing circuit 33 in synchronism with the respective changes of scr to a low level and outputted to s do in order.