the drawing the memory cell for phines like cells has for example a bottom oxide with a thickness ranging from 2 nanometers to 10 nanometers a charge trapping layer with a thickness ranging from 2 nanometers to 10 nanometers and a top oxide with a thickness ranging from 2 nanometers to 15 nanometers in some embodiments the gate comprises a material having a work function greater than the intrinsic work function of n type silicon or greater than about 4 1 ev and preferably greater than about 4 25 ev including for example greater than about 5 ev representative gate materials include p type poly tin pt and other high work function metals and materials other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to ru ir ni and co metal alloys including but not limited to ru u2014 ti and ni t metal nitrides and metal oxides including but not limited to ruo2 high work function gate materials result in higher injection barriers for electron tunneling than that of the typical n type polysilicon gate the injection barrier for n type polysilicon gates with silicon dioxide as the top dielectric is around 3 15 ev thus embodiments of the present technology use materials for the gate and for the top dielectric having an injection barrier higher than about 3 15 ev such as higher than about 3 4 ev and preferably higher than about 4 ev for p type polysilicon gates with silicon dioxide top dielectrics the injection barrier is about 4 25 ev and the resulting threshold of a converged cell is reduced about 2 volts relative to.