26a of a nand gate 26 and to a second input 22b of the gate 22 the output 20c of the gate 20 is connected to the reset inputs r of the seconds counter 3 and the frequency divider 2 the counter 21 is combined in manner known and here not described with a decoder whose three outputs 21b 21c and 21d take the logical 34 1 34 state successively and individually when the counter 21 is in its states 0 1 and 2 respectively the output 21b is connected to the input 27a of a nor gate 27 the output 21c is connected to the input 11a of the circuit 11 through an inverter 28 and to the input 24b of the gate 24 the output 21d is connected to the inputs 18b 22c and 23b of the gates 18 22 and 23 and also to the input 11b of the circuit 11 through an inverter 29 the outputs 22d 23d and 24c of the gates 22 23 and 24 are connected to the inputs 4b 6b and 9b respectively of the gates 4 6 and 9 the output 25c of the gate 25 is connected to the inputs 8b 27b and 31b of the gates 8 27 and 31 and the output 26c of the gate 26 is connected to the inputs 19b and 23c of the gates 19 and 23 the output 27c of the gate 27 is connected to the inputs 20b and 25b of the gates 20 and 25 while finally the input 26b of the gate 26 is connected to the output 5b of the minutes units counter 5 through an inverter 30 the circuit operates in the following manner at normal times that is to say as long as the user.