the jammer timeout period has elapsed the second independent process includes steps 506 507 508 and 509 in step 506 the digital jammer detection circuit samples the output of comparator 105 and determines if the sampled output is a logic high signal if the sampled output is not a logic high signal the counting is stopped and current count value is maintained in step 507 the slave counter determines the average time the jammer was present in step 508 the digital jammer detection circuit determines if the peak counter value is greater than the programmed peak threshold value in step 509 a jammer interrupt signal is sent and a reset request generated sending the process back to step 501 the digital jammer detection circuit determines if an external reset request has been made an external interrupt may be initiated by different events such as single wire bus interface sbi overwrite global device reset or gain mode transition fig6 a and 6b show two different digital logic configurations for implementing digital jammer detection circuit 360 in accordance with an exemplary embodiment block 600 is the initialization logic which generates a digital jammer detection circuit reset signal when any of the following inputs are triggered global reset gain mode transition sbi override or digital jammer detection circuit timeout in fig6 a block 601 is an sr latch circuit an sr latch circuit is an arrangement of logic gates that maintains a stable output after the inputs have been.