clock correction unit every time the reference clock is generated certain times which is equal to a second integer determined in accordance with a difference between the above mentioned ratio and the first integer the clock correction unit temporarily hinders passage of the reference clock to the counter even if one bit time is not a multiple of the reference clock the communication machine can transfer the data at high speed without increasing the reference clock frequency application_number US 28314902 A description embodiments of the present invention will be described with reference to the accompanying drawings referring to fig1 a uart according to a first embodiment of the present invention is illustrated similar reference numerals are used to designate similar elements in fig1 and 9 and description of such elements is omitted different and new elements as compared with the uart shown in fig9 are only described below the uart of the first embodiment includes two additional elements namely a correction counter 6 and an or gate 7 the correction counter 6 includes a correction count register 6 a for storing a correction count set value a correction counter auto reloadable counter 6 b for counting the reference clock clk up to the correction count set value and a flip flop 6 c for capturing a signal outputted from the correction counter 6 b during the rising edge of the next reference clock clk every time all bits in the correction counter 6 b become u201c 1 u201d i e every time the reference clock clk is counted up to the correction count set value in order.