similarly a multiplexer mux 110 receives a global clock signal c and a local clock signal c and the output of the mux 110 drives the clock input of the latch 100 additionally a multiplexer mux 112 receives a global reset signal r and a local reset signal r and the output of the mux 112 is provided to the reset control of the latch 100 the output 106 of the latch 100 is an and function of the local signals e c and r and the input 102 input 102 may be an output of a programmable logic block an output of a register or a global input signal fig3 shows an exemplary logic block based latch 120 in this latch a look up table lut 124 receives inputs b 2 b 3 and b 4 respectively similarly lut 122 receives inputs b 5 b 6 b 7 the outputs of the luts 122 amp 124 are provided to a mux 126 which is controlled by input b 1 the output of mux 126 is provided to another mux 128 which receives b 0 at a second input the output of the mux 128 is provided to the input of a latch 130 turning now to the control signals for the latch 130 a multiplexer mux 136 receives a global enable signal e and a local enable signal e and the output of the mux 136 is provided to the enable control of the latch 130 similarly a multiplexer mux 132 receives a global clock signal c and a local clock signal c and the output of the mux 132 drives the clock input of the latch 130 additionally.