caches present difficulties since for testing purposes they are conventionally regarded as separate ram and cam arrays the disclosed test engine tests the cache as a whole in the test mode cache writes are absolutely addressable selecting a particular entry in a particular way set during each operation using line addressing and common tag data this enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting application_number US 17304802 A description the various aspects of the invention disclosed herein relate to a built in self test unit and or associated test procedures for testing a cache memory which provide a unified test of the entire cache system reference now is made in detail to the presently preferred embodiments of the invention examples of which are illustrated in the accompanying drawings and discussed below 0028 fig1 illustrates a portion of an integrated circuit ic for example a portion of a programmable processor the illustrated portion of the ic includes a cache memory block 11 the invention is applicable to self testing of any type of cache memory in the illustrated example the cache memory 11 under test is an instruction cache memory block the other elements shown in fig1 are elements of a built in self.