max plus ii version 6 0 state machine syntax any arbitrary state machine has a set of states and a set of transition rules for moving between those states at each clock edge the transition rules depend both on the present state and on the particular combination of inputs present at the next clock edge the altera epld 22 used in the preferred embodiment contains enough register bits to represent all possible states and enough inputs and logic gates to implement the transition rules a general transmit program flow diagram 70 for the transmit state machine is shown in fig8 within the general flow diagram 70 are three state machine diagrams for the inquire 74 arbitrate 76 and transmit 78 phases of the transmit state machine the processor module cpu 32 initiates the inquire phase 74 as shown in fig9 eight states are shown along with the transition rules necessary for the bus controller 22 to sense bus activity after initiation a transmit request is forwarded to the bus controller 22 to see if there is bus activity the bus controller 22 monitors the arbitration bus 50 for a minimum of 7 clock cycles six internal bus controller addresses are examined for collisions if no collisions are detected a request to arbitrate is made on the inactive bus as shown in fig1 the arbitrate request sets a flip flop 80 and begins sending out a unique identifier followed by six address bits on the arbitration line hsbi_arb 1 _n 50 a collision is detected if any of.