memory and provides an interface to the memory for external devices the digital processor the latch circuit the input interface and the error correction circuit are all formed on a single substrate application_number US 35496199 A description fig5 is a schematic block diagram of a code error correcting apparatus 10 according to one embodiment of the present invention the code error correcting apparatus 10 includes a digital processor 11 a latch circuit 12 an input interface circuit 13 an error correcting and detecting circuit 14 an output interface circuit 15 and a latch clock generator 16 the code error correcting apparatus 10 including the circuits 11 to 16 is preferably integrated on a single semiconductor substrate and connected to a control microprocessor 30 the input interface circuit 13 the error correcting and detecting circuit 14 and the output interface circuit 15 are connected to a buffer ram 20 the control microprocessor 30 and the buffer ram 20 are preferably integrated on another single semiconductor substrate the input interface circuit 13 the error correcting and detecting circuit 14 and the output interface circuit 15 comprise a cd rom decoder 19 the digital processor 11 receives an efm signal from an analog signal processor and generates cd rom data by performing processes such as efm demodulation and circ decoding on the efm signal at the same time the digital processor 11 generates a channel identification signal lr indicating the switching timing of the cd rom data in accordance with each process time the digital processor 11 processes each 8 bit symbol data then transfers the cd rom data to the latch circuit 12 in units of 16 bits the latch circuit 12 receives the cd rom data from the digital processor 11 and latches the cd.