28 however the spacing between adjacent memory cells in the y plane which is shown in fig2 a through 2h is on the order of 0 6 microns between adjacent storage electrodes 28 these dimensions result in a cell size of approximately 1 4 microns by 1 8 microns or slightly greater than 2 5 square microns per cell assuming a 0 8 micron diameter trench and the trench to trench spacings discussed previously an important technical advantage of the present invention is that access to the buried wordline of the memory cell is conveniently and efficiently available and only requires the use of the substrate surface area occupied by a single memory cell the filament channel transistor used as the pass gate transistor in each of the memory cells of the present invention contain several technical advantages the substantially cylindrical shape of the filament channels 32 enable the pass gate transistors to be very sensitive to small changes in gate voltages placed on the wordline conductors 38 because the wordline conductors 38 completely surround the cylindrical filament channels 32 it is possible to completely delete or completely invert the semiconductor material contained in the filament channels 32 depending upon the mode of operation desired further the general vertical orientation of the filament channels 32 enables the extremely small cell sizes of the present invention further the novel method of accessing the buried wordlines of the memory cell further allows for efficient access to the gates of the pass gate transistors while occupying a minimum of the substrate surface area in summary a memory cell is provided which comprises a trench capacitor formed in a semiconductor substrate a storage electrode of the trench capacitor is coupled to a filament channel which is insulatively surrounded.