f d between the received data clock f r and frequency f n is a prescribed value namely the output of the frequency accumulator 80 indicates whether the recovered clock is running faster or slower than the clock embedded in the received data signal where the output clock clko is running faster than the received signal rx the state of the overflow underflow output 81 of the accumulator 80 will cause the multiplexer 30 to incrementally advance or step through the plurality of output ports 32 1 32 2 32 n of the delay line 20 as will be described below with reference to the timing diagram of fig3 this has the effect of lengthening one of the half cycles of the output recovered clock signal thereby slowing down the recovered clock on the other hand where the output clock clko is running slower than the received signal rx the state of overflow underflow output 81 of the accumulator 80 will cause the multiplexer 30 to incrementally reverse through the plurality of output ports 32 1 32 2 32 n of the delay line 20 as will be described below with reference to the timing diagram of fig4 this has the effect of shortening one of the half cycles of the output recovered clock signal thereby speeding up the recovered clock more particularly fig3 shows a set of three phase delayed versions of the fixed input clock signal clki as produced at output ports 32 1 32 2 32 n of the fraction delay line 30 where n 4 since n 4 each successive version of the input clock signal is delayed by 90 u00b0 relative to its immediately preceding version of the input clock.