bus or an sio bus embedded system 13 comprises a microprocessor 12 and memory module 14 including download module 18 embedded memory 16 memory check module 20 and erase module 22 embedded memory 16 may be a serial or parallel flash memory storing firmware that microprocessor 12 operates accordingly embedded memory 16 may be embedded in a multi chip module mcm or in a system on chip soc design download module 18 and memory check module 20 together form a gate guard to determine whether the memory data in the embedded memory 16 can be released to host 10 erase module 22 can erase the memory data in the embedded memory upon an erase_trigger signal an embodiment of the invention prevents the release of the memory data in embedded memory 16 to host 10 if embedded memory 16 is not u201c empty u201d embedded memory 16 is presumed not to be empty if the memory data does not meet a criterion for example if the memory data is all 0s or all is embedded memory 16 is determined to be empty because firmware generally includes code with 0s and 1s mixed together in other words if the memory data has a predetermined pattern it may be determined to be empty other methods of determination are possible for example if the memory data is concluded to have a cyclic redundancy check crc the same as a predetermined result embedded memory 16 is presumed to be empty accordingly memory check module 20.