to lines 64 and 65 it can now be appreciated how the direction of current flow through the winding of the solenoid reed valve used in the present invention can be alternated referring to fig2 if q output 63 is first assumed to be high then not q output 61 is low and thus inputs 73 and 74 of and gates 77 and 78 respectively are negative and inputs 71 and 72 of and gates 75 and 76 respectively are positive therefore as transistors 80 and 81 are connected to and gates 75 and 76 respectively as seen in fig2 transistors 80 and 81 are switched on thus current will flow from point 82 at 9 volts into collector 83 and out of emitter 84 of transistor 80 through the winding of valve means 10 represented schematically at point 90 in a direction from point 85 to point 86 and then into collector 87 and out of emitter 88 of transistor 81 to ground at point 89 at the next positive edge entering clock input c 57 q output 63 goes from high to low and not q output 61 goes from low to high thus inputs 71 and 72 of and gates 75 and 76 go from positive to negative thereby turning off transistors 80 and 81 and inputs 73 and 74 go from negative to positive thereby turning on transistors 91 and 92 current can now flow from point 82 into collector 93 and out of emitter 94 of transistor 91 through.