transistor q 1 which forms an input gate stage an npn type inverter transistor q 2 used for an output stage resistors r 1 r 2 r 3 and so on in the circuit of fig1 when one or more of the input signals input to the emitters of the transistors q 1 is low the current flowing from a power source v cc through the resistor r 1 flows into the emitter whose potential is rendered low so that the potential of the collector of the transistor q 2 is cut off and an output signal out becomes high if all the input signals in 1 in 2 and in 3 are high the collector voltage of the transistor q 1 becomes high and the transistor q 2 is turned on therefore the output signal out becomes low fig2 is a circuit diagram of another example of an inner gate circuit used in a conventional gate array lsi device the circuit of fig2 differs from that of fig1 in that an npn type buffer transistor q 4 is inserted between an input multi emitter transistor q 3 and an output inverter transistor q 5 so as to increase the drive ability of the output inverter transistor q 5 and to some extent prevent the switching speed from deteriorating due to the capacitive load as mentioned earlier these inner gate circuits have the disadvantages of large input currents which cause a decrease in the fan out number and cause considerable dependency of the rise time on the load capacitance according to the present invention there is provided a gate array lsi device which overcomes these problems fig3 is a circuit diagram of a structure of a transistor transistor logic ttl inner gate circuit used in a gate array lsi device.