under the second floating gate 53 b is defined as a second channel a second gate insulating film 55 is formed on the semiconductor substrate 51 inclusive of the first and second floating gates 53 a and 53 b in a first direction a first control gate 56 a is formed on the second gate insulating film 55 covering a top portion and one side of the first floating gate 53 a a second control gate 56 b is formed on the second gate insulating film 55 covering a top portion and one side of the second floating gate 53 b in this embodiment the first and second control gates 56 a and 56 b are isolated from each other the first floating gate 53 a and the second floating gate 53 b are electrically floated by the second gate insulating film 55 a cell array of nonvolatile memories of the present invention in which the aforementioned flash memory cell is employed as a unit cell will be explained next referring to fig5 b and 6 the cell array of nonvolatile memories includes a matrix of flash memory cells each having first and second floating gates 53 a and 53 b first and second control gates 56 a and 56.