wesley peterson 34 error correcting codes 34 the m i t preses pp 149 152 1961 ref 7 when the call numbers in the memory 35 has been cleared the memory 35 provides an output signal to the timing circuit 34 the timing circuit 34 stops the circuits 35 36 and 39 in response to this signal and at the same time starts the end mark signal generator 38 for example for 0 93 seconds as shown in fig2 b and 2 c the end mark signal is transmitted three times while repeating 31 bits of all 34 0 34 and 31 bits of all 34 1 34 as shown in fig2 e this end mark signal generator 38 can be composed of a 31 bit clock counter and a flip flop adapted to be inverted in state by the output of the clock counter when the transmission of the end mark signal has been terminated the timing circuit 34 is stopped until the next call number is fed to the memory 35 since the above described signal group consisting of the preamble signal calling signal and end mark signal is not transmitted if the calling signal is absent the time intervl between the signal groups s s.