been patterned to produce gates 201 and 205 together with runner 203 which extends over field oxide 113 thus it will be noted that fig1 15 depict the formation of two adjacent transistors separated by field oxide 113 furthermore gate level runner 203 extends along field oxide 113 gate level runner 203 may be connected although not shown in the particular cross section of fig1 to gate 201 or 205 or to the gate source or drain of some other transistor not shown in fig1 layer 119 which may be silicon dioxide is formed on substrate 111 next layer 121 is deposited layer 121 may be silicon nitride or silicon oxynitride layer 123 is deposited upon layer 121 layer 123 may be formed from teos or bpteos or any of a variety of other deposited dielectrics typical thicknesses for layers 119 121 and 123 are similar to the thicknesses for aforementioned layers 19 21 and 23 in fig1 7 next in a manner analogous to that depicted in fig4 10 layers 123 121 and optionally 119 are anisotropically etched to create spacer layers 119 121 and 123 illustrated in fig1 some drain regions 300 301 and 302 may be formed in a manner similar to that discussed before although fig1 shows the shapes of junctions 300 301 and 302 to have standard profiles lightly doped drain ldd profiles may be created.