is at or above the upper level threshold almost full marker 415 is active alternatively when the data level is above the lower level threshold and below the upper level threshold the almost empty and the almost full markers are both inactive network reference clock 403 is processed by frequency translator 411 to generate an srts reference clock 421 in the exemplary embodiment network reference clock 403 is the t1 clock rate of 1 544 mhz frequency translator 411 generates a 2 43 mhz srts reference clock 421 based the 1 544 mhz network reference clock 403 in other preferred embodiments the network reference clock and or the srts reference clock may have other frequencies in the preferred embodiment of the present invention frequency translator 411 is implemented with a phase lock loop pll the function and operation of which is considered to be well known to those skilled in the relevant art however as would be apparent to one skilled in the art frequency translator 411 may utilize other translation methods to create a suitable srts reference clock 421 from network reference clock 403 it should be noted however that a pll is preferred due to its ability to control jitter and phase transients in the reference clock distribution system srts clock recovery subsystem 404 maintains a constant phase offset between the receive clock of the source node and the transmit clock of the destination node the srts clock recovery subsystem includes an rts sample generator 420 for generating a destination rts sample 429 it also comprises a subtractor 422 for determining the difference between this destination rts sample and the source rts portion of the information stream generating a current phase offset 425 between the source and.