the duty cycle of the waveform via the input 620 fig7 illustrates an exemplary overshoot waveform generated by the waveform generation circuit 600 the generation process starts at approximately 0 5 nanoseconds with the current regulator 602 increasing the voltage at the v dut node to a value of v ddstress by 0 6 nanoseconds the voltage remains at a value of v ddstress throughout the delay caused by the programmable delay circuit 612 after the delay the voltage is discharged by the discharge device 608 to a nominal v dd value the current regulator 602 may pull down the voltage to roughly zero volts at approximately 0 8 nanoseconds the waveform generation starts at the rising edge of the clock 606 which occurs appropriately at 0 5 nanoseconds and completes after the falling edge of the clock 606 which occurs appropriately at 0 8 nanoseconds the generation repeats ever clock cycle as desired fig8 illustrates an exemplary circuit level implementation of the waveform generation circuit 600 the circuit is constructed using the components discussed in the foregoing discussion more specifically a current regulator 802 is coupled to a voltage comparator 804 the comparator 804 generates a rising edge once node v is greater than v ref a set reset s r flip flop 806 triggers the discharging transistor attached to node v after an insertion delay introduced by a programmable delay circuit 808 thus the actual value of the overshoot voltage may be set by.