for a memory cell array with a plurality of block regions in the process 3 shown in fig4 a photo resist 211 is formed in a stripe shape in a y direction and the insulation oxide film layer 27 is removed by etching in the process 4 shown in fig5 using the photo resist 211 which was formed in the process 3 p type impurities b or bf 2 are obliquely implanted and p type diffusion regions 12 are formed the p type diffusion regions 12 will later become bit lines in the process 5 shown in fig5 using the photo resist 211 which is not removed additional etching is performed and the n type well 11 is etched and removed in a groove shape half way into the silicon substrate the grooves are patterned in a y direction forming a three dimensional channel the p type diffusion layer 12 which has already been formed is patterned so that it is exposed on the upper part of both side wall surfaces of the grooves in the n type well 11 in the process 6 shown in fig5 the photo resist 211 is removed and n type impurities p or as are obliquely implanted in the same direction as the process 4 at a.