line this implementation provides for a decrease in the number of components and therefore a decrease in size the implementations of fig1 and 2 allow continuous read and write of the digital memory however if continuous operation is not required the circuit of fig3 can be used it is comprised of an input output delay line 11 first switching means 12a and 12b samplers 13 second switching means 14 analog to digital converters 15 digital to analog converters 16 memories 17 control logic 18 and processor 19 with the first and second switching means placed in position 1 an input signal is allowed to be distributed along the delay line 11 control logic 18 generates a command to the samplers 13 to sample the input waveform and to the a d converters 15 to convert the sample to a digital word memory addresses are generated in memories 17 by the control logic 18 and the digital words corresponding to the samples are stored in memories 17 to reconstruct the output waveform the first and second switching means are switched to position 2 which therefore allows a stored digital word converted back to an analog level by d a converters 16 to be transferred to samplers 13 and distributed to the input output delay 11 it will be understood by those knowledgeable in this art that the switching means 14 can consist of a simple diode network or a circulator to allow flow of information in only one direction shown in fig4 is a particular implementation of interest used in the present invention reference numeral 20 shows a 0 to 500 mhz 330 microsecond broadband digital rf memory in this.