is not set to a 1 condition meanwhile bit b bit c 34 count 34 and c k are applied to and gate 66 since bit c is effectively a 1 and bit b is a 1 gate 66 will provide an output to or gate 65 gate 65 also receives bit a also effectively a 1 and so sets the k input of bistable 63 to a 1 condition the output v f is therefore a logic 0 indicating no violation this is to be expected since the first data 0 of the pair held in 60 a is followed by only a single data 1 held in 60 b bistable 73 has both inputs set to the 0 condition by virtue of a 0 logic level appearing at one input to each of the and gates 67 68 and 69 hence also to one of the inputs to and gate 70 therefore bistable 73 will not toggle to a 1 output when clocked it being assumed that it is already in a 0 condition during the next digit period the contents of the shift register are respectively 1 0 and 1 the output of bistable 62 remains at 1 because bit a is now effectively 0 and there is still no violation output v f the 34 count 34 of 1 now represents the first data 1 following the first 0 of the pair of 0 39 s similarly the bit a and bit b inputs to gate 64 are 0 while the bit c input is.