on output line 32 with a frequency depending on the voltage on control input line 31 the signal on output line 32 can be used directly or indirectly as system clock of the audio system the signal on line 32 is also fed to divider 34 which will generate an output signal on line 35 which is of the same frequency and phase as the occurrence of the code violation in the preamble of the digital audio signal a deviation between both frequencies and phase will result in an error signal in form of a series of pulses at the output of detector 36 the error signal is filtered by the pll loop filter consisting of capacitance 37 and resistor 38 and fed to voltage controlled oscillator 30 to correct the frequency and phase of the oscillator and thus locks the pll fig5 is a schematic illustration of a combination of the circuit of the present invention 102 and a commercially available integrated decoder circuit 100 of the type saa7274 receiver circuit 100 receives digital audio signals at input 101 the same signal is fed to clock recovery circuit 102 the output of clock recovery circuit 102 is fed to input 103 of receiver circuit 100 receiver circuit 100 provides the signals data 110 bit clock 111 l r clock 112 x system clock 113 and all sub code signals 114 at.