in series between the power supply signal v dd and ground the fets n2 n3 are arranged in series to form a voltage divider means the source of fet p3 is connected to the power supply signal v dd the source of fet n3 is connected to ground the fet n2 which has its gate connected to v dd has its source connected to the drain of fet n3 and also has its drain connected to the drain of fet p3 the third parallel circuit comprises field effect transistor p4 and n4 which are connected in series between the power supply signal v dd and ground the source of fet p4 is connected to the power supply signal v dd while the source of fet n4 is connected to ground the gates of fets p4 and n4 are connected to each other and to the common junction between fets n2 and n3 the common junction between fets p4 and n4 is connected to the input of inverter inv 1 a capacitor c1 is connected between the power supply signal v dd and the input to inverter inv 1 the output of inverter inv 1 is respectively connected to the gate of fet p1 and the input to inverter inv 2 the output of inverter inv 2 provides the output signal por and is also connected to the gate of fet n3 the gates of fets n1 and n2 are respectively connected to the power supply signal v dd the gate of fet p3 is connected to the common junction between fets.