signal to raise the voltage of a respective row line associated with the identified row decoder driver circuit the signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder driver circuits the signal generating circuit output maintains the gate voltage of each of the input transistors near the edge of conduction when receiving the signal that the voltage of the respective row line is to be raised otherwise the signal generating circuit maintains the gate voltage at ground potential application_number US 36304694 A description fig1 shows a block diagram of a unit of eight row driver decoders rd1 through rd8 each row driver decoder rd1 through rd8 receives an rcom signal as discussed in greater detail below and three address bits address 1 address2 and address3 selected from bits a3 a2 and a1 and their complements some precoding of a row address is accomplished prior to the three address bits being provided to the circuit of fig1 three address bits provide for one of eight row selection the eight row driver decoder circuits of fig1 are replicated in each of 64 units for a memory of 512 rows a common rcom signal is provided to all 64 units of eight row drivers other configurations are possible a schematic diagram of an illustrative embodiment row driver decoder rd1 is shown in fig2 in which transistors m1 and m4 are p channel transistors and.