necessary which is connected to receive transfer signal tr1 from the appropriate signal source in addition write erase loops 12 and 13 may be connected to suitable generators g1 and g2 respectively generators g1 and g2 may be any suitable generator such as but not limited to loop generators which are known in the art in this arrangement loops 12 and 13 can be used to write information into storage loops 1 l through m l and 1 r through m r via transfer switches 19 and 20 respectively as will be discussed hereinafter this arrangement provides an alternative input system for the memory device transfer replicate switches 17 and 18 are coupled to access loops 10 and 11 respectively access transfer loop 11 includes a suitable generator g1 39 of any suitable configuration such as a loop generator a similar generator g2 39 is associated with access loop 10 while the conductor loops of generators g1 39 and g2 39 are shown connected separately they can be connected in series with each other and arranged to receive a common signal from an appropriate source wherein bubbles can be generated in a known fashion the ends of access loops 10 and 11 are connected to detectors d1 and d2 respectively detectors d1 and d2 shown schematically can be any suitable type of stretcher detector many of which are known in the art detectors d1 and d2 are preferably but not necessarily connected together in a common bridge network not shown wherein the full data output of the memory device is retrieved in the particular system described herein it is important that the arrangements between the respective generators.