program and program verify is described the threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines bit line to control gate line capacitance is also used to reduce the number of voltage references needed program current is reduced by use of a load device coupled to the source diffusion the result is increased program bandwidth with lower high voltage charge pump current consumption application_number US 37151803 A description based on the memory cell structure in fig4 a program and verify conditions for the twin monos memory cell of patent application ser no 09 426 692 filed oct 25 1999 are given in fig5 a through fig5 d the memory cell 410 is comprised of one word gate 402 a left diffusion region 401 a right diffusion region 403 and two control gates 406 and 407 and two nitride storage sites 404 and 405 the left nitride storage site 404 is positioned under the left control gate 406 above the left diffusion 401 and close to the word gate 402 the right nitride storage site 405 is positioned under the right control gate 407 above the right diffusion 403 and close to the word gate 402 it should be noted that the program condition shown are significantly lower than the program voltages for a conventional monos device the voltage difference is due to.