described hereinafter in the form of a multiplexer although as noted above it can be embodied in the form of other known circuits the digital logic circuit 3 has an output coupled via an i o line y to one of the scan lines e g p 1 15 of the scan matrix 2 the digital logic circuit 3 has three inputs coupled via three separate i o lines s 0 s 1 s 2 from three corresponding scan lines e g p 1 12 p 1 13 p 1 14 of the scan matrix 2 the output y is provided to the processor 1 to inform the processor 1 whether one of the keys sw 1 sw 8 has been pressed and the inputs s 0 s 1 s 2 are provided from the processor 1 to allow the processor 1 to decode the identity of the key sw 1 sw 8 that has been pressed fig3 illustrates the logic control for the keys sw 1 sw 8 and the logic control circuit 3 if none of the keys sw 1 sw 8 are pressed then y will always be 0 on the other hand if any one of the keys sw 1 sw.