the q output of flip flop 300 going high on the 31st count at this point counter 400 is caused to reach its terminal count so that its c out output goes high causing the d input of flip flop 500 to go high therefore on the 32nd count when flip flop 500 is clocked the q output of flip flop 500 goes low enabling the presetting of counters 200 and 400 and the q output of counter 500 goes high which will repeat every 32 counts as is understood by one skilled in the art the counting apparatus of fig2 can be alternatively described as a series of units composed of a counter and a flip flop or as a series of counters each pair of counters being separated by a flip flop and the last counter being followed by a flip flop taking either approach it is clear that the string of counters and flip flops can be extended as far as necessary to achieve the desired divisor ratio and that the present invention is not limited to two counters and two flip flops in order to evaluate the advantage of the synchronous carry frequency divider over frequency dividers employing a terminal count decode network but not a pulse gobbler propagation delays may be calculated using typical propagation delays for the 74 f series logic including the 74f 161 counter the 74f 100 nand gate and the 74f 109 flip flop available from fairchild semiconductor division of fairchild camera and.