through n channel sink transistors 32 34 which are connected between vout vout u2212 and ground the gates of n channel sink transistors 32 34 are driven with an adjustable bias voltage during auto zeroing phase u03c6 1 switches 52 54 close and switches 56 58 are open a bias voltage vb is generated by current source 16 providing a current through resistor 14 and n channel bias transistor 18 which has its gate and drain connected together as bias voltage vb the bias voltage applied to the gates of n channel sink transistors 32 34 causes them to operate in the linear region to provide a high gain but low current and thus a lower speed of operation with feedback switches 10 12 closed the dual input differential amplifier operates as a unity gain op amp during auto zeroing phase u03c6 1 during amplifying phase u03c6 2 switches 52 54 are open but switches 56 58 close the gates and drains of p channel primary differential transistors 22 24 are shorted together by switches 56 58 causing n channel sink transistors 32 34 to operate as a resistor with a resistance of 1 gm the high current provides a faster speed of operation although the gain is low thus the dual input differential amplifier operates as a high speed low gain amplifier during amplifying phase u03c6 2 fig7 is a schematic of a final latch an adc may have several stages such as 8 stages of fig6 cascaded together with a final latch stage that drives the compare output back to sar 302 of fig1 rather than sample and hold the input analog voltage as shown in fig1 the result of comparing the input analog voltage to the dac voltage va is stored in.