nmos transistor 50 is applied the elimination of one masking step can result in appreciable saving in the fabrication cost furthermore nmos transistor 50 realizes advantageous electrical characteristics first nmos transistor 50 has a higher breakdown voltage bvdss due to reduced electric field and deeper drain junction second nmos transistor 50 is a symmetrical high voltage device where both the source as well as the drain can achieve high voltages the symmetrical structure is not achievable in other high voltage devices such as nch ldmos devices third nmos transistor 50 has improved analog characteristics such as higher output impedance due to less impact ionization and reduced electric field due to the lightly doped n well compared to nldd regions lastly the nmos transistor 50 can be applied in flash products to achieve the higher voltages needed for flash devices according to another aspect of the present invention nmos transistor 50 can be formed without p well 62 a in the channel region of the transistor in that case the substrate without or without additional threshold adjustment implants serves as the channel of the transistor when the channel of the nmos transistor is formed in the p substrate 64 either a substrate device with threshold adjust enhancement implantation or a native device without any threshold adjust.