integrator 24 notably stage 22 does not require like summing junction 60 since only the 1 bit quantized output signal is utilized recalling that the frequency of oversampling clock signal f s is much much greater than the maximum frequency component of the input signal if the averaged value of the analog input signal minus the feedback signal via dac 58 is greater than the reference potential then the output signal of comparator 54 is logic one otherwise if the averaged value of the analog input signal minus the feedback signal via dac 58 is less than the reference potential the output signal of comparator 54 is logic zero the operation of triple stage u03c3 u03b4 modulator 12 is thoroughly described in u s pat no 4 704 600 34 oversampling converter 34 issued to uchimura et al and is hereby incorporated by reference briefly stages 14 18 and 22 are first order modulators and as such are unconditionally stable the output signal of the stage 14 v 14 can be shown to be e 14 is the error signal provided at the second output of stage 14 furthermore the output signals of respective stages 18 and 22 v 18 and v 22 can be shown to be e 18 is the error signal provided at the second output of stage 18 e 22 is the error signal provided at the second.