outputs to buffer 112 on lines 164 166 and 168 and also to multiplexers 128 132 and 136 on lines 228 230 and 232 respectively multiplexers 138 to 152 are also provided with one of their inputs coming from one of the eight read data outputs r d1 to r d8 respectively and the other of their inputs coming from buffer 112 as in the embodiments described in fig4 eight read data ports are provided on the register file 112 and multiplexers 138 to 152 operate in the same way as multiplexers 59 to 73 described in fig4 that is to say these multiplexers are for the purpose of verifying data read from register file 110 is up to date data and if it is not up to date data then the value from buffer 112 is returned to the execution unit that made the read request the embodiment of fig5 a also includes write enable signals and circuitry which have not been shown for clarity reasons but which are shown in fig5 b and will now be described fig5 b shows the write enable signals and circuitry between the execution units 114 to 120 register file 110 and buffer 112 of fig5 a each of the execution units 114 to 120 includes first and second write enable signals on lines 248 to 262 first write enable lines 248 252 256 and 260 from execution units 114 to 120 are connected to buffer 112 second write enable signals on lines 250 254 258 and 262 from each execution unit are provided to one.