performance improvement including increased charge carrier mobility referring to fig1 a 1f in an exemplary embodiment of the method of the present invention are shown cross sectional schematic views of a portion of a semiconductor wafer during stages in production of a cmos structure strained channel transistor according to an embodiment of the invention for example referring to fig1 a is shown an exemplary cmos semiconductor device shown is a semiconductor substrate 12 including an active channel region 12 a source drain extension regions e g 14 a and source drain regions e g 14 b gate dielectric 16 a gate electrode 16 b gate liner e g 18 a and offset spacer 18 b the semiconductor substrate 12 may be formed of silicon silicon on insulator soi strained silicon and silicon germanium sige or combinations thereof still referring to fig1 a gate structures including a gate dielectric portion e g 16 a and gate 16 b may be formed by conventional cvd deposition lithographic patterning and plasma and or wet etching methods known in the art preferably the gate dielectric portion e g 16 a may be formed by any process known in the art e g thermal oxidation nitridation sputter deposition or chemical vapor deposition the physical thickness of the gate dielectric may vary depending on the scaling design constraints but is preferably in the range of 5 to 100 angstroms the gate dielectric may be formed of silicon oxide silicon nitride silicon oxynitride a high k dielectric or combination thereof when using a high permittivity high k dielectric preferably the dielectric constant is greater than.