least one of the two sets of gate electrodes straight along their width and receptive of a phase of clocking signal so as to erect barrier potentials during image intetgration times in the portions of the charge transfer channels thereunder where only one set of straight electrodes is so biased during each image integration time the sets may be alternately so biased thus to provide interlace when dynamic clocking is resumed there may be spill over of excess collected photocharge both sets of straight electrodes are biased to erect barrier potentials during image integration which desirably reduces dark current collection then prior to resumption of dynamic clocking one clock phase is dropped to eliminate the induction of barrier potential in the portions of the charge transfer channels thereunder there will be no excess of collected photocharge to spill over the dropped phase may be alternated from field to field to provide interlaced image sampling when parallelled charge transfer channels with five phase clocking during charge transfer as described above are used in an image register and where field to field interlace of image samples is not used it is advantageous during image integration to bias only the interlaced pairs of meandering gate electrodes e g those receptive of u03c6 c and u03c6 e clock phases in fig3 so as to erect barrier potentials in the portions of.