v 10 v 2 7 v avx vdd 10 v 2 7 v pp 0 v 0 v 0 v ndis u2212 4 v 0 v 0 v np vdd vdd vdd wldrvss u2212 4 v 0 v 0 v wl u2212 4 v 10 v 2 7 v in the erase mode nmos transistor 220 is off because the gate bias ndis u2212 4v fig3 shows a cross sectional view of a portion of the circuitry of fig2 one of the source drain terminals 205 of the nmos transistor 220 is coupled to ground reference 250 which acts as a reference supply voltage during memory operations the other of the source drain terminals 207 of the nmos transistor 220 is coupled to the word line 209 nmos transistor 220 is formed in the p well 211 which in turn is formed in the n well 213 which in turn is formed in the p type substrate acting as a ground 250 during the manufacturing process negative plasma induced charge is passed from the word line 209 through nmos transistor 220 and to the semiconductor substrate acting as a ground 250 negative plasma induced charge on the word line 209 causes the voltage of the word line 209 to be lower than the voltage of.