domain lt 3 gt and a signal domainb lt 3 gt generated from the first signal generating means 31 a second flip flop 387 for being triggered in an ascending edge of a clock signal tclk being inputted to a clock terminal and delaying the output of the second transfer gate 386 by u201c 1t cycle u201d the third delay means comprises a third transfer gate 388 for transferring the output signal of the second flip flop 387 of the second delay means according to a third domain signal domain lt 4 gt and a signal domainb lt 4 gt generated from the first signal generating means 31 a third flip flop 389 for being triggered in an ascending edge of a clock signal tclk being inputted to a clock terminal and delaying the output of the third transfer gate 388 by u201c 1t cycle u201d the fourth delay means comprises a fourth transfer gate 390 for transferring the output signal of the third flip flop 389 of the third delay means according to a fourth domain signal domain lt 5 gt and a signal domainb lt 5 gt generated from the first signal generating means 31 a fourth flip flop 391 for being triggered in an ascending edge of a clock signal tclk being inputted to a clock terminal and delaying the output of the fourth transfer gate 390 by u201c 1t cycle u201d and outputting it via a data pad dq the transfer means 392 comprises a first.