zero layer wafer substrate 11 is provided which for example can be a silicon wafer so that the process is compatible with a standard cmos process next transistor devices can be formed by standard cmos process steps as required not shown followed by deposition lithography and etch steps to form interconnection including a contact layer 12 a metal layers 13 and via layers 12 b a dielectric layer 14 is provided to isolate the metal patterns of the layers where there should not be connection furthermore a bond pad pattern 15 is formed on the topmost metal layer and a passivation layer 16 is formed on top of the overall structure in one embodiment the contact layer 12 a and the via layers 12 b can be made of tungsten the metal layers 13 can be made of aluminum and the dielectric layer 14 can be made of oxides such as silicon dioxide other conductive or dielectric materials can be used to replace what are suggested above and the structure can include more or less number of metal layers in the shown structure between the innermost first metal layer 13 and the outermost metal structure item 30 of fig1 c referred to also as the u201c upper structure u201d hereinafter an etchable structure 20 is formed which includes a portion of the contact layer 12 a metal layers 13 and a via layer 12 b the purpose of the etchable structure 20 is to define a suspended structure of the mems device which will become clearer as referring to the following process steps the outermost metal structure can either provide a guard ring function to protect the circuitry not shown from etch damage or moisture or act as an upper electrode to be explained later.