detects that the sam data applied thereto from the register 24 is not zero viz 0000 0000 0000 0011 and changes the logic state of the control signal c6 viz from 34 0 34 to 34 1 34 in response to the control signal c6 logic 1 the selector 20 is controlled such as to choose the output of the sam data renewal circuit 26 while the selector 22 is controlled to select the output of the address register 38 instead of the base address the register file address generator 28 generates a 4 bit register file address 34 1110 34 by detecting a logic 1 at the 14th bit position in the sam data applied thereto from the sam data register 24 the register file 30 in response to the address 34 1110 34 initiates transfer of data stored in the 14th register 30 14 to the memory access controller 14 over a line l2 when the controller 14 acknowledges receipt of the data from the register file 30 the controller 14 issues a control signal c8 which is applied to the controller 32 on the other hand the sam data renewal circuit 26 changes a logic 1 at the 14th bit position in the sam data viz 0000 0000 0000 0011 further during the same time duration the main memory address generator 36 issues a main memory address using the base address and the index number both applied thereto and then applies the main memory address thus obtained to the address register 38 the memory access controller 14.