etc two cell strings are assigned sources of memory cells in two adjacent strings are commonly connected to corresponding even numbered sub bit lines sbl2k and drains thereof are connected to two odd numbered sub bit lines sbl2k 1 and sbl2k 1 at both sides of each strings respectively for example the sources of the cells m13 and m14 are commonly connected to the sub bit line sbl4 and the drains thereof are connected to the sub bit lines sbl3 and sbl5 respectively odd numbered sub bit lines sbl1 sbl3 etc are electrically connected to the main bit lines mbl1 mbl2 etc via a first string selection circuit which is constituted with string selecting nmosfets st1 st2 etc respectively similarly even numbered sub bit lines sbl2 sbl4 etc are electrically connected to the ground lines gl1 gl2 etc via a second string selection circuit which is constituted with ground selecting mosfets gt1 gt2 etc respectively the main bit lines mbl1 u02dc mblj are electrically connected to the sense amplifiers sa1 u02dc saj via the first column selection circuit 46 which is constituted with a group of first column selection mosfets bt1 bt2 etc respectively fig4 shows an example of each sense amplifier circuit san shown in fig3 where n is 1 2 j in this figure the sense amplifier circuit san has a data line dl a dummy data line or a reference line ddl first and second precharge circuits 52 and 54 and a current mirror type differential amplifier 56 the data line dl is electrically connected to a corresponding main bit line mbln.