A description detail descriptions of the chip testing circuit of the invention will be given herein with reference to the drawings in which one element is represented by the same symbol fig2 a and 2b show schematic diagrams illustrating the chip testing circuit according to one embodiment of the invention the chip testing circuit 300 according to one embodiment of the invention comprises the write circuit portion as shown in fig2 a for inputting the test signal ts to the dram cell array or internal circuit 3001 of the chip and the read circuit portion as shown in fig2 b for acquiring the cell signal fs from the dram cell array 3001 of the chip as shown in fig2 a the write circuit of the chip testing circuit 300 according to one embodiment of the invention comprises a plurality of write units 32 a first interface circuit 31 and a first switch 33 each write unit 32 is coupled to at least one dram cell array of the chip for example the chip can be a memory component a memory containing semiconductor device or a logic component in a form of a wafer a bare die or a packaged chip the write units 32 according to one embodiment of the invention can be part of the dram cell array 3001 of the chip for example in the memory component the write units 32 may operate with the word driver for writing the test data into the specific address of the memory unit the write units 32 can be divided into a first write group 32 a and a second write group 32 b the first interface circuit 31 is coupled.