node b is substantially 13 volts and the voltage at node a is in the range between 17 and 13 volts the actual voltage at node a depends on the rate of leakage of charge within the memory cell and the size of capacitor 20 in a total absence of leakage the voltage at node a would remain at 17 volts however in the presence of leakage the voltage at node a becomes less negative as the quantity of leakage increases the charge which flows from node a to node b to restore the voltage at node b to 13 volts replaces any charge which leaked from node b and has the effect of refreshing a logical one stored in the memory cell since the logical one is refreshed in each clock cycle the memory system is capable of storing a logical one indefinitely without the necessity of rewriting the logical one such refreshing action can only take place if the voltage at node b is sufficiently negative for read and boost transistor 22 to be rendered conductive during at least part of the time period t 10 t 4 if the voltage on node b is not sufficient to render read and boost transistor 22 conductive during at least part of the time period t 10 t 4 then no boost or refresh effect takes place and the memory will treat the information stored in the memory cell as a logical zero further the charge on nodes a and b will eventually leak off to leave substantially ground voltage at those nodes the exact voltage level which is the.