4481572 A abstract a time shared bus for use with digital computers the computers are structured around a high speed bidirectional time shared bus whereby both address and data are carried on the same lines in a typical configuration one or more processors one or more memories and one or more peripheral devices are coupled in parallel on the time shared bus and in addition are each connected by respective control lines to a resource controller the bus is multiplexed at a relatively high rate whereby a continuous series of relatively short time slots or windows on the bus are provided these time slots are selected to be as short as reasonably possible as required to allow the settling of the bus to each new state as set by the then transmitting unit on the bus and to latch the transmitted information into the receiving unit for that time slot each unit on the bus has associated therewith a response time represented by a predetermined number of time slots between its receipt of a request for information and its providing of information onto the bus which number of time slots delays is resident in both the respective unit controller and in a resource controller direct memory access cache memories and other features are disclosed application_number US 31045881 A description one of the underlying concepts of the present invention.