of expression such a device is termed herein as a u201c multi pipe system on chip u201d or u201c mp soc u201d this system u201c on a silicon chip u201d comprises a cluster of gpu driven pipeline cores organized in flexible topology allowing different parallelization schemes theoretically the number of pipeline cores is unlimited restricted only by silicon area considerations the mp soc is driven by software driver modes which re resident to the host cpu the variety of parallelization schemes enables performance optimization these schemes are time image and object division and derivatives of thereof the illustrative embodiment of the present invention enjoys the advantages of a multi gpu chip namely bypassing the converge limitation of a single gpu while at the same time it gets rid of the inherent problems of a multi gpu system such as restricted bandwidth of inter gpu communication mechanical complexity size power and heat redundancy of components and high cost as shown in fig4 a the physical graphic system of the present embodiment comprises of a conventional motherboard 418 and mp soc based graphic card 415 the motherboard carries the usual set of components which are cpu 411 system memory 412 memory bridge of i o chipset 413 and other non graphic components as well see fig 1a for the complete set of components residing on a pc motherboard the printed circuit graphic card based on the mp soc chip 416 connects to the motherboard via a pci express 16x lanes connector 414 the.