pixel region u201c c u201d is designed to have a relatively high value for the second pixel region u201c b u201d however the parasitic capacitance u201c cgs u201d is designed to have the highest value even though the kickback voltage u201c u03b4vp u201d of the second pixel region u201c b u201d has the intermediate value between those of the first and third pixel regions u201c a u201d and u201c c u201d because the voltage drop of the common voltage signal is the highest in the second pixel region u201c b u201d more compensation is needed for the parasitic capacitance u201c cgs u201d of the second pixel region u201c b u201d that is to say in case of the second pixel region u201c b u201d the voltage drop of the common voltage signal as well as the gate voltage signal affects the kickback voltage u201c u03b4vp u201d therefore the parasitic capacitance u201c cgs u201d must have the highest value for the second pixel region u201c b u201d to achieve the optimum parasitic capacitance u201c cgs u201d first to third overlapping widths u201c l a u201d u201c l b u201d and u201c l c u201d of the drain electrode 164 a 164 b and 164 c are respectively adjusted in accordance with the first to third pixel regions u201c a u201d to u201c c u201d in case of considering the voltage drop of the gate voltage signal u201c vg u201d only the third overlapping width u201c l c u201d is designed to be the largest the second overlapping width u201c l b u201d is designed to be larger than the first overlapping width u201c l a u201d further in case of considering the voltage drop of the.