each of the masks having a portion adjacent to a tip of a respective one of the floating gates of a given thickness wherein the given thicknesses of the mask portions are different from one another and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness application_number US 61467706 A description fig3 10 are partial sectional views illustrating an embodiment of an improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages the method may use a chemical mechanical polish cmp floating gate formation process commonly used in 0 13 technology for partially forming the floating gate structures of the flash memory cells as shown in fig1 the floating gate structures 410 formed by the method have lower ftvs and narrower cell to cell ftv ranges than prior art floating gate structures 400 the lower ftvs improve the erase performances of the floating gate structures and the narrower ftv range provides a more uniform erase performance from cell to cell the flash memory cells described herein may be used in embedded memory applications including without limitation smart cards and communication ic.