latch 73 is written to mainstore at the address in the msar 72 after the data has been written in mainstore control 80 writes the accessed buffer tag field 50 1 to the empty state if comparator 64 indicates no match or after control 80 has written the buffer tag field 50 1 to the empty state then the address in the evar 25 is incremented by selecting the lab 28 through the incrementor 26 each buffer entry is examined in turn and if it matches as described above it is released from the buffer after all buffer entries have been processed no buffer entries belonging to the accessed tlb entry remain in the buffer control 80 then allows the translator 30 to replace the old translation in the tlb with the new translation by writing each of the tlb fields as described above by adhering to the above algorithm the control block 80 guarantees that there will never be data in the buffer belonging to a displaced tlb entry unless both the new and the old tlb entry translate to the same system page address for completeness we describe both the move in and the move out processes whereby data is moved from mainstore to the buffer and from the buffer to mainstore once a cpu data request has a matching tlb entry as described above comparator 64 determines whether there is a resident.