the input electrode of the next semiconductor 12 through the gate to gate transmission line 17 18 which provides the correct time delay to cause cancellation of reflections from the device input electrodes and finally into the input termination network 19 providing for a low reflection at the amplifier input terminal the output electrodes of the semiconductor devices are likewise connected through the drain to drain transmission line 16 20 with a time delay designed to provide both reflection and cancellation from the fet output electrodes and signal summation of the amplified fet outputs the gate to gate transmission line 17 18 is designed to be physically in close proximity to the drain to drain transmission line 16 20 to allow some of the amplified signal present on the drain to drain line to couple back to the gate to gate line the amplitude of feedback signal is determined by the physical separation of the drain transmission lines from the gate transmission lines the phase of the feedback signal is determined by the length of the line pair for the purpose of computing the precise effect of the coupling by computer modeling the coupled transmission lines can be described by the so called even mode and odd mode impedances z 0 e z 0 o and the phase length at a specified frequency as shown in fig5 the graph in fig6 shows a computer simulation of a computer optimized drf amplifier made with commercially available fet devices this circuit has been computer optimized for flat gain from dc to 40 ghz referring to the circuit of fig5 the amplitude and phase of the feedback signal can.