ground terminal 412 is less than one half of power supply voltage vdd this increased voltage advantageously decreases standby power of the memory circuit as previously discussed upon a transition to active mode such as a read or write operation address signals ra x0 n and ra y0 for example are applied to the row decode circuits of block 400 the common virtual ground terminal of memory block 400 is quickly discharged to reference voltage vss virtual ground terminals of other unselected memory blocks 402 404 remain at their saturation voltages a product of the discharge current of block 400 and metal resistance induces a brief voltage spike on the power supply reference voltage lines 422 such a voltage spike is often referred to as array noise and may capacitively couple to signal lines such as adjacent bitlines and create a data error the present invention however advantageously minimizes the magnitude of this voltage spike by activating only one of the memory blocks corresponding to a respective predecoded address signal moreover due to the relatively small magnitude of the voltage spike no significant time delay is required before a read operation of a selected memory cell may be performed referring now to fig5 there is a single memory block 500 showing another embodiment of the present invention as with the example of fig4 memory block 500 is preferably one of m memory blocks in a memory array memory block 500 includes n rows of segmented wordlines each segmented wordline includes a global wordline for example global wordline 504 and wordline segments 508 and 512 memory block 500 is selected from.