out under the following conditions assuming that the first 100 bits of the new frame data are written in line buffer a and the next 100 bits from 101th through 200th bit of the new frame data are written in the write line buffer at addresses 1 through 100 the moment the 201th bit is written at address 101 of the write line buffer a write request wrq is generated as mentioned above since data transfer to the memory array has been already complete before the 301th bit is written the output of a readout request rrq for data transfer of 101th bit through 200th bit from the memory array to the read line buffer may be admitted resulting in input of a rrst signal as mentioned above namely new data can be retrieved to be read out if a signal rrst is output after more than 300 swck clock cycles following the generation of a wrst signal after 300 bits of data have been written it must not to be allowed for rrst signal to output within the range of 100 to 300 swck clock cycles after generation of the last wrst signal because determination whether the old or new data shall be readout is impossible in this time range since data write and readout can be performed asynchronously the clock pulse widths of swck and srck can be changed freely also in this case assuming that swck and srck at occurrence of wrst and rrst are of 0 cycle respectively no confusion can occur mixing of old and.