the integer code representing the next msd and the remaining fraction code being carried on l2 39 and l8 39 to stage iii to determine the next bcd digit successive integer codes are extracted by in the preferred embodiment ten successive stages thereby yielding a ten place bcd decimal representation of a 24 bit binary fraction at bit 22 time type d flip flops 144 144 39 and the type d flip flops associated with the succeeding stages are pulsed by a transfer pulse which occurs when q x of flip flop 136 is 1 q x it should also be noted feeds nor gate 150 along with the complement produced by nor gate 152 of the checked word w i e w the inputs to nor gate 152 permit a checked word w to enter multiplier stages 18 only when q x of flip flop 136 is 0 thus during the word time when q x is 0 a checked word w enters multiplier stages 18 to be converted while during the next word time q x 1 no check word is sent through to multiplier stages 18 instead the transfer pulse is passed through nor gate 154 to transfer the bcd decimal outputs in flip flops 114 114 39 et seq to the ten nixie tubes 156 of the display reference in now made to fig2 which illustrates in timing diagram form the operation of the hardware of the present invention the sign bit sb line indicates the sign bit time which occurs at the twenty fifth bit time of each word sb in.