that the output of the gate 66 does not change when the delay pulse produced by the delay circuit 68 ends by chaining together a plurality of delay circuits 68 and 70 and producing a plurality of delayed control pulses a control pulse of extended duration can be obtained at the output of the second gate 66 additional delay circuits 68 70 can be added to increase the length of the control pulse of extended duration the control pulse of extended duration is the boost signal which is input to the control portion of the booster circuit 74 the delay circuits 68 and 70 together with the nor gate 66 may be viewed as a pulse extender to insure glitch free operation the pulse extender of the present invention should have outputs taken from enough points along the delay line to insure no glitch in the extended pulse returning to fig3 the voltage regulator 40 may have a differential amplifier 78 which produces a first output signal out 1 for directly driving transistor 46 and a second output signal out 2 which indirectly drives transistor 48 a bias voltage is supplied to the differential amplifier 78 through an n channel transistor 82 transistor 82 is responsive to a control signal vgregbias a transistor 84 is connected in series with a transistor 85 with the two transistors 84 and 85 connected in parallel with the transistor 82 the boost signal may be additionally used to control the transistor 84 because the boost signal is active low an active high version is taken from the output of inverter 56 such that when the boost signal is active the transistor 84 is turned on when going into nap.