generated from the controlling portion 502 in response to the first clock clk 1 when the shift clock sclk is generated 100 times in response to the second clock clk 2 the latch clock lclk is generated once in response to the first clock clk 1 the decoding portion 510 and the buffering portion 512 operate in a manner corresponding to the decoding portion 310 and the buffering portion 312 shown in fig3 respectively the decoding portion 510 inputs data that is simultaneously output from the data register 508 and selects voltages corresponding to the respective data among the voltages v 1 through v 64 of 64 levels corresponding to all the bit combinations of the six bit data the buffering portion 512 temporarily stores the voltages selected from the decoding portion 510 and outputs them as panel displaying voltages through the 300 channels the above described operation of the data register 508 corresponds to normal operation of the apparatus for providing panel displaying voltages in response to the latch clock lclk generated from the controlling portion 502 in response to the first clock clk 1 operation of the data register 508 when the decoding portion 510 is tested for a circuit verification in the apparatus for providing panel displaying voltages will now be described as mentioned above the controlling portion 502 generates the latch clock lclk in response to the first clock clk 1 during a normal operation however when the test control signal test is applied to the decoding portion test controller 504 of the controlling portion 502 the controlling portion 502 generates the latch clock lclk maintaining a high level and.