oxide 17 the selective epitaxial film 20 of p type has a dopant density higher than that of the p type substrate 1 and a thickness which would be determined according to the dopant density and a desired characteristic of 0 01 u03bcm 0 1 u03bcm when the dopant density is set to 10 17 cm 3 10 19 cm 3 in this isolation structure the p type selective epitaxial film 20 is arranged to connect between the p type drain region 212 and the substrate 1 however the lattice defects in the oxide 17 and on the boundary thereof normally function to increase the threshold voltage of p channel to thereby reduce the affect of leak current between the drain region 212 and the substrate 1 fig2 a 2f show the fabrication steps of the cmos device according to the present invention in the step of fig2 a an n well 210 is locally formed in a p type silicon substrate 1 and the entire surface of the substrate 1 is exposed a gate oxide film 3 n type poly silicon film 4 a first electroconductive film of low resistivity and a nitride film 5 a first insulating film are sequentially accumulated on the substrate surface the above three layer film and the substrate 1 are selectively etched along a pattern of isolation region to thereby form a trench 30 the trench 30 is formed by for example reactive ion etching rie such that an etched sidewall of the n well 210 and an opposed etched sidewall of the substrate 1 surround or border the trench 30.