electrode 108 but do not cover the gate bus lines 101 101 u2032 0042 fig3 c is a sectional view of a third embodiment of the present invention in fig3 c and similar to fig3 b the common electrode 119 overlaps the data electrode 108 however the common electrode 119 and the data electrode 108 do not overlap any portion of the gate bus line 101 the overlapping of the common electrode 119 and the data electrode 108 in effect creates a capacitor between the two layers 0043 fig3 d is a sectional view of a fourth embodiment of the present invention as illustrated the common electrode 119 does not overlap the data electrode 108 but overlaps the gate bus line 101 in addition certain portions of the data electrode 108 overlaps the gate bus line 101 the above conductive lines and electrodes in effect creates a capacitor between two overlapping conductive layers moreover certain capacitance is formed even between non overlapping conductive layers which are in near vicinity of each other in accordance with the present invention it is possible to achieve the high aperture ratio by using sog mode storage capacitor only or both sog mode storage capacitor and soc mode storage capacitor further it is possible to prevent the apparatus from a short which may be generated between the gate bus line the electrode and the.