55 the total number of matches between the outputs of the fsm states in the table is determined in this case there are no matches thus the total number of matches is zero in state 56 it is determined there are no more states with 34 don 39 t care 34 entries in step 58 the finite state machine is generated using the combination of values for the 34 don 39 t care 34 entries which resulted in the least number of matches that is the finite state machine is generated so that in the idle state the output value of c is 1 fig5 shows a resulting implementation of a finite state machine since each fsm state has a unique set of output values the finite state machine requires only three flip flops thus storage memory elements 12 includes a d flip flop 34 for the a output a d flip flop 35 for the b output and a d flip flop 36 for the c output a clock line 37 is also shown there is no need for additional storage elements 13 next state logic 11 includes logic 31 to generate an input to d flip flop 34 logic 32 to generate an input to d flip flop 35 and logic 33 to generate an input to d flip flop 36 logic 31 performs the following logic operation as will be understood from the information discussed above insig1 is an input value and idle is determined from the output values listed in table 3 above as being equal to as will be understood from the information discussed above wait is determined from the output values listed in table 3 above as being.