of the word line driver in the semiconductor memory device of the first embodiment of the present disclosure of fig2 in that at timing t 6 the word line bias control signal act goes high and the inverted signal act goes low so that the internal node node 2 is controlled to the word line set level voltage vpp and thereafter at timing t 4 the word line bias control signal act goes low and the inverted signal act goes high so that the internal node node 2 is controlled to the bit line high voltage vdd according to this embodiment the nmos transistor qn 3 can reduce the gate to source voltage of the nmos transistor qn 1 in the word line reset state from vpp vw to vpp u2212 vth_n3 vw where vth_n3 is the threshold voltage of the nmos transistor qn 3 similarly the pmos transistor qp 4 can reduce the gate to source voltage of the pmos transistor qp 2 in the word line reset state to vpp u2212 vth_p4 vw where vth_p4 is the threshold voltage of the pmos transistor qp 4 as a result the reliability of the nmos transistor qn 1 and the pmos transistor qp 2 can be improved also according to this embodiment the sources of the pmos transistors qp 1 in the word line drivers 120 a and 120 b are connected commonly to the internal node node 2 and the word line bias control circuit 200 is provided which switches a voltage supplied to the internal node node 2 between vdd and vpp as a result the source to drain voltage of the pmos transistor qp 1 in the word line reset state can be reduced from the.