element isolating films 21 the gap region 15 has a width a of 0 1 0 3 u03bcm at a widest portion of its entrance see fig5 b and a depth b of 0 2 0 5 u03bcm in addition an interlayer insulating film or an ono insulating film 16 made of for example silicon oxide film silicon nitride film silicon oxide film is deposited at a thickness of for example about 300 u00e5 converted to an equivalent oxide film thickness on upper and side surfaces of the floating gate electrode 23 and on the surfaces of the gap regions 15 further a conductive polycrystalline silicon film of a control gate electrode 22 is formed to cover the floating gate electrode and extends to fill the gap regions 15 while insulated from the floating gate electrode by the interlayer insulating film 16 that is parts of the control gate 22 and the interlayer insulating film 16 extend beyond the sides of the floating gate electrode 23 to the under sides thereof exposed to the gap regions 15 another interlayer insulating film 19 is deposited over the control gate electrode 22 and then the metal wiring layers 25 are formed on the interlayer insulating film 19 as shown in fig1 b which is taken along the line ib ib in fig2 the n type drain diffusion layer 12 and source diffusion layer 13 are formed in the surface of the p type silicon substrate 11 so as to partially overlap.