the horizontal pr line 3639 is formed and the semiconductor layer 3637 is formed over the gate insulating layer 502 so as to overlap with the gate line layer 3651 moreover the sd line 3652 that partly overlaps with the semiconductor layer 3637 is formed and the first interlayer insulating layer 505 covering the sd line 3652 is formed the pin photodiode 3630 is a photoelectric conversion layer which is a stack of a silicon layer 3653 p containing a p type impurity element an i type amorphous silicon layer 3653 i and a silicon layer 3653 n containing an n type impurity element further a second interlayer insulating layer 509 covering the pin photodiode 3630 and the first interlayer insulating layer 505 is formed and the ito electrode 3654 using a transparent conductive film is formed over the second interlayer insulating layer 509 the ito electrode 3654 serves as a contact electrode for connecting the sd line 3652 for the transistor including the semiconductor layer 3637 to the pin photodiode 3630 note that the pixel electrode which is formed using the same material and in the same process as the ito electrode 3654 is formed in the display region the case where the transistor electrically connected to the pin photodiode 3630 is a bottom gate transistor has been shown in fig8 b however there is no particular limitation on the structure of the transistor the transistor may have another bottom gate structure or a top gate structure instead in this embodiment an example of an electronic device including a display area a touch panel.