rate of u00bd for the hr sttc encoder according to the second embodiment and performs qpsk modulation so that the two compound codes are parallel concatenated the channel encoded input signals a 1 and a 2 are channel encoded symbols continuously output through the channel encoder i e outer encoder the symbols continuously output through the channel encoder are sequentially mapped to input terminals of the hr sttc encoder as the input signals a 1 and a 2 the input signal a 1 is output as a symbol s 11 through the first binary adder 401 and the first delay 403 and then transmitted via the first transmission antenna tx 1 and the symbol s 1 is fed back to the first binary adder 401 where it is added to a next input signal here a structure for adding accumulating a previous signal delayed by a delay to a next signal is generally referred to as an accumulator an output symbol s 12 calculated by adding the current input signal to a previous signal in the first binary adder 401 is output via the second transmission antenna tx 2 the input signal a 2 is output as a symbol s 21 through the second binary adder 405 and the second delay 407 and then transmitted via the second transmission antenna tx 2 and the symbol s 21 is fed back to the second binary adder 405 where it is added to a next input signal an output symbol s 22 calculated by adding the current input signal to.