transistor is connected in current mirror fashion to the gate and drain of transistor 46 which has its source connected to the drain of transistor 48 the source of transistor 48 is connected to ground and its gate is connected to node outa at the source of high side driver transistor 30a the gate of switching transistor 44 is also connected to the drain of cascode transistor 50 which has its gate biased to v cc the source of cascode transistor 52 is connected to the drain of transistor 52 which has its source biased to ground and its gate receiving the output of inverter 41 the gate and drain of transistor 46 and thus the drain of transistor 50 and the gate of switching transistor 44 are connected to the collector of p n p mirror transistor 54 which has its emitter biased to a voltage v that is significantly higher than v cc e g on the order of five volts higher the base of mirror transistor 54 is connected in current mirror fashion to the base and collector of p n p mirror transistor 56 that also has its emitter biased to v the collector of transistor 56 is connected via the source drain path of cascode transistor 57 which has its gate biased to v cc to the drain of transistor 58 transistor 58 has its source drain path connected in series with the source drain path of current source transistor 55 between the collector of transistor 56 and ground the gate of transistor 58 is connected to line bts a and the gate of transistor 55 is connected to line bias to conduct the specified current therethrough when transistor 58 is turned on.