retained high in the embodiment of fig5 in each channel the write enable signal we is applied to the write enable terminal we of the dut via the buffer 3b as is the case with the other signals di and a a chip select signal cs from the signal generation part 20 is applied via the and gate 3a to a chip select terminal cs of the dut when the output s from the logical comparator 3c goes to 34 1 34 the gate 3a is disabled inhibiting the passage therethrough of the chip select signal cs and hence placing the memory dut in the inoperative state thus further write can be inhibited as in the case of fig2 it is apparent that the construction for inhibiting the chip select signal cs on the basis of the result of comparison s is applicable to the fig4 embodiment as well in such a case the output s from the selector 3e in fig4 is used as the inhibit signal of course as described above according to the present invention the operation of writing or erasing data d of logic 34 1 34 or 34 0 34 is repeated for m memory cells of the address a in duts whose input output data has an m bit configuration and once the write is completed for the memory cell of any one.