memory accesses one electrode of the transistor is connected to a precharge voltage this electrode overlaps the dnw which is biased to the same precharge voltage this electrode provides the dnw n contact region application_number US 5355798 A description fig1 shows an integrated dram 110 memory arrays 120 1 120 2 in dram 110 alternate with read write r w circuitry blocks 130 1 130 2 130 3 along the horizontal direction in fig1 the memory column direction each memory array 120 is surrounded on the left and right by r w circuitry blocks 130 each memory array 120 is an array of memory cells each cell includes an nmos transistor 210 fig2 source regions 210 s and drain regions 210 d of transistors 210 of each memory array are formed in one or more p wells 216 each p well 216 is formed in a corresponding deep n well dnw 220 drain 210 d of each transistor 210 is connected to a bit line bl or a complimentary bit line not shown in fig2 source 210 s is connected to a memory capacitor 226 which is also connected to a reference voltage vref p well 216 is biased to a negative voltage u2212 1 0v in some embodiments in.