the read though less than the coercive voltage nevertheless may alter the polarization of some ferroelectric materials by using voltages for read that are low relative to the polarization voltage potential disturbs to the polarization state that might result are minimized fig1 is a plan view diagram illustrating the ferroelectric fet structures placed and electrically connected in rows and columns to form a memory array gate electrodes of fets in any given row of the array are connected with a word line in one embodiment the word line consists of a strip of conductive thin film 140 or 141 across the array consisting of any conductive material including platinum aluminum polysilicon and silicides the source and drains of fets in any given column of the array are electrically connected in one embodiment sources of fets in a given column are connected with strips of n type material formed in a p type substrate such as buried bit line 122 of fig1 drains are similarly connected with buried bit line 123 active area 124 span the area under the word between bit line 122 and 123 defining an area of thin silicon dioxide to make up the channel region regions outside the active area are covered with a thick layer of silicon dioxide to make up the field region between the transistors the ferroelectric material is formed on the inside edges of the buried bit line where the bit line intersects the word line for example ferroelectric material 133 and 134 are formed along the inside edge of bit line 122 and 123 respectively this ferroelectric material may overlap partially overlap or underlap the buried bit line the.