that more delay is needed in order to delay the delayed chip clock chip_clk_del to the desired delay point 60 in a second case represented by the waveform b when a positive edge of the delayed chip clock chip_clk_del occurs in the u03c0 interval after the desired delay point 60 a u2018 0 u2019 is latched at the prior positive edge of the chip clock chip_clk this u2018 0 u2019 indicates that less delay is needed in order to delay the delayed chip clock chip_clk_del to the desired delay point 60 thus in both of the previous two cases the delay of the delayed chip clock chip_clk_del was between u00b1 u03c0 of the desired delay point 60 i e was within the phase capture range of the d flip flop phase comparator 58 shown in fig5 in a third case represented by the waveform c a positive edge of the delayed chip clock chip_clk_del occurs before the u03c0 interval prior to the desired delay point 60 thus the delay of the delayed chip clock chip_clk_del is outside the phase capture region of the d flip flop type phase comparator 58 shown in fig5 as shown in fig6 in this case a u2018 0 u2019 is latched at the subsequent positive edge of the chip clock chip_clk this u2018 0 u2019 is then interpreted as less delay being needed in actuality.