in u s pat no 4 698 787 issued to mukherjee et al on oct 6 1987 titled u201c single transistor electrically programmable memory device and method u201d and its modification as disclosed for example in u s pat no 6 137 723 issued on oct 24 2000 titled u201c memory device having erasable frohmann bentchkowsky eprom cells that use a well to floating gate coupled voltage during erasure u201d a typical nvm cell such as is used in electrically erasable programmable memory eeprom devices uses two components a transistor and a capacitor in a classical stacked gate cell such as the cell disclosed in the above cited 39 787 patent a second polysilicon layer is used to create the capacitor in an alternative design such as that disclosed in the above cited 39 723 patent a well to floating gate capacitor is used both of these designs utilize the transistor to perform the program and read functions the erase function is performed through the transistor or through the capacitor coupling to the capacitor to optimize operating voltages a 4 transistor cell alternative such as that disclosed in u s pat no 6 992 927 issued on jan 31 2006 to poplevine et al utilizes a separate designated transistor to perform each function and therefore does not require high voltage switches the traditional programming methods are based upon hot electron injection in conditions created in the programming transistor in the more common implementation the hot electrons are injected from the channel when the source drain current is high in alternative implementations e g u s pat no 6 862 216 and the above cited 39 927 patent electrons are generated by band to band tunneling when current consumption is lower by a few orders of magnitude fig1 shows.