signals op lt 1 gt and op lt 2 gt therein the first and second information signals op lt 1 gt and op lt 2 gt stored in the mode register 13 may be transmitted to the odt controller 15 the control signal receiver 14 may receive the external control signal ctrl_ex through the odt pad 2 or not in response to the second information signal op lt 2 gt for example the control signal receiver 14 may receive and output the external control signal ctrl_ex through the odt pad 2 when the second information signal op lt 2 gt has a logic u201c high u201d state and the control signal receiver 14 may not receive the external control signal ctrl_ex through the odt pad 2 when the second information signal op lt 2 gt has a logic u201c low u201d state the odt controller 15 may receive the write enable signal wt_en the read enable signal rd_en and the external control signal ctrl_ex as input signals and may generate an odt enable signal odt_en for activating the odt circuit 3 in response to the first and second information signals op lt 1 gt and op lt 2 gt configurations and operations of the odt controller 15 will be described hereinafter with reference to fig2 as illustrated in fig2 the odt controller 15 may.