for these modes however for cascaded programming and other applications where clkout and dout are required the speed of cclk must be less than 1 mhz in these modes to specify the desired application function the user must load the internal sram which the cla device uses to store configuration information the user does not need to generate the sram bit pattern this is done for the user by the configurable logic array software system the user must also determine the method by which the configuration ram is loaded many factors including board area configuration speed and the number of designs concurrently implemented in a device can influence the user 39 s final choice upon power up the cla goes through a boot or initialization sequence this sequence initializes all core cells repeaters i o logic clock distribution logic and open collector controls as well as the configuration register and external memory address counter discussed below core cells become flip flops with a n and b n inputs i 0s are set as ttl inputs only with the pull up on during the initialization sequence the cla device 100 drives the con pin low since power up initialization uses an internal clock for timing no external clock source is required once initialization is complete con which is an open collector output is released it must be pulled high by an external pull up resistor after power up initialization is complete the cla device 100 is ready to accept the user 39 s configuration after con has been released for a minimum period of time the user.