the input signals of the filer 10 namely the control signals including the chip enable signal ce the write enable signal we and the output enable signal oe and the address signal the transition detection circuit 41 detects a transition of a given bit in the control signals and the address signals for example the transition detection circuit 41 detects a change from h to l in any of the control signals ce we and oe and a change from l to h or vice versa in the address signal when such a transition is detected the transition detection circuit 41 generates the transition detection signal stdpz the transition detection signal stdpz is applied to the ref act comparator circuit 44 and the pulse width expansion circuit 42 the ref act comparator circuit 43 compares the transition detection signal stdpz with the ref request signal refpz and outputs the resultant ref act selection signal refz to the core control circuit 44 if the transition detection signal stdpz leads to the ref request signal refpz in terms of timing the ref act selection signal refz is l in contrast if the transition detection signal stdpz lags behind the ref request signal refpz the ref act selection signal refz is h the act request signal actpz is generated from the signals that have passed through the filter 10 as in the case of fig1 0041 fig8 is a timing chart of an operation of the circuit shown in fig7 more particularly fig8 illustrates a case where the ref request signal refpz leads to the act request signal actpz the transition detection signal stdpz generated by the transition detection circuit.