the invention may be practiced without these specific details in the interest of not obscuring presentation of essences and or embodiments of the present invention in the following detailed description processing steps and or operations that are well known in the art may have been combined together for presentation and or for illustration purpose and in some instances may not have been described in detail in other instances processing steps and or operations that are well known in the art may not be described at all a person skilled in the art will appreciate that the following descriptions have rather focused on distinctive features and or elements of embodiments of the present invention in semiconductor manufacturing industry various types of active semiconductor devices such as transistors including cmos fet of n type nfets and p type pfets may be created or formed on a single substrate of semiconductor by applying well known feol processing technologies the well known feol technologies may include processing steps and or operations of inter alia cap deposition photo resist mask formation photolithography hard mask formation wet etching reactive ion etching rie ion implantation and chemical mechanical polishing cmp to list a few during and or after the formation of transistors stress liners of the same or different types may be applied to the transistors i e nfets and pfets for device performance improvement improvement in device performance may come from improved mobility of electrons in the channel region of nfets and or holes in the channel region of pfets brought by strains induced by the stress liners in the following detailed description well known device processing techniques and or steps may not.