sram device structure that will be used for a subsequent buried contact region gate insulator silicon dioxide 3 is removed via use of a buffered hydrofluoric acid solution this is shown schematically in fig1 b photoresist removal is performed using plasma oxygen ashing and careful wet cleans fig2 a and fig2 b show the creation of a first polycide gate structure a first layer of polysilicon 5 is deposited using low pressure chemical vapor deposition lpcvd processing at a temperature between about 480 u00b0 to 620 u00b0 c to a thickness between about 500 to 1500 angstroms the polysilicon can be grown intrinsically and doped via ion implantation of arsenic or phosphorous at an energy between about 30 to 80 kev at a dose between about 5e13 to 5e15 atoms cm 2 the polysilicon layer 5 can also be deposited using insitu doping procedures by incorporating either arsine or phosphine into the silane flow a first layer of tungsten silicide 6 is next deposited again via use of lpcvd procedures at a temperature between about 420 u00b0 to 600 u00b0 c to a thickness between about 1000 to 2000 angstroms using tungsten hexafluoride and silane as reactants finally a first insulator layer of silicon oxide 7 is deposited using lpcvd or plasma enhanced chemical vapor deposition pecvd procedures at a temperature between about 400 u00b0 to 800 u00b0 c to a thickness between about 700 to 3000 angstroms using tetraethylorthosilicate teos as a source photolithographic and reactive ion etching rie procedures using photoresist mask 8 and using chf 3 as an etchant for silicon oxide layer 7 and cl 2 as an etchant for both tungsten silicide layer 6 and polysilicon layer 5.