drive signal sin are constituted by the 3 bit selection signals respectively depending upon the combination of the bits no recording or one of the plural sorts of drive waveform signals four sorts in the present embodiment i e fire 01 04 is selected the main latch circuit 32 holds the parallel signals which are generated by the main serial parallel conversion circuit 31 so as to correspond to the respective actuators 3 of the recording head 1 in accordance with rising edges of pulses of the latch signal lat transmitted from the gate array 14 in the first circuit portion of the first drive wave form signal generating circuit 35 the drive waveform data signal data 1 serially transmitted from the gate array 14 in synchronization with the clock signal clk 2 is inputted directly to the latch circuit 35 a while in the second circuit portion the drive waveform data signal data 1 is inputted to the latch circuit 35 c in synchronization with an inverted signal of the clock signal clk 2 which has been passed through the inversion circuit 35 b in the first circuit portion of the second drive waveform signal generating circuit 36 the drive waveform data signal data 2 serially transmitted from the gate array 14 in synchronization with the clock signal clk 2 is inputted directly to the latch circuit 36 a while in the second circuit portion the drive waveform data signal.