feature a buffer synchronizes phase data to a reference signal before inputting it to a digital modulator of the phase locked loop application_number US 43657203 A description the present invention will be discussed with reference to preferred embodiments of the invention the preferred embodiments discussed herein should not be understood to limit the invention furthermore for ease of understanding certain method steps are delineated as separate steps however these steps should not be construed as necessarily distinct nor order dependent in their performance fig1 illustrates a fractional n pll 100 according to an embodiment of the invention a reference signal 105 at a reference frequency f ref is applied to one of the inputs of a phase frequency detector 110 a second other input to the phase frequency detector 110 is supplied by a carryout signal 165 at a frequency f 1 from variable divider 160 which comprises a programmable counter in preferred embodiments the phase frequency detector 110 compares both input frequencies f ref and f 1 and generates an output that is a measure of their phase difference if there is a difference in frequency between the two signals input to the phase frequency detector 110 the output of the phase frequency detector 110 is a signal that vanes at the difference frequency the output of the phase frequency.