be selected between the ics tdi and tdo pins via the tlm 39 s tap link control bus exactly as the ic and core tap domains were described being selected once selected the oct interface can serve as a master tap interface to a slave tap interface i e a conventional 1149 1 tap interface on another ic thus an ic having the tlm architecture improvement shown in fig1 a would have the conventional 1149 1 tap interface 1102 plus the selectable oct interface 1106 for mastering the tap interface of another ic or ics 1108 while one oct interface 1106 is shown in fig1 a any number of oct interfaces may be provided fig1 b illustrates the oct interface 1106 being coupled 1110 to a tap interface of another ic 1108 as seen in fig1 b the oct interface consists of buffers which couple the tdi oct tck tms oct tdo oct and trst tlm architecture signals up to tdo tck tms tdi and trst pads 1104 respectively of the ic in which the tlm architecture resides the tdo tck tms tdi and trst pads 1104 can be coupled to the tdi tck tms tdo and trst pads of the other ic 1108 via connections 1110 to provide access the tap domain of the other ic 1108 the tap domain of the other ic could be similar to that shown in fig1 a fig1 14 illustrate the changes required to the input and output linking circuitry of fig5 7 respectively to add the oct interface of fig1 a as seen in fig1 an additional and gate 1202 is added to provide gating on and off the tms input tms oct of the oct interface as.