signals the v dis vector must be changed to low by decoding the proper input values fig6 depicts yet another embodiment wherein the test vector decode circuit 10 is configured to allow latching in response to a low signal output from a nand gate 26 as in the previous embodiment a high wcbr signal will cause latching only as long as v dis transmits a high signal it should be further noted that wcbr and sv are not the only signals that could be used to latch and reset the output vectors they have been identified in this specification for demonstrative purposes only fig7 illustrates that in general all that is needed is some sort of operations circuit 28 configured to receive at least one input a perform some function based on that input and transmit at least one output b in addition the operations circuit 28 is configured to perform its function in response to receiving a function prompt signal 30 however that signal 30 is subject to being blocked by any embodiment of the current invention such as some form of lockout circuit 32 nevertheless the operations circuit 28 could be configured to once again receive the latching prompt signal in response to a reset prompt signal 34 one of ordinary skill can appreciate that although specific embodiments of this invention has been described for purposes of illustration various modifications can be made without departing from the spirit and scope of the invention for example the memory device could be configured to provide a test vector lockout signal from an external device 22 that is independent from the test vector decode circuit 10 and the output.