order deciding part 108 which is disposed in the address temporary memory part 103 it is assumed that the first processor 105 the second processor 106 and the third processor 107 demand accesses to the main memory part 101 simultaneously the requests are made using the request signals 209 210 and 211 after outputted the request signals 209 210 and 211 are supplied to the priority order deciding part 108 which is disposed in the address temporary memory part 103 if the first processor 105 has the highest priority rank and the third processor 107 has the lowest priority rank the priority order deciding part 108 accepts the access from the first processor 105 first the priority order deciding part 108 thereafter notifies the first processor 105 of the acceptance using the request signal 209 notified of the acceptance of the request the first processor 105 outputs an address control signal pair to the address bus 207 at the same time the decision request signal 219 is outputted to the empty address search part 109 so that the empty address search part 109 accepts the address control signal pair from the first processor 105 receiving the decision request signal 219 the empty address search part 109 recognizes an empty address within the address control signal part 112 using the empty flag information which indicates an empty address and outputs the empty address signal which indicates the empty address to the input address generation part 110 at this stage as the empty flag information an empty flag may be assigned to each address within the address control signal part 112 the input address generation part 110 outputs the empty.