this embodiment fig6 b is a timing chart showing the operation of the reset transistor in the floating diffusion portion as step 1 of the reset operation in this embodiment after reducing the impressed voltage of the vr terminal from vcc to vcc u2212 1 the impressed voltage of the gate electrode of the reset transistor is set from 0 v to vcc owing to this vcc u2212 1 is written to the floating diffusion portion in a state in which the channel of the reset transistor is sufficiently turned on as the subsequent step 2 the impressed voltage of the vr terminal is returned from vcc u2212 1 to vcc owing to this in the floating diffusion portion vcc u2212 vth is written the channel of the reset transistor is turned off and shifts to the state of sub threshold region owing to the above reset operation vcc u2212 vth in particular approximately vcc u2212 0 5 v which is a voltage higher than vcc u2212 1 v is written to the floating diffusion portion here the voltage written in the floating diffusion portion depends on the vth of the reset transistor however by carrying out cds correlated double sampling the dependency is eliminated further by creating a state in which the channel of the reset transistor turns off.