regrow step can be performed to thicken the tunnel oxide referring now to fig6 a layer of polysilicon 34 is deposited over the surface of the substrate and within the trench to a thickness of between about 1000 to 4000 angstroms and doped an interpoly dielectric 36 such as ono silicon oxide silicon nitride silicon oxide is deposited over the polysilicon layer 34 a second polysilicon layer 38 is deposited over the dielectric 34 to a thickness of between about 2000 to 4000 angstroms and doped the first and second polysilicon layers and the interpoly dielectric layer are patterned to form a stacked polysilicon gate structure the first polysilicon layer 34 forms the floating gate and the second polysilicon layer 38 forms the control gate of the memory cell arsenic ions 39 are implanted into the substrate using the polysilicon gate structure as a mask to form source and drain regions 40 on either said of the stacked gate back end processing continues as is conventional in the art and as is illustrated in fig7 silicon dioxide spacers 42 are formed on the sidewalls of the stacked polysilicon gate structure a dielectric layer 44 such as borophosphosilicate glass bpsg is deposited over the surface of the substrate contact openings are etched through the dielectric layer to expose the drain regions 40 where contact is desired metal layer 46 typically aluminum is deposited and patterned to complete the contacts a top view of the completed memory cell is shown in fig8 view 7 7 is that shown in fig7 the floating gate 36 and the control gate 38 are illustrated the metal 46 completing contact is shown contacting the drain region 40 source region.