volatile memory device of the programmable and electrically erasable type implementing the method and comprising a memory cell array organized in a row and column layout and divided in array sectors including at least one row decode circuit portion being supplied positive and negative voltages the method is applied whenever the issue of the erase algorithm is negative and comprises the following steps forcing an incompletely erased sector into a read condition scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state identifying and electrically isolating the failed row re addressing from said failed row to a redundant row provided in the same sector re starting the erase algorithm application_number US 67522103 A description first of all the mechanisms that cause an erase fail condition shown with reference to the prior art can be analyzed in detail in order to understand all the aspects of this invention an erase fail condition is caused by the negative charge pump circuit 12 arranged to energize the control gate region hereinafter abbreviated to u201c gate region u201d of a failed memory cell 4 becoming shorted to the positive charge pump circuit 11 which is energizing the source region 6 of the cell and the common substrate 5 of all the cells in a sector with charge pump circuits of conventional design the voltage used during erase operations can be maintained not even if the failure occurs just at one cell the voltage values are those provided by the splitting effect caused by the short circuit and are transferred to both the control gate regions of the cells in the same row as the failed cell and to the gate regions of the other cells in the same sector however these are insufficient voltages.