inactive i e standby current may be reduced in some embodiments of the invention various signals related to the operation of a memory section should be driven to a known logic level in order to fully deactivate operation of the memory section including the row decoder 240 and the sense amplifier gap control circuit 250 fig3 illustrates an isolation circuit 300 according to an embodiment of the invention that may be used with memory section power control logic such as the memory section power control logic 280 of fig2 to set the logic levels of the various signals for a memory section a portion of memory section power control logic is illustrated in fig3 in particular a two input nand gate 260 is coupled to a switch 270 to provide a power down pd signal for controlling provision of a supply voltage through the switch 270 the isolation circuit 300 includes two input nand gate 310 and two input nor gate 320 an inverter 330 is coupled to receive the pd signal and provide an inverted signal to one of the inputs of the nand gate 310 the nor gate 320 also is coupled to receive the pd signal the nand gate 310 and the nor gate 320 further receive control signals controla controlb respectively from upstream logic circuitry and generate output signals outf out signals based on the logic levels of the pd signal and the controla controlb signals the controla controlb signals may represent various known memory section control signals for controlling operation of.