standby bus arbitor 4 2 using an empty area of a standby memory bus in accordance with the content of the queue 3 in the asynchronization mode a memory write operation from the active system to the standby memory 2 2 is not performed the synchronization asynchronization mode is set by an operation mode register r1 1 one bit in the active processor 1 1 the active standby mode is set by an active standby setup register r2 1 in the active system when logic 34 0 34 is set in the register r2 1 a 0 system processor is active and a 1 system processor is standby when the active standby setup register r2 1 of the active system is set at logic 34 1 34 the 0 system processor is standby and the 1 system processor is active in this case a register r2 2 stores an inverted content of the register r2 1 operation mode registers r1 1 and r1 2 and the active standby setup registers r2 1 and r2 2 can be set in accordance with a program fig3 shows a detailed arrangement of the duplex processing apparatus shown in fig1 and particularly a detailed arrangement of the queue 3 referring to fig3 reference numerals 31 1 and 31 2 denote input selectors 32 1 and 32 2 output selectors 33 an address queue 34 a data queue and 35 a queue controller reference symbol s1 denotes a stop request line for sending a request for stopping the opposite processor between the active and standby processors 1 1 and 1 2 reference symbol s2 denotes a signal line for reading a stop address.