dt8 which form an 8 line data bus for the transfer of data dat between the integrated circuit ic and the ram equipment rm the direction of data transfer is controlled from the processing unit pu the address data bus ba1 to ba10 dt1 to dt8 is used on a multiplex basis in different time intervals for either byte addressing or data transfer this multiplexing also being controlled from the processing unit pu as an alternative a separate 8 line data bus can be provided but this requires an additional eight connecting pins on the integrated circuit ic fig2 shows schematically the addressing of the chapter size memory units together with the addressing of the memory unit 8 bit bytes in the ram equipment rm the 64 memory units ch1 ch2 ch64 have respective unit select leads cs1 cs2 cs64 connected to them a unit select signal on a chosen one of these select leads as determined by the decoder dec in accordance with the particular 6 bit code on the address lines ca1 to ca6 will select the relevant memory unit for data transfer when less than the full number 64 of memory units is provided the unit select leads pertaining to omitted memory units are not used and thus correspond to invalid addresses however because of the provision of the decoder dec each memory unit which is present.