data retention errors can be expected since a limited number of data retention errors can be corrected as is well known in the art ecc techniques allow a limited number of bits to be corrected therefore the refresh rate in the reduced power refresh mode should not be so low that more errors are generated in a group of data than can be corrected by the ecc techniques this reduced refresh rate can significantly reduce the power consumed by the dram 122 it is possible for the data stored in the dram array 140 to be modified between refreshes by for example writing data to the dram array 140 for this reason each time data are written to the dram array 140 the ecc logic 144 resets the flag bit appended to the syndrome corresponding to the data stored in the memory cells to which the data are written one of the advantages of using the process shown in fig2 is that in many cases it will be necessary to generate and store syndromes for very few memory cells in the dram array 140 when the dram 122 is idle as it generally will be when in a reduced power refresh mode such as a self refresh mode data will not be written to the dram array 140 as a result the flag bit appended to almost all syndromes will still be set thus making it unnecessary to generate and store syndromes for almost all of the memory cells in the dram array 140 as a result the power consumed by the dram 122 is reduced by the amount of power that would be consumed in performing these syndrome generating.