v r in standby mode the nvm cells connected to bit line 201 are not selected i e word line 205 is at a u201c low u201d state see waveform 303 of fig3 and thus are not activated consequently the electrical conductance of nvm cell 202 is low no active steady current path exists for a current to flow from read voltage bias v r to the ground reference through an nvm cell attached to bit line 201 the voltage v r on bit line 201 turns on nmos transistor mn 3 which pulls node 204 signal d waveform 307 to the ground reference thus rendering pmos transistor mp 4 conducting pulling node 203 signal u201c d u201d waveform 306 to core u201c high u201d voltage v cc as a result complementary data output terminals 203 and 204 signals u201c d u201d and u201c d u201d of read circuit 200 respectively are set to u201c high u201d and u201c low u201d states u201c default states u201d in reading mode i e between times t 0 and t 1 of fig3 the voltage at the gate terminal of pmos transistor mp 1 i e signal u201c sense enable u201d waveform 302 of fig3.