respect to one another the only precaution is that the length intervals between the different paths be compatible with the width of the cutting line for example of the saw and its positioning tolerances in practice this amounts to preferentially providing a minimum interval between sections 5 towards sections 4 smaller than the positioning tolerances of the cutting with respect to the chip edges this condition enables guaranteeing the non deterministic character of the identifier generation as a specific example the most currently used saws are designed for cutting paths interval between two chips 2 of a same wafer 1 on the order of 100 u03bcm and the cutting line corresponding to the width of the saw has a thickness on the order of from 20 to 25 u03bcm the tolerances in the saw alignment are on the order of 5 u03bcm which leaves a 10 u03bcm range to differentiate the lengths of the conductive sections the number of conductive paths generating and storing the identification numbers depends on the application and on the chip size the respective minimum lengths of the buried conductive depositions or of the metallization levels formed in integrated circuits with respect to the chip sizes allow generation of identifiers over a large number of bits several hundreds if need be conductive sections may be formed in buried layers active layers or in upper metallization levels interconnection levels an advantage of buried layers is that they avoid the occurrence of splinters in the cutting as is the case for metal levels it should be noted that although a saw cutting line generally causes a scaling at the front surface of the chip this scaling is not disturbing it only adds a random element in.