at pin 3 that is electrical noise will probably exist at pin 3 in the form of brief voltage spikes these brief spikes can briefly drive q1 into conduction causing brief current pulses through r causing brief voltage spikes on vout the capacitor c absorbs the current pulses which would otherwise traverse through resistor r the small voltage rise in capacitor c due to the absorbed charge is dissipated by subsequent discharging through resistor r capacitor c preferably has a value of 10 picofarad and resistor r preferably has a value of 100k ohms 1 the construction of transistor q1 is significant it is a lateral pnp structure fabricated using cmos complementary metal oxide semiconductor techniques fig3 shows a lateral pnp a lateral pnp is different from a 34 vertical 34 pnp one type of which is shown in fig4 in a parasitic vertical pnp the collector c is held at the same voltage potential as the substrate such a transistor could not be used in a straightforward manner for the invention because in such a case vout in fig2 which is connected to the collector c would also be held at substrate potential however by using a lateral pnp the collector is not held at substrate potential as indicated in fig3 but its voltage can float thus the use of a lateral pnp transistor allows the collector c to rise in voltage above vss thus allowing a voltage drop to occur across resistor r 2 transistor q1.