occurs faster than the access times of memories suitable for waveform storage control logic 34 thus responds to a cache write request on line 92 by writing the waveform memory data at the required cache memory address within two cycles the details of the convolution unit are shown in fig9 coefficient logic 100 derives the n coefficients as a function of current address fractional part 4 according to the master state counter as interpreted by control logic 101 this can be accomplished according to various algorithms some of which are described in patent application ser no 07 462 392 multiply accumulator 102 forms the sum of products required by the interpolation algorithm from the coefficients 103 times the cache memory data 104 control logic 101 can reset the cumulating sum in the accumulator using and gates 105 at the beginning of each new channel the ultimate sum of products is then formatted for example into a serial data stream for further processing by output formatting logic 106 provision is also made by use of multiplexers 107 and 108 to use any idle cycles of the multiply accumulator one of which is necessary if single port cache memory has been used as described above for alternate functions for example the output of the multiply accumulator 39 s final sum can be routed into one input of the multiplier by multiplexer 107 while a volume scaling number is routed into the other input by multiplexer 108 allowing the idle cycle to provide an individual volume control for each channel before the final sum of products is routed to output formatting logic 106 the foregoing.