write input into the latch in a manner more fully described below the data bus 23 and outputs 21 and 22 are each shown as single conductors of a bus having n conductors although only a single latch is shown for simplicity however in practice a group of n latches is used to implement a register where n is typically 4 6 8 16 32 or 64 but may be any desired value the number of latches in a given register is typically equal to the number of bus conductors but may differ in some cases referring to fig3 a description of the latch and it operation is provided the latch includes inverters 31 and 32 a feedback switch 33 and an input switch 34 the switches are typically implemented as transmission gates in mos technology this arrangement is conventional as thus far described for a typical prior an d latch however the operation of the switches provides for an improved operation as follows when the genetic write and unique addresses are valid a write function is implemented by turning on input switch 34 and turning off feedback switch 33 this allows the input signal on line 38 to set the state of the latch by means of inverters 31 and 32 so that the q output is high if the input signal on line 38 is high and the q output is low if the input.