dp system 100 comprises a pair of processors such as a first processor 110 and a second processor 150 for example each processor 110 and 150 includes a memory controller mc 115 and 155 to enable direct communications with an associated memory 120 and 160 via links 125 and 165 respectively moreover the memories 120 and 160 may be independent memories or portions of the same shared memory as specifically shown in fig1 processors 110 and 150 are coupled to an input output hub ioh 180 via point to point links 130 and 170 respectively ioh 180 provides connectivity between processors 110 and 150 and input output i o devices implemented within dp system 100 in addition processors 110 and 150 are coupled to each other via a point to point link 135 according to one embodiment of the invention these point to point links 130 135 170 may be adapted to operate in accordance with u201c common system interconnect u201d specification developed by intel corporation of santa clara calif referring now to fig2 an exemplary block diagram of a multiprocessor mp system 200 in accordance with one embodiment of the invention is shown similarly mp system 200 may be a desktop or mobile computer a server a set top box personal digital assistant pda alphanumeric pager cellular telephone or any other type of wired or wireless communication devices herein according.