on a per connection basis while also providing functionality that is required to support the dlc protocol the cell pool ram is partitioned as shown in fig9 the watm cell region 902 is partitioned into a number of 56 byte regions each region having a header 906 and a body 908 and which serve to store watm cells in the transmit and receive directions watm cells can then be linked by managing pointers using the following technique that merge fifo queue management and dlc operation requirements in a single novel architecture advantageously atm queue management and dlc is merged in such a manner as to support virtual queues on a per connection basis with the capabilities of watm cell retransmission and cell reordering with reference now to fig1 a there it shows the partitioning of ram memory residing within the pointer processor unit shown in fig2 in the transmit direction a vci region consists of data structures which permit the emulation of fifo functionalities of the xpointer 1004 and xqueue 1006 regions respectively the xpointer region contains free start address pointers which indicate where watm cells can be stored in the cell pool ram these pointers are stored in a fifo manner using any of a variety of techniques the xqueue region contains the address pointers of stored cells in the cell pool ram fig1 b shows the structure of the xpointer and xqueue regions the size of the xpointer region determines the queue size for a given connection based on its quality of service qos requirements a number of address pointers which guarantee the required qos is stored in this region these pointers are referred.