clock pulse the first data packet 8 1 is forwarded from the input shift register 60 1 as bit group 1 1 into the bit group register 40 1 and the second data packet 8 2 is forwarded simultaneously from the input shift register 60 2 as bit group 1 2 into the bit group register 40 2 in each case in parallel with a width of 128 bits and are temporarily stored there as a result of the direction information in this exemplary embodiment both temporarily stored bit groups are intended for forwarding to the output 90 1 at the next bit group bus clock pulse the bit group 1 1 is forwarded from the bit group register 40 1 by the bit group bus 20 simultaneously to all output filters 50 while only the output filter 50 1 releases the forwarding all other output filters 50 2 50 n block the forwarding of the bit group 1 1 as bit group 5 1 at this bit group bus clock pulse therefore the bit group 5 1 is read into the output memory 10 1 and stored in a bit group memory register at the next bit group bus clock pulse the bit group 1 2 temporarily stored in the bit group register 40 2 is likewise forwarded by means of the bit group.