controller 18 will write the line of data retrieved from system memory 16 to cache 10 cache controller 18 determines what cache line address to store the retrieved line of data depending upon the particular mapping technique being implemented in addition cache controller 18 will generate the tag address that is stored at the same address as the cache line address in tag memory 60 cache controller 18 also coordinates the writing of the associated parity bits generated by a parity bit generator 120 parity bit generator 120 generates the parity bit s as determined by the particular parity scheme being implemented for example if even parity is chosen parity bit generator 120 would count the number of u201c one u201d bits in the retrieved data line if the number of u201c one u201d bits were odd the associated parity bit would be u201c one u201d conversely if the number of u201c one u201d bits were even the associated parity bit would be u201c zero u201d should odd parity be chosen the associated parity bit would be the complement of the even parity bit it will be appreciated that a single parity bit s could be used for the combined tag and data parity in such an embodiment the parity bit s would be generated based upon both the retrieved data line and the tag this combined parity bit s could be stored in either the data store 55 or the tag memory 60 data store 55 may be configured as either a write through or a write back data store such that not only reads from system memory 16 are cached but also writes to system memory 16 are cached as well in a write through configuration each write cycle to system memory 16 to.