a low electrical resistivity such a metallization enables relaxed mask alignment and etching tolerance requirements and is therefore useful in vlsi circuits application_number US 28137888 A description referring now to fig1 there is shown a body of single crystal silicon 10 having already formed therein source and drain regions 11 and 12 and field oxide regions 13 14 and 15 the source and drain regions formed by ion implantation through a thin thermally grown silicon dioxide layer not shown on the surface of silicon body 10 polysilicon gate 16 on top of gate oxide 17 and polysilicon element 18 on top of field oxide 13 are located on the surface of silicon body 10 both polysilicon gate 16 and element 18 protected by oxide sidewall spacers 19 20 21 and 22 as is known the spacers may be formed typically either by high pressure oxidation or chemical vapor deposition of a silicon dioxide layer on the surface of the device followed by anisotropic reactive ion etching to selectively remove portions of the oxide layer referring now to fig2 after formation of the polysilicon elements the source drain and oxide sidewall spacers a layer 23 of tungsten is selectively deposited on the exposed single crystal and polycrystalline silicon surfaces the portions 23a b c.