the memory core 194 and present a signal to the memory core 194 additionally the register 196 may receive the clock signal clock the register 196 may also present receive signals to from the i o buffer 198 the i o buffer 198 may be controlled by the signal tristate additionally the i o buffer may present receive the signal data referring to fig7 a detailed diagram of a memory cell 210 is shown the memory cell 210 may be implemented as a cell of the memory core 194 the memory cell 210 generally comprises a device 211 a device 212 and a block or circuit 213 in one example the devices 211 and 212 may be implemented as one or more nmos transistors however other types and polarities of transistors for example pmos transistors may be implemented to meet the design criteria of a particular application the block 213 may be implemented as a latch the latch 213 generally comprises an inverter 214 and an inverter 215 an output of the inverter 214 may be connected to an input of the inverter 215 an output of the inverter 215 may be connected to an input of the inverter 214 the memory cell 210 may receive a signal e g bl a signal e g blb and a signal e g wl the transistors 211 and 212 may be gated by the signal wl the transistor 211 may couple the signal bl to an input of the inverter 214 the transistor 212 may couple the signal blb to an input of the inverter 215 referring to fig8 a detailed diagram of a memory latch 220 is shown the memory latch 220 may be implemented as a latch of the.