s application ser no 08 775 769 referenced above 0097 fig1 is a block diagram of a phase corrector shown in fig8 the phase corrector corrects for the frequency offset in the carrier and the carrier phase jitter the carrier frequency offset is tracked by a second order pll 1400 which uses the phase error 1410 between the symbols from the decoder and the input symbols the phase jitter is tracked by a 60 tap real adaptive fir filter 1420 since the jitter is not very large u2153 rd of the filter taps are updated each symbol the amplitude error between the output of the phase corrector and the decision symbols from the decoder is sent to the gain tracker in the equalizer the decision symbol from the decoder is then rotated 1420 by the same amount as the input symbol but in the reverse direction the error between the rotated decision symbols and the input symbols is used to update the equalizer taps 0100 fig1 is a block diagram of a sync recovery circuit shown in fig8 the sync recovery section estimates the frequency difference between the local and remote sample clocks this delay will appear as a constant frequency offset introduced by the channel and reflected in the equalizer taps to compute this constant shift a dft 1500 is done on the equalizer taps to generate the b 4 and u2212 b 4 spectral components where b is the baud rate the phase difference between the components is the sync error which is filtered through a second.