and d 2 unit 35 and 16 32 bit b registers forming register file 31 the functional units of each data path access the corresponding register file for their operands there are two cross paths 27 and 37 permitting limited access to one register in the opposite register file each pipeline stage central processing unit 1 includes control registers 13 control logic 14 and test logic 15 emulation logic 16 and interrupt logic 17 program fetch unit 10 instruction dispatch unit 11 and instruction decode unit 12 recall instructions from level one instruction cache 2 and deliver up to eight 32 bit instructions to the functional units every instruction cycle processing occurs in each of the two data paths 20 and 30 as previously described above each data path has four corresponding functional units l s m and d and a corresponding register file containing 16 32 bit registers each functional unit is controlled by a 32 bit instruction the data paths are further described below a control register file 13 provides the means to configure and control various processor operations fig2 illustrates the pipeline stages 200 of digital signal processor integrated circuit 100 prior art these pipeline stages are divided into three groups fetch group 210 decode group 220 and execute group 230 all instructions in the instruction set flow through the fetch decode and execute stages of the pipeline fetch group 210 has four phases for all instructions and decode group 220 has two phases for all instructions execute group 330 requires a varying number of phases depending on the type of instruction the fetch phases of the fetch group 210 are program address generate phase 211 pg program address send phase 212 ps program access ready wait stage 213 pw and program fetch.