where the output of the nand gate x2 is high so as to keep the switch q4 closed now when the bottom of the resistor r2 goes low in response to the next current pulse of fig2 d which occurs at the trailing end of the switch control voltage pulse of fig2 b the input 50 of the nand gate x3 is driven low so that its output goes high this causes the output of the nand gate x2 to go low and open the switch q4 this condition remains until the next pulse in fig2 c again causes the bottom of the resistor r1 to go low and the operation previously described is repeated with the circuit thus far described false triggering of the switch q4 can occur when the switch q2 is opened if the load 10 is inductive for the following reasons a voltage is produced due to the cessation of current in the load 10 between the reference bus and the bus 26 as indicated by the phantom circle dv dt this dv dt voltage causes currents to flow through resistors r1 and r2 via stray capacitances between them and the bus 2 these stray capacitances are indicated in phantom at 56 and.