fig5 adjacent input signals are inverted by supplying the first through the fourth input terminals 11 in to 14 in with the input signal of u201c hlhl u201d or u201c lhlh u201d as a result of this it is possible to work around the above mentioned case a result obtained by the first and the second output terminals 21 out and 22 out is similar to that of the first embodiment illustrated in fig3 in addition test of the terminal open in the semiconductor device where a plurality of semiconductor circuits 10 a each comprising the logic circuit 100 a illustrated in fig5 that are arranged in parallel is carried out as follows first the first through the fourth input terminals 11 in to 14 in of all of the semiconductor circuits 10 a are connected to the first through the fourth input pins in 1 to in 4 of the semiconductor testing apparatus the lsi tester in common respectively then the first through the fourth input terminals 11 in to 14 in are supplied with the bit parallel first input signal u201c hlhl u201d where logic levels are inverted in turn thereafter the first through the fourth input terminals 11 in to 14 in are supplied with the bit parallel second input signal u2018 lhlh u201d which is obtained by inverting the bit parallel first input signal thus it is possible to.