gate to detect illegal or invalid states the output of this detection logic sets a state catcher the output of the state catcher is readable by scan logic so that the occurrence or non occurrence of the invalid state may be read by test hardware application_number US 94758501 A description 0007 fig1 is a schematic diagram of an example dynamic logic gate with logic attached to detect invalid states on its outputs in fig1 the circuitry inside box 102 is an example dynamic logic gate in this case the gate is an and gate that takes inputs a and b their complements an and bn and produces the logical and of a and b on pair of complementary signals c and cn when the clock ck is high note that this gate is only an example and that the logic function implemented could be any simple or complex logic function with an arbitrary number of inputs and two outputs wherein the outputs have at least one invalid state note also that the invalid state for this gate is when both outputs c and cn are both high the complementary outputs of gate 102 c and cn are connected to the inputs of logic function 104 in fig1 the logic function is a nand gate a nand gate is chosen as the logic function in this example because the invalid state for gate 102 is when both outputs are high accordingly when an invalid state appears on the outputs c and cn the output of logic function 104 will go low all other times the output of logic function 104 will remain high likewise an and gate could have been chosen and the output would.