204 204l and 204u or the content of the control register is read from the host apparatus an active low read signal 218 is supplied to the memory chip 203 an active low write signal wr 219 is supplied to the memory chip 203 the control register 220 outputs the address select signal sel for controlling the address selector 205 more specifically the address select signal sel for switching between the direct address a15 through a0 and the indirect address ra15 through ra0 is set in the control register 220 via the data bus 213 in this case when the address select signal sel is 34 0 34 the direct address a15 through a0 is selected when it is 34 1 34 the indirect address ra15 through ra0 is selected the control register 220 is reset to 34 0 34 upon power on a power supply line vcc line 221 receives a power supply voltage of 5 v in a normal mounting state reference numeral 222 denotes a ground line fig2 shows a logic structure of registers for realizing the indirect access method in this embodiment a select register 301 and a data register 302 are incorporated in the read write control circuit 202 shown in fig1 in fig1 the data register 302.