for example if samples passed by element 12 are not bit shifted and samples passed by element 14 are shifted four bit positions and complemented the coefficient value is 1 1 16 or 15 16 the samples output from shifters 12 and 14 are applied to first and second input ports of adder 16 which provides the weighted output samples at output port 18 for simplicity of illustration consider the tap coefficients as being numbers from zero to one though negative coefficients and coefficients greater than one are realizable the shift and add type of multiplier or weighting circuit produces tap weights of binary coefficients the tap weights t may be represented by the equation equ1 where the a i equal zero or 1 and the number n is the maximum number of bit shifts permitted in the particular application for the shift and add circuit of fig2 only two at most of the a i are permitted to equal 1 note however that if the fig2 circuit is augmented with additional shift circuits which apply additional shifted samples to adder 16 then for each additional shifter one more of the a i coefficients may equal 1 consider the circuit of fig2 where at most two a i factors are equal to one and assume for illustration that the number n is equal to 5 the sample values from each of the shifter circuits 12 and 14 may therefore be weighted by the factors 0 1 1 2 1 4 1 8 1 16 and 1 32.