at least one recess in the semiconductor wafer the recess extending from the main surface of the wafer and having a shape factor greater than five the recess including a side surface forming at least one dielectric layer in the recess including two treatments in a controlled pressure reactor one of said the treatments including the chemical vapor deposition at sub atmospheric pressure of a dielectric onto the side surface of the recess the chemical deposition being carried out at a temperature lower than 400 u00b0 c and at a pressure greater than 100 torr in the reactor and another of the treatments including the plasma enhanced chemical vapor deposition of a dielectric onto the side surface of the recess the chemical deposition being carried out at a pressure of less than 20 torr in the reactor and filling the recess with a conductive material thus forming a via application_number US 201314382731 A description the drawings and descriptions below mainly contain elements of definite nature they can therefore not only be used to give a better understanding of the invention but can also contribute to the definition thereof when necessary the invention is not limited to the examples of method and apparatus described herein given solely as examples but encompasses all variants which could be envisaged by the person skilled in the art within the scope of the claims hereof 3d integration in cmos technologies offers prospects of reducing the sizes of transistors and of reaching performance in terms of reduced propagation delay and limited energy consumption the use of through silicon vias tsvs in a substrate with these 3d technologies allows high density stacking of chips whilst continuing to have contacts with.