the assertion reference which signals in the design by parsing the assertion and mapping each reference in the assertion to the point in the design to which it refers then the signal in the design database is marked with the attribute indicating that there is an assertion that refers to this signal when the output design is created those signals marked with the attribute that an assertion refers to this signal should the signal otherwise be needed in the output design it is emitted with its original name if the signal exists in the output design albeit broken into many parts the system might add to the adaptor code which would create a the original signal from these constituent parts the following is an example output model code created from the above input model code the model translation system 106 of fig1 when it produced the above output model code also inserted an equivalent psl assertion again introduced by the comment syntax u201c psl u201d the assertion is modified from the original as the synthesizer understood that the original assert which said that the signal enable must change from true to false on the next cycle after the signal becomes true and be expressed by asserting that the signal enable must be false whenever the state machine enters state s 1 this is the case because the state machine goes to state s 0 whenever the.