fully described by way of an embodiment mode and embodiments with reference to the accompanying drawings it is to be understood that various changes and modifications will be apparent to those skilled in the art therefore unless such changes and modifications depart from the scope of the invention hereinafter defined they should be constructed as being included therein a layout of a transistor according to the invention is illustrated in comparison with a layout of a conventional transistor fig1 and fig2 show a typical layout of a transistor according to the invention and a typical layout of a conventional transistor respectively in a transistor shown in fig2 four contacts 201 and a gate electrode 203 are arranged on an active region 202 a region 204 including a margin for a contact is assumed to be a circle having a diameter of r which is denoted by a dotted line in the layout of a conventional transistor as shown in fig2 the regions 204 each including a margin for a contact are arranged to be a tetragonal lattice when the size of a gate electrode is not considered in that case the area of the active region 202 is approximately 2r u00d7 2r l in a.