the timer output with a time after which full preheating is needed and if the timer output is less a transition from preheat mode to ignition ramp mode can be made immediately rather than waiting for the voltage on the cph pin to reach 4 0 volts as in fig2 in general other components in fig3 can be understood from the figure itself or from the description of their counterparts in the 39 623 patent when the non op signal from ballast lamp control and half bridge driver circuitry 60 is high pfc circuitry 130 is generally disabled so that the pfc control circuitry does not operate during fault mode and under voltage lockout mode when the non op signal goes low at the beginning of preheat mode circuitry 130 is generally enabled and begins to boost voltage by providing signals through the pfc pin in a manner that can be understood from the 39 614 patent because circuitry 130 has been enabled however the preheat mode begins with the dc bus at a non operating voltage that is lower than the voltage at which the lamp ignites the signals through the pfc pin bring the dc bus voltage to its nominal running level only after the first few initial switching cycles of the half bridge driver section during the initial half bridge switching the voltage appearing across the capacitance in the load.