when the solenoid 44 is energized the inverter ua1 input goes low and its output goes high the output of ua1 is connected to a second inverter ua2 when the solenoid 44 energizes the output of ua2 goes low and triggers the stop delay timer u4 through c9 and starts the timeout process the stop delay timer 75 in this design uses a 555 556 type ic analog timer u4 other types of timers including digital timers may be used timer u4 produces a positive going output during the timeout period of which the negative going trailing edge can trigger a second timer stop timer 77 the delay period of u4 is established by c10 and a combination of resistance of r19 r20 r21 and r22 and the setting of dip switches s1 s2 and s3 with a 10 mf capacitor for c10 and three dip switches with resistors proportioned binarily and a 0 75 mw resistor r19 always in the circuit one can achieve nominal delays of 8 25 41 58 74 91 107 and 126 seconds of delay one minute has been found to be a practical time in actual usage if the load is connected again before timeout is complete the output of ua1 goes low again and is coupled to the reset bus of u4 and u5 through c18 to abort the timing sequence it should be noted that the common power lead of the.