t fly without guidance for any longer than 0 5 seconds the null present enable and the time out override are gated together with a nand gate 34 such that whichever signal disables first takes precedence and signals the end of the event the null present logical and time out signal is routed to a d flip flop 53 where it is synchronized to a clock 54 outputs from the d flip flop 53 true and complement of the signal null present logical and time out are directed to respective inputs of two three input nand gates 55 and 56 these two nand gates 55 and 56 provide the clocking signals to a 4 bit up down counter 57 depending on the status of the system outputs from counter 57 drive the 4 most significant bits of a multiplying digital to analog converter 58 mdac which is configured as a digitally controlled analog attenuator the counter 57 outputs are also directed to the inputs of a four input nand gate 61 and a set of logical inverters 62 63 64 and 65 output from nand gate 61 indicates when the counter has reached a count of 15 or all four outputs are high this logical signal is fed to the input of nand gate 56 which disables the count up clock signal directed to counter 57 the outputs from the inverters 62 63 64 and 65 are routed to a four input nand gate 66 and its output indicates when counter 57 has reached zero all outputs low this signals the nand gate 66 to disable the count down clock signal to the counter.