circuitry 104 and especially the nonlinear operation of amplifier 110 on the digital predistorted input signal introduces offsetting memory based and memoryless distortion resulting in a substantially linear analog output signal at system output 112 the memoryless dpd circuit block 116 may be implemented using various techniques including a lut based circuit block as noted above for example a lut based dpd implementation suitable for circuit block 116 is disclosed in u s patent application ser no 10 818 547 filed apr 5 2004 the disclosure of which is incorporated herein by reference in its entirety more generally memoryless dpd circuit block 116 may be implemented using conventional dpd circuits and still provide acceptable memoryless distortion correction due to the more tractable nature of such distortion such known memoryless dpd circuit implementations for dpd circuit block 116 will not be described in more detail since a variety of different known implementations may be employed as will be appreciated by those skilled in the art next the preferred embodiments of memory dpd circuit block 118 will be described the preferred methods of correcting power amplifier memory effects implemented by memory dpd circuit block 118 involve altering a memoryless model based on a taylor series expansion two embodiments are illustrated in detail that model and correct the frequency dependent behavior associated with the memory of the power amplifier the first embodiment described in detail below in relation to fig5 and 6 transforms even order nonlinear sub signals into a joint time frequency representation the transformed even order sub signals are then used to re modulate the input signal producing the desired odd.