to 2 ghz by reducing to 2 or 3 taps the lower end of the range may be no less than 500 mhz as in a conventional fir filter the input d i is delayed in successive delay elements 28 however rather than weighting the individual delayed signals and summing the weighted signals to obtain the desired output the delayed signals are applied to a 5 to 32 decoder 32 one of the 32 output bits from the decoder 32 is high with any input state and that high bit addresses a 4 bit word from the 32 u00d7 4 random access memory 34 the memory 34 is shown to be random access in order to allow for reprogramming of the equalization using a training process below however the system may be a fixed design which can be implemented using a read only memory the 4 bit output from ram 34 defines one of the 15 output levels generated by a digital to analog converter 36 and applied to the transmission line 38 those levels include 0 seven positive levels where dout u2212 is pulled low and seven negative levels where dout is pulled low to simplify the implementation each fir filter is approximated by a transition filter implemented with a look up table as illustrated in fig9 the.