100 in accordance with one embodiment of the present invention idct processor 100 includes a prescaler 102 a multiplexer 104 a matrix multiplier 106 a final scaling rounding stage 108 a block buffer 110 an intermediate scaling rounding stage 112 and a transpose buffer 114 generally speaking prescaler 102 performs the prescaling operation of equation 7 while matrix multiplier 106 performs the matrix multiplication of equations 8 and 9 fig2 is a flowchart describing the steps of efficiently obtaining the 2 d idct in accordance with one embodiment of the present invention the flowchart is herein described with reference to an 8 u00d7 8 input matrix of dct coefficients but other dimensions would be readily achievable in accordance with the invention at step 202 prescaler 102 multiplies each dct coefficient in the input matrix by the prescaling coefficient from equation 7 that corresponds to its position in the matrix referring again to fig1 the properly scaled and rounded prescaled dct coefficients are one input to multiplexer 104 the remainder of the computation follows a two pass method wherein matrix multiplier 106 is essentially applied to the prescaled dct coefficient data twice first at step 204 multiplexer 104 directs the prescaled dct coefficient data to an input of matrix multiplier 106 at step 206 multiplier accumulator 106 individually multiplies each row of the prescaled dct coefficient matrix.