is used to block the high energy implantation and a 3 1 spacer scheme is used to optimize the source drain doping profile with this approach the dose implanted into the thin poly si gate can be increased while the deep source drain implantation can be optimized without worrying about the penetration problem application_number US 42005306 A description the present invention which provides a technique for providing an increased dopant dose to a thin poly si gate while optimizing the dose within the deep source drain regions as well as the resultant cmos structure that is formed by the same will now be described in greater detail by referring to the following discussion and drawings that accompany the present application it is noted that the drawings of the present application are provided for illustrative purposes and as such they are not necessarily drawn to scale in the description and drawings that follow a preferred embodiment of the present invention is described and illustrated in which at least one nfet and at least one pfet are formed onto a surface of a semiconductor substrate although such description and illustration are made the present invention is not limited to forming such a cmos structure instead the present invention can be used in forming a cmos structure including at least one pfet or at least one nfet on a surface of the substrate reference is made to fig1 a 1f which illustrate the basic processing steps of a first embodiment of the present invention that are used in forming a cmos structure including at least one nfet and.