address thus sent from the selector 82 in accordance with a signal 34 xsp 34 indicating the start of access to the memory 62 the selector 85 selects the address held in the ff 85 when the data corresponding to the access address are not held in the latch 71 or when a single access to the memory is needed the selector 85 then selects if necessary an address sent from the incrementer 84 the address being subsequent to the access address and outputs it as an address 34 vadr 34 requesting access to the memory 62 fig9 shows each specific circuit of the address latch unit 53 the validity judging unit 54 and the match judging unit 55 provided in the hit detection unit 52 in fig9 the address latch unit 53 which is provided with an and gate 91 a selector 92 and ffs 93 holds an address for the data held by the data storage unit 45 the and gate 91 detects a timing for starting to write data to the data storage unit 45 and for starting to read data from the memory 62 the selector 92 selects an address 34 vadr 34 requesting read access to the memory 62 in the timing detected by the and gate 91.