62 the different electrical connectors 60 are identified in fig1 as electrical connectors 60 0 through 60 7 with the left most being 60 0 the locations for the electrical connectors 60 for contact with the corresponding electrical conductors 24 are labeled 0 through 7 in the figures the position labeled gc identifies the location of ground connector 64 which typically electrically contacts electrical conductors 24 at each level while only one electrical connector 60 is shown to contact an electrical conductor 24 at each level in practice many different electrical connectors 60 would be used to contact electrical conductors 24 at the same level during wafer scale operations the same basic processing steps are used on a third 3 d stacked wafer 56 1 to create an array of stacked multichip modules 61 fig9 shows the structure of fig8 after creating an initial processing photoresist mask 57 on dielectric material 54 followed by etching through dielectric material 54 down to hard mask layer 30 this creates openings 58 aligned with ground conductor location gc and electrical conductor locations 0 7 a first photoresist mask 66 shown in fig1 is created on the structure of fig9 except for openings 58 at electrical.