conducted at an angle of preferably from about 15 to 75 u00b0 and more preferably from about 30 to 60 u00b0 pocket implants 24 25 is also formed within substrate 10 to a depth of preferably from about 200 to 400 u00e5 and more preferably from about 250 to 350 u00e5 pocket implants 24 25 are preferably p pocket implants for nmos and are formed to prevent device punch through self aligned trench 26 28 etch and first rapid thermal anneal u2014 fig3 as shown in fig3 self aligned trenches 26 28 are etched into substrate 10 ldds 20 22 stis adjacent gate structure 18 and stis 12 14 this etching process also thins gate structure 18 and stis 12 14 to form thinned gate structure 18 u2032 having a thickness of preferably from about 800 to 2800 u00e5 and more preferably from about 1300 to 2300 u00e5 and etched stis 12 u2032 14 u2032 trenches 26 28 are recessed as at 30 by preferably from about 50 to 200 u00e5 and more preferably from about 70 to 130 u00e5 beneath gox 16 this leaves remaining ldds 20 u2032 22 u2032 as shown in fig3 an optional first rapid thermal anneal rta may then be performed either before or after formation of self aligned trenches 26 28 at a temperature of preferably from about 800 to 1000 u00b0 c and more preferably from about 850 to 950 u00b0 c for preferably about 3 seconds and more preferably about 2 seconds formation of liner teos structures 32 34 u2014 fig4 as shown in fig4 a layer of teos is formed over the structure of fig4 and is then etched back to form liner teos structures 32 34 over the exposed.