of hierarchy schematic and layout representations are reduced to a common form in terms of placements instantiations of lower level matched blocks and devices these two representations are then compared in terms of blocks and devices the process is better illustrated with reference to the flowchart depicted in fig4 a and 4b at step 600 a hierarchical net list is extracted from the schematic design and at step 610 a hierarchical net list is extracted from the layout design the hierarchical net list contains a listing of the blocks and devices which comprise the circuit and the blocks and devices instantiated within each block at step 615 the various hierarchical elements are sorted in order of hierarchical levels starting with the highest order first the net lists may be sorted by examining the components within each block and sorting the block containing instantiations of other blocks to be at a higher hierarchical level than the instantiated blocks similarly each block may be identified by a hierarchical level identifier for quick sorting or pre sorted in hierarchical order at step 620 starting with the lowest level the block name in the schematic net list is compared to the block names in the layout net list if there is no match then that block is marked for flattening i e all instantiations of the block would be flattened in terms of its components devices and lower level blocks for verification a list of blocks for which block names in schematic and layout net list are same is formed and sorted in order of hierarchical levels starting from the lowest and block level set 635.