nb is connected to the clock signal the pulse circuit signal is provided at the drain of transistor na the source of transistor na is connected to the drain of transistor nb to form a stack of n channel transistors the source of transistor nb is connected to a pull down voltage source such as ground the pulse circuit signal is connected to an output inverter 300 to provide the variable width pulse generator signal the output inverter 300 may be for example a static complementary metal oxide semiconductor cmos inverter a dynamic inverter a reset assist inverter or the like the pulse circuit 100 also includes two p channel transistors pa and pb the sources of both transistors pa and pb are connected to a pull up voltage source 15 which may be for example 1 8 or 2 5 volts the drains of both transistors pa and pb are connected to the pulse circuit signal an inverter 14 is connected between the pulse circuit signal and the gate of transistor pb two inverters 210 200 are connected in series between the pulse circuit signal and the gate of transistor pa the output of inverter 200 is the u201c reset u201d signal of the pulse circuit 100 as explained in detail below these two inverters 210 200 form a variable delay reset loop path that automatically resets the pulse generator 100 a control signal c is input to one of the inverters 200 in the reset loop path to control the width w of each pulse produced by the output invertor 300 the operation of the.