of the selection signal line s 1 is high the series of the memory cells mc 1 mc 2 are selected and are connected to the bit line bl on the other hand when the voltage of the selection signal line s 2 is high the series of the memory cells mc 1 39 mc 2 39 are selected and are connected to the bit line bl the number of the series of memory cells connected to the bit line bl can be changed as occasion demands particularly if the number of the series of memory cells connected to the bit line bl is 1 the selection transistors are unnecessary as the series of memory cells are connected directly to the bit line bl a method for manufacturing the nand type rom device of fig1 is explained next with reference to fig2 a through 2e first referring to fig2 a a p type monocrystalline silicon substrate 1 is thermally oxidized to form a thin gate silicon oxide layer 2 then gate electrodes 3 made of polycrystalline silicon including phosphorus are formed by using a chemical vapor deposition cvd process and a photolithography process next arsenic ions are doped into the silicon substrate 1 with a mask of the gate electrodes 3 to form n type impurity regions 4 within the silicon substrate 1 next referring to fig2 b a photoresist pattern 5 is formed by using a photolithography process and phosphorous ions are doped into the silicon substrate 1 with a mask of the photoresist pattern 5 thus completing a data write operation to.