the rising edge the p type pulse generator 1212 is triggered to generate a pulse signal v pp going up from the voltage v ss to the voltage v bp with the predetermined period t p this pulse causes that the voltage sharing gate driving signal v psgd goes down from the voltage v bp to the voltage v ss and the transmitting gate driving signal v pgd simultaneously goes down to the voltage v ss so that the transmitting transistor q p is turned on more completely in this way more currents flow from the voltage source v dd to the output end o of the buffer 1000 through the voltage sharing transistor q ps increasing the speed of charging the capacitor c out for instance it can be seen that in the output signal v out of fig2 the rising speed of the first rising edge of the output signal v out is faster than the rising speed of the output signal of a conventional buffer shown by the dot line because of the p type pulse signal when the input signal v in changes from logic u201c 1 u201d into logic u201c 0 u201d the falling edge the n type pulse generator 1222 is triggered to generate a pulse signal v np going down from the voltage v dd to the voltage v bn with the predetermined period t p this pulse causes that the voltage sharing gate driving signal v nsgd goes up from the voltage v bn to the voltage v dd and the transmitting gate driving signal v ngd simultaneously goes up to the voltage v dd so that the transmitting.