lower event rates in a conventional tester when a pin requires a higher event rate and thus more tgs considerable hardware expense is incurred should a pin actually require a lower event rate then the excess tgs allocated to the pin represent hardware expense that is wasted the advantages of connecting tgs to pins via a reconfigurable allocator circuit includes reducing the hardware cost required to achieve the required per pin event rate fig9 illustrates the concept of an inexpensive high performance tester the tester sketched in fig9 is manufacturable with today 39 s technologies at a significantly lower cost than that of a similar performance conventional tester tgpeb timing generator pin electronics board cf fig9 fig1 and fig1 future increases in bicmos asic integration densities will make it possible to migrate the simd array cage containing the tgs shown in fig9 into the test head containing the pes while migrating the pes into the reconfigurable allocator circuits the integrated tgpeb is shown in fig1 the resulting tester sketched in fig1 would allow further manufacturing cost reduction extrapolating conservatively from the empirical results presented in my prior publications and disclosures regarding the performance to cost ratio increase afforded by i cache enhancement i expect the various aspects of this invention combined in a variety of parametric instantiations to decrease by at least one third and at most three quarters the materials assembly and installation cost of a tester made using current and foreseeable vlsi and system implementation techniques and meeting a given event rate and timing accuracy performance requirement although there have been described hereinabove various specific arrangements of a star i.