balancing the controller 112 comprises a central processing unit cpu 122 support circuits 124 and memory 126 the cpu 122 may be a form of processor microprocessor microcontroller including an application specific integrated circuit asic the support circuits 124 comprise well known circuits that support the functionality of the cpu 122 including power supplies clock circuits bus circuits interface circuits and the like the memory 126 comprises random access memory read only memory and combinations thereof the memory 126 stores the control software 128 that is executed by the cpu 122 to control the operation of the interleaved flyback circuits 106 and 108 to facilitate digital control the signals from the sensors 114 116 118 and 120 are converted from analog signals to digital signals using analog to digital conversions adc that may stand alone or be part of the controller 112 in operation the controller 112 processes the sensor signals to derive timing signals for the switches q1 and q2 to achieve timing synchronization and load balancing for the interleaved flyback circuits 106 and 108 the use of interleaved flyback circuits reduces ripple current in the output power doubles the ripple frequency to facilitate simplified filtering to remove the ripple and doubles the output power of the converter interleaving functions best when the activation and deactivation cycles of each flyback circuit are exactly 180 degrees out of phase for embodiments of the present invention to achieve automatic balancing and timing accuracy the conversion frequency of the converter must be dependent upon the current i.