as shown the transmitter does not include circuits for block encoding and the modulation is binary the outputs of device 36 are applied directly for one of the subchannels and through a separate register 38 for the other subchannels to respective modulators 16 which each receive carriers at frequencies f1 f2 f3 or f4 the type of modulation is advantageously such that the demodulators of the receiver may be simple for example of the envelope detection or differential type however any amplitude phase or frequency modulation may be used the receiver fig6 includes downstream of conventional input amplification and filtering stages not shown symmetrical with those of the transmitter as shown each subchannel includes a demodulator 22 delivering a sample at successive times separated by equ1 with d useful linear flow rate generally that part of the receiver situated downstream of the demodulator is digital and each subchannel then includes an a d converter 24 delivering for example the sample coded as a three bits word to the time de interlacing circuit 26 this circuit is formed of three shift registers 42 causing delays complementary to those applied to the corresponding subchannels upon transmission in this particular interlacing case registers 42 automatically operate in synchronism due to the parallel transmission the frequency de interlacing circuit 40 consists of a wired array for simultaneously delivering samples representative of the message coded by the convolutive encoder but affected by noise on four parallel outputs the samples coded as three bits words are applied to the metric computing unit 28 provided for calculating twice.