sufficient stages 340 and 350 are each suitable for high speed switching when the control signal driving capacity is small resulting in a large delay time for directly driving the nand gates of the data input stage 310 the control signal is passed through a non inverting buffer between the enable disable control gates and the data input stage gates so that the operating delay time is decreased such non inverting buffers can be added to enable disable control stages 340 350 and the resulting circuits provide operation similar to that of enable disable control stages 340 350 thus enable disable control stage 360 is composed of two and gates 361 362 and two non inverting buffers 363 364 when the enable disable control signal is a logical 34 0 34 stage 360 outputs a logical disabling signal likewise enable disable control stage 370 is composed of two nor gates 371 372 and two non inverting buffers 373 374 so that when the enable disable control signal is a logical 34 1 34 stage 370 outputs a logical 34 0 34 disable signal enable disable control stage 380 also operates without inverting the control signals thus enable disable control stage 380 is formed of two two input nand gates 381 382 the outputs of which pass through inverters 383 384 to operate similar to the outputs from enable disable control stage 350 stage 390 is formed of two two input or gates 391 392 the outputs of which pass through inverters 393 394 and operate similar to enable disable control stage 340 as with enable disable control stages 360 370 the multiplexer speed characteristics.