ground are u2018 off u2019 if either side of any 6t cell connected to the associated lbls is pulled to u2018 0 u2019 the corresponding nand output goes to u2018 1 u2019 and pulls the respective global bit line to u2018 0 u2019 while the other symmetrical side stays at u2018 1 u2019 giving a double ended sensing circuit speed is obtained via the extra drive provided by the nand gates obviously area comparisons for the different approaches require detailed layouts a simple indication of the relative areas can be determined from the number of added devices for each approach compared to the 6t sram since in the hierarchical bit line approach the basic building block is 16 cells per local bit line the number of added devices per 16 cells was used for the comparison fig4 illustrates that the hierarchical bit line 6t sram approach has an additional 6 devices for every 16 cells compared to the 6t sram the 6thb_nand approach has an additional 9 devices for every 16 cells the numbers of added devices for the 7t and 8t approaches are 17 and 32 respectively also illustrated in fig4 are the number of additional bit lines and word lines.