22 the transfer finishing signal 134 is outputted when the access to data of one sector is finished the timing signal 135 is generated from the control signal 22 when the host computer 2 reads or writes the sector data a status register 139 stores data indicating the state of the memory control unit 1 when the interrupt signal 131 is outputted and when the transfer finishing signal 134 is outputted the status register 139 is set to the busy state also the status register 139 is set to the ready state by the microprocessor 8 when the status register 139 is in the busy state the host computer does not read and write the sector data fig3 is a block diagram showing configuration of the data changing means 11 a data selection setting register 115 is a storage means set by the microprocessor 8 using for example a signal along a signal line 18 where information to select the data to be outputted to the ecc bus 113 and the internal data bus 114 from the first memory bus 111 or the second memory bus 112 is set a read data selecting circuit 116 selects data to be outputted to the internal data bus 114 from the first memory bus 111 or the second memory bus 112 according to a content of the.