or data bus 106 using gates 184 and 186 for transfer to port iod 0 31 for output additionally inputs into port iod 0 31 may also be processed by the crc system 100 and return to port iod 0 31 for output similarly inputs to ports he 0 31 and pp 0 31 may be processed internally in crc system 100 and returned to ports he 0 31 and pp 0 31 therefore the architecture of crc system 100 is programmable and flexible to handle different protocols and data processing operations data flow control through crc system 100 is performed via control 190 by using inputs through gates 181 189 crc enable 192 input enable 196 dout latch enable 197 and status enable 194 control 190 also receives error signal 198 for processing error correction information provided by crc generator 130 edit buffer 160 and compare 170 the improved architecture of the present invention provides flexibility in data flow and data processing which can be demonstrated by a number of processing modes in a first mode of operation crc system 100 receives parallel data from ports c 0 7 he 0 31 and pp 0 31 by enabling gates.