
{"publication_number": "US-6077305-A", "abstract": "a system and method are provided for selectively inferring latch elements in a circuit design from an event - driven hardware description language file to an event - independent format . the method includes modeling the file as a plurality of data flow equations , analyzing the plurality of equations for uninitialized variables , and placing a latch at any utilized , uninitialized variable . control signal information for an inferred latch is also derived during the data flow analysis .", "application_number": "US-21564598-A", "description": "referring first to fig1 data flow analysis provides a perspective on circuit design necessary for the latch inference method and system of the present invention . data flow analysis is a set of techniques for collecting information regarding how data values are modified and accessed across basic circuit blocks ( wherein a basic block is a linear sequence of simple statements free of pauses and branches except at the end ). data flow information is collected by setting up and solving a system of data - flow equations of the form shown in fig1 which can be read as , &# 34 ; the information available at the end of a statement s ( out [ s ]) equals the information generated in s ( gen [ s ]) plus the information available at the beginning of s ( in [ s ]) excluding the information killed in s ( kill [ s ]).&# 34 ; referring next to fig2 we find an example of data flow analysis leading to latch inference . we assume that out [ s 1 ]={ a , b , c 