timer 13 is triggered by a rising pulse edge and timer 14 is triggered by a falling pulse edge the two timers control a bistable flipflop built from two nand circuits 15 and 16 the timer 13 serves to define a deadtime for the circuit while the timer 14 serves to define the integration time which is a little less than the deadtime to account for the resetting time of the integrators in the quiescent state the output signal from nand circuit 15 is equal to 0 as well as the signal on line 10 is equal to 0 so that the switches 6 are held closed by line 11 the integrators 4 and 5 fig4 are held reset to zero the one input of nand circuit 17 is held at zero via the resistor 18 which is why its output signal is 1 accordingly the nand circuit 19 receives the signals 0 from nand circuit 15 and 1 from nand circuit 17 and therefore it passes logic 1 to switch 7 via line 12 the summator 5 is coupled off the capacitor c 1 in fig4 the timer 13 is in its quiescent state to that its output signal q is logic 1 in this text underlines are used instead of overbars as in the drawing and the nand circuit 20 passes logic 1 to the nand circuit 15 as one of its inputs is on 0 from line 10 the nand circuit 16 receives a 0 from the output q of timer 14 which is in its quiescent state and therefore passes a logic 1 to the other input of nand 15 the control circuit is started by a short control pulse on line 10.