bus converter 722 preferably converts addresses between an arm u2122 axi bus and a vbusm the arm u2122 axi has separate channels for read and write transactions bus bridge 621 merges the axi read and write channels onto the single vbusm r w command channel via bus converter 722 this merge introduces a possibility that coherent reads can block a following memory update writeback if the coherent read triggered a snoop of other processing cores the memory update writes that do not trigger snoops are writeback and writeclean the coherent writes that may trigger snoops are writeunique and writelineunique a snoop filter in the interconnect allows snooping to be done only when necessary by tracking cache line ownership by all coherent masters without a snoop filter a basic interconnect must snoop all coherent masters for every coherent transaction this can be inefficient in the invention multi core shared memory controller 700 includes this snoop filter as a part of overall coherency support the converted read and write addresses as well as the read data write data snoop response snoop data and snoop address pass between clock domains via asynchronous crossing 723 configuration registers 724 are readable and writeable by core with cache 611 via respective read address 701 read data 703 and write address 702.