rectifier circuit with a level preset by a potentiometer 120 and produces an output voltage corresponding to the difference between the rectifier output level and the preset level when switched in circuit by an fet switch in the chip u1 the agc output is connected to a vco chip u2 fig2 b to control the pulse duty cycle of the output signal from the chip u2 to prevent a negative swing which could damage the oscillator chip u2 a diode 122 clamps the output to a minimum of 0 6 volts a scan comparator corresponding to the comparator 24 in fig1 is shown in fig2 b as amplifier 128 one input of amplifier 128 is coupled to the output of rectifier amplifier 106 and the other amplifier input receives a signal of about 90 of the output buffer amplifier 11o fig2 a through resistors 130 132 when the rectifier signal exceeds 90 of the level on the peak detector the output of the comparator 128 goes to a logic 1 corresponding to a match signal having the designation cmp scanning logic corresponding to the blocks 28 30 32 and 34 in fig1 is shown in fig2 c as a system clock comprised of inverting amplifiers 134 136 connected in a resistor capacitor.