a logic 34 lo 34 during the timing cycle once the timing cycle is completed and the output of the delay timer goes 34 low 34 when the corresponding positive going pulse on the output of the inverter ic 3b goes 34 hi 34 it clocks the d flip flop ic 5a this positive going clock pulse passes the input on a data line to the q output referenced as q in fig4 if the data line to the d flip flop ic 5a is at a logic 34 hi 34 at the end of the timing cycle indicating a malfunctioning system condition this 34 hi 34 is passed to the q output triggering a silicon controlled rectifier scr1 into conduction it should be mentioned that the dual d flip flop ic 5 has two separate d flip flop circuits on the chip since only one is used i had referenced it as ic 5a ic 5b is not shown nor is it utilized ic 5 would have comprised both ic 5a and ic 5b once the scr1 is triggered it allows current to flow through the audio piezo alarm 22 pz1 on fig4 and the service visual alarm 20 led3 on fig4 both the audible alarm pz1 and the visual alarm led3 alarms 22 and 20 respectively will be active until the reset button sw1 14 in fig4 is depressed breaking the current flow through scr1 and resetting the entire sensing and logic circuits if at the end of the fifteen 15 minute delay the system has.