is roughly three eighths of a one frame collection of valid video segments mapping 210 shows an additional feature that can be used to reduce buffer size in both an encoding system and in a decoding system according to the invention the block arrangement has been modified such that the order in which qvga superblocks are used in synthesizing a 525 60 frame correlates roughly with the raster order of the synthesized 525 60 frame this is best visualized by viewing fig1 in conjunction with fig1 fig1 shows a tiling diagram 220 divided into five sets of four qvga superblocks each sets 222 224 226 228 and 230 these superblocks are grouped according to a u201c superblock raster order u201d i e superblocks are grouped in rows according to a left to right top to bottom ordering superblock set 222 is mapped such that it occupies the first four valid qvga superblock mapping positions in mapping 210 i e either the four u201c a u201d positions or the four u201c b u201d positions shown in the first two superblock rows of fig1 depending on whether the frame is even or odd with this mapping two effects are achieved all superblocks in the top fifth of a qvga frame are used within the first fifth of a frame time as input to the encoder thus latency at the input buffer can be reduced from one frame to one fifth of a frame and buffer size.