fig1 an additional circuit 39 allows remote control of the magnitude of the scan b voltage the additional circuit 39 includes a memory mem illustrated as a block 40 together with a digital to analog converter dac for producing a signal b align signal b align is applied to the base of a transistor q 108 by way of a temperature compensating diode cr 112 and a voltage divider including resistors r 127 r 128 and r 129 transistor q 108 has its emitter coupled by a resistor r 130 so it produces a collector current which is linearly responsive to the magnitude of b align and produces an additional offset of the feedback signal at tap point 22 1 of voltage divider 22 which can be used to perform fine adjustment of the scan b voltage the memory 40 is active during all the horizontal frequency modes but accesses different memory locations under the control of regb _sw the memory locations are preprogrammed with values which compensate for tolerances an advantage of this arrangement is that the coarse adjustment of the feedback ratio is provided by resistor r 120 and the combination of memory 40 and dac 42 can be used over its full dynamic range for trimming the scan b voltage the error signal produced by u 103 by comparing the feedback scan b signal from tap 22 1 of voltage divider 22 of fig1 is applied by way of error signal input port 32 5 of fig2 to input terminal.