currently in use but wreqd is asserted meaning that write data is waiting for the data bus this write data goes first on the data bus but the read response data immediately follows in both of the cases 210 212 the data bus is available for the waiting read response when ds makes a transition from the asserted state to the dis asserted state which indicates that the one prior transaction is complete this transition is indicated at 231 in fig8 the timing of the signals for the case 210 is illustrated in fig1 in connection with fig8 in fig1 a processor i with a response at the head of the read response queue asserts rspreqd 204 and samples ds and wreqd 206 the signal wreqd is asserted and ds is dis asserted as indicated above this means that there is no valid data for the data bus in the next clock cycle i e after the data 250 the data bus is unoccupied for the next clock cycle 251 it is now the turn of the waiting write data to gain access to the data bus thus the signal wreqd is dis asserted 253 the write command is issued on the command bus 254 and the command bus is released recall a write command holds the command bus until the write data is.