rp 206 b 2 rp 207 b 3 rp 208 increments at one value of the two bit combination q1q0 for example the incrementing of the two bit bank u201c 0 u201d read pointer b 0 rp 205 is triggered by a signal from u201c pls u201d generator when q1q0 u201c 01 u201d that of the bank u201c 1 u201d read pointer b 1 rp 206 at q1q0 u201c 10 u201d bank u201c 2 u201d read pointer b 2 rp 207 at q1q0 u201c 11 u201d and bank u201c 3 u201d read pointer b 3 rp 208 at q1q0 u201c 00 u201d the flip flop output u201c f u201d is the q0 output shown in fig4 a and is controlled by the trdylrdy signal u201c f u201d or u201c q0 u201d is high whenever any of the and gates triggers a pls generator to supply a signal to its associated bank read pointer 205 206 207 208 to increment when the decoder is also enabled to supply its output the flip flop output u201c f u201d is part of external circuitry connected to the fifo a two bit bank read pointer selects through mux 4 212 mux 3 210 mux 2 211 mux 1 209 which register of each bank is to be read bank 0 read pointer b.