binary counter 406 and the set input to ring counter 408 with flip flop 417 in the reset state the clock enable inputs of binary counter 406 and binary counter 407 are enabled all counters commence counting in response to their clock input signals counters 406 409 count at a nominal frequency of 64 khz binary counter 406 and ting counter 408 are clocked by the signal from divider 103 received via conductor 123 and binary counter 407 and ring counter 409 are clocked by reference signal 121 received via conductor 131 and gates 412 413 and 414 compare the stages of ring counters 408 and 409 an and gate outputs a 34 1 34 if both of its corresponding stages in ring counters 408 and 409 are at a 34 1 34 state after some period of time if a frequency difference exists between dtcxo 104 and reference signal 121 ring counter 408 and ring counter 409 will be simultaneously in the 34 1 34 state in all stages together when this occurs and gates 412 414 transmit 1s 34 to and gate 415 which transmits a 34 1 34 via conductor 439 to flip flop 417 the 34 1 34 on conductor 439 is synchronously clocked into flip flop 417 and sets that flip flop on the.