gate bias does not address the avalanche current component thus a different solution had to be found for nldmos arrays to address avalanche current breakdown the present invention adopts a novel current balancing structure on the drain side of the devices in particular the present invention makes use of additional in depth sub collector implants this is best understood by considering a prior nldmos device fig3 shows a cross section through a prior art nldmos device which includes an n drain 300 with drain contact 302 a gate 304 with gate contact 306 and a source 308 with source contact 310 in addition the nldmos device includes a base 312 with base contact 314 one embodiment of the present invention is shown in fig4 and provides for an n type deep implant in the form of an n sinker 410 which in this embodiment extends vertically between the drain region 400 and an n buried layer nbl 412 other than the n type deep implant the nldmos like structure of the present invention is substantially the same as the prior art and includes a drain 400 with drain contact 402 a gate 404 with gate contact 406 and a source 408 with source contact 410 the present nldmos like structure also includes a base 422 with base contact 424 while the embodiment of fig4 had the n sinker 410 extending between drain and nbl in another embodiment the sinker was formed spaced laterally from the drain the effect of including a sinker is shown in fig5 for different sinker mask locations and with no gate source voltage graph 500 shows.