for the maximum possible time i e until v in lt v out summarizing the described invention addresses particularly the case in which the current drawn from the system albeit being lower than the current limit programmed for the specific power source causes the input voltage v in to drop below input threshold voltage v in u2014 low mainly because of the connection cable resistance or the low quality of the power source in this case the control loop presented above insures 1 that the buck converter or in general the system supply regulator is not shut down unlike the prior art scheme of fig1 prior art 2 that the buck current limit is reduced in such a way to bring the voltage at v in node above the v in u2014 low threshold furthermore in the case the power source is plugged out the buck converter of the present invention maximizes the time during which power is delivered to a load since the power path is turned off only when the input voltage falls below the output voltage it has to be understood that the present invention outlined above in regard of an embodiment using a buck converter can be obviously also applied to other kind of voltage regulators as e g to linear voltage regulators or buck converters having different implementations from the one described in the present invention as long as they.