is the read latency bus 35 as shown in fig7 as shown the latency bus 35 comprises four lines rl lt 0 3 gt which indicates the read latency to be used with the device for example if a 1 5 ns clock is to be used requiring a read latency of 10 the signals of the latency bus 35 will represent the number 10 in a binary fashion e g rl lt 3 gt u2018 1 u2019 rl lt 2 gt u2018 0 u2019 rl lt u2018 1 u2019 gt u2018 1 u2019 and rl lt 0 gt u2018 0 u2019 if a 3 0 ns clock is to be used requiring a read latency of 5 the signals of the latency will represent the number 5 in a binary fashion e g rl lt 3 gt u2018 0 u2019 rl lt 2 gt u2018 1 u2019 rl lt 1 gt u2018 0 u2019 and rl lt 0 gt u2018 1 u2019 as disclosed in the examples herein a read latency from 5 to 10 is contemplated although one skilled in the art will realize that other read latencies could be used and therefore that this range of values is merely exemplary in a preferred embodiment.