close together fig7 shows a schematic of one embodiment of a data clock synchronization circuit 60 that that can be used with scan in testing operations scan in or scanning operations involve disabling the circuit from normal operation and scanning in a test data sequence the results of the test sequence are analyzed at various points within the system to evaluate the performance of the circuit the circuit 60 is essentially the same configuration as the circuit shown in fig2 except that it includes an additional multiplexor 62 that is inserted between the flip flop 44 and the latch 45 also an and gate 64 is inserted before the inverted clock input of the latch 45 and a second and gate 66 is inserted in front of the or gate 46 shown in fig2 the additional multiplexor 62 has q as one input and scan u2014 data as the other input scan u2014 data represents the test data sequence for the scanning operation the additional multiplexor 62 is controlled by a scan u2014 enable signal when the scanning sequence is activated by the scan u2014 enable signal the output of the additional multiplexor 62 is scan u2014 data that is input to the latch 45 scan u2014 data passes from the latch as the value of q u2032 and on through the first multiplexor 48 as the value of mux u2014 out fig8 shows a schematic for an alternative embodiment of a data clock synchronization circuit 70 in this embodiment the data d is input to a.