6 to 9 cmos pullup transistor and a ratio of 10 to 1 nmos pulldown transistor the rising edges take a long time to charge the capacitors 128 and 134 and the falling edges would quickly to discharge the capacitors 128 and 134 therefore the signals on node 110 would be as shown in fig3 notice that the output signal shown in fig3 would not have any glitches and that a valid rising edge is passed after a significant delay and a valid falling edge is passed after a short delay it is important that falling edges are passed quickly through the waveshaper because for the scsi reqb and ackb signals it is the falling edges that determine when the data is latched that is the data setup time is measured before the falling edge and the data hold time is measured after the falling edge if the inverter 112 that drives node 110 had been designed for equal rise and fall times then several short high glitches would add up to charge the capacitor as high as a valid rising edge since the circuit 100 provides slow rise times and fast fall times the capacitors 128 and 134 within control circuits 116 and 118 are reinitialized to 0 volts every time a glitch is finished so the circuit treats every glitch the same during the 5 volt operation the capacitor sizes give appropriate delays with the pullup portion of the inverter 112 driving node 110 to adjust for operation in the 3 to 3 6 volt range two p.