via is used to connect the metal line and hence the common clock lines with the vcc line allowing the input pass transistors to be turned on permanently requiring no external control 0054 fig6 shows a circuit diagram of another type of memory cell the memory is similar to the embodiment shown in fig1 except memory cell 400 also has one more transistor 444 connected to ground 170 for resetting the latch 400 the reset transistor 39 s 444 in each latch are controlled by a common global line 460 it should be appreciated that in yet a further type not shown the latch 400 could be set by connecting transistor 444 to the supply vdd 160 0056 fig7 shows the physical template for the memory cell 400 of the second type in which the reset transistor is connected with the ground rail 170 and is controlled by a common global signal 460 0057 fig8 shows the physical template of a 2 u00d7 2 memory cell array of the second type the reset transistors 444 a 444 b in memory cells 400 23 400 22 respectively are connected with the ground rail 470 a using the vias 416 417 respectively also the reset transistors 444 c 444 d in memory cells 400 32 400 33 respectively are connected with the ground rail 470 b using the vias 418 415 respectively in normal working operation of the fpga when the common global signal 460 goes high all of the reset transistors 444 turn on which resets the memory cells 0058 fig9 shows a second embodiment of the present invention for hardening the fpga of the programmable memory cell array using memory cells of the.