the bond pads 3 4 to vertical contact elements 6 7 that are also disposed on the face 2 of the semiconductor die 1 the vertical contact elements 6 7 are constructed as bump shaped elevations which are evenly distributed on the face 2 of the semiconductor die 1 and which are configured in a matrix i e at intersections of mutually orthogonal rows and columns the vertical contact elements on the face 2 include contacts for normal operation 6 and test operations 7 the tracks 5 of the rewiring plane conductively connect the pads 3 which are provided for normal chip operation to the respectively allocated vertical contact elements 6 which are also provided for normal operation the tracks 5 also connect the test pads 4 to respectively allocated vertical contact elements 7 fig1 b represents an enlarged section of one of the vertical contact elements 6 that is provided for normal operation with the actual contact region 8 which is installed on a bump shaped elevation 9 and which is connected to the allocated bond pad 3 via the track 5 fig2 represents a cross section through the enlarged section of the vertical contact element 6 of fig1 b with the bump shaped elevation 9 that is disposed on the face 2 of the semiconductor die 1 the actual contact region 8 covers a portion of the bump shaped elevation 9 namely the top portion like a cap and is conductively connected to the track 5 which is allocated to the contact element 6 accordingly fig1 a 1 b and the cross section according to fig2 represent a view after the singling step of the semiconductor die that is fabricated according to a wafer level packaging technique.