signal within controller 16 to the microprocessor 24 alternatively the output of the throttle block 34 can be used to deny access of the microprocessor 24 to the main system bus 21 thus preventing it from fetching instructions and causing it to halt the throttle block 34 takes two inputs one is mp_enable from the pdc 42 for the power down mode 1 the mp_enable signal is used to completely disable the microprocessor 24 when power down mode 1 is entered the other input to the throttle block 34 is throttle which consists of three values m s and b which determine the proportion of time that the microprocessor 24 is enabled the value of throttle can be changed by the firmware writing to registers within the bus interface and control logic block 30 the values m mark and s space determine the ratio of clock cycles for which the microprocessor 24 is enabled and disabled the b value determines the minimum number of clock cycles in a row the microprocessor 24 will be enabled or disabled for this allows the microprocessor 24 to gain access to the memory 14 for a minimum number of clock cycles since there would be overhead and inefficiencies when enabling and disabling the microprocessor 24 for too few clocks cycles thus the values m s and b indicate that the microprocessor 24 is enabled for m b clock cycles from every m s b clock cycles the hardware interleaves m blocks of cycles with s blocks of cycles in an optimum way to minimize long sequences of cycles with the microprocessor 24 disabled which could reduce the microprocessor 24 responsiveness to events such as interrupts the pattern set by m s and b is as follows.