components 2 3 4 8 9 10 included in the diagram of fig1 are well known to persons skilled in the art it is then useless to describe their structure fig2 is a diagram illustrating an embodiment of the frequency multiplier 7 such a diagram is known per se however its application to the device according to the present invention ensures particular advantages the frequency multiplier of fig2 comprises an oscillator controlled by a frequency division phase interlocking loop it comprises a phase comparator 73 which generates on its output 731 a voltage proportional to the phase difference of the alternate signals applied to the input 71 see fig1 and to the other input 732 a controlled oscillator 74 to the control input 741 of which there is applied the voltage at the output 731 of the comparator 73 and whose output is the output 72 of fig1 a frequency divider 75 arranged to divide the frequency at the output 72 which is connected to its input 751 by a coefficient equal to the desired multiplication coefficient e g 10 m and to apply the divided frequency from its output 752 to the input 732 of the comparator 73 it is known that when the loop comprising the comparator 73 the oscillator 74 and the divider 75 is in an equilibrium state the output frequency of the oscillator 72 is synchronized with the signal applied to the input 71 with negligible phase difference it is also known that the time constant t of such.