will be apparent to those skilled in the field that the instructions listed in table 1704 can be readily translated into a hardware implementation numerous variations of the instruction set are possible including e g removing redundancy in the instruction set adding instructions in the instruction set to avoid initializing the memory or optimizing the instruction set to conform to memory operation characteristics such variations are to be considered within the scope of the invention 0098 fig1 illustrates an encoder 1800 incorporating various features of the present invention encoder 1800 fully vectorizes with rotations encoder 1000 note that the figure indicates z 4 whereas our example has z 3 in general we may have any z gt 1 but in practice z values of the form 2 k for integer k are often preferable similarities between encoder 1800 and encoder 1000 are apparent in particular the encoder control module 1802 and the operation control module 1812 function in the same or similar manner as their respective counterparts 1002 and 1012 in encoder 1000 for example to encoder ldpc code defined in fig1 and 13 the operation of these components would be exactly the same as their counterparts in encoder 1000 when encoding the example code 400 the encoding memory 1806 is a vectorized version of its counterparts 1006 in encoder 1000 whereas in encoder 1000 the memories stored single bits the corresponding memories in encoder 1800 store sets i e z bit vectors these vectors are written and read as single units using simd instructions thus the message identifiers sent to the memory from the ordering control 1804 i e memory indices are equivalent or similar to those in encoder.