110 in fig1 it is common to form these two transistors 105 110 in a single rx semiconductor island using soi technology both gates are driven by the same node this arrangement 100 is commonly referred to as u201c side to side u201d stacking of the two transistors 105 110 where such stacking is relatively efficient in terms of area of the integrated circuit ic utilized i e a relatively compact transistor layout as well as the amount of interconnect wiring required as seen in fig1 the gate terminal conductors 125 130 for each of the two transistors 105 110 are parallel to each other however a problem with this prior art u201c side to side u201d transistor stacking arrangement 100 is that from an ser perspective primary or secondary ionizing radiation particles traveling in the soi plane have a relatively large solid angle where they can travel from the body of one cmos transistor 105 110 in fig1 to the body of the other cmos transistor 105 110 and cause an upset in other words the ionizing particles have a relatively large solid angle for hitting both transistors 105 110 this relatively large solid angle is represented as the angle between the two lines with arrowheads 135 140 shown in.