will be described in detail with reference to accompanying drawings fig5 is a block diagram showing the structure of an inflector point detector applied to an fsk demodulator according to a first embodiment of the present invention the inflection point detector includes a 32 stage shift register 51 an inflection point extraction circuit 52 an amplitude monitoring circuit 53 preamble detectors 54 and 55 an and gate 56 an edge detector c 10 a pre frequency offset generator c 11 and a delay circuit c 16 the 32 stage shift register 51 retains sample values corresponding to amplitude values of a frequency detection signal s 0 by two symbols after sampling the frequency detection signal s 0 at an operating clock rate that is 16 times greater than a symbol rate in addition as shown in fig5 the 32 stage shift register 51 has retained outputs of a first shift register or a 32th shift register the 32 stage shift register 51 outputs sample values of the frequency detection signal s 0 which are sequentially input from the first shift register while retaining the sample values in addition the sampling rate is not limited to 16 times greater than the symbol rate for example the sampling rate may be 32 times greater than the symbol rate if the sampling rate is 32 times greater than the symbol rate the shift register 51 must have 64 stages the inflection point extraction circuit 52 corresponds to an inflation point extraction part and includes subtracters c 1 to c 3 an absolute value.