decade the binary stage thus contains the most significant or 1000 39 s digit counted by the counter 13 which may have a value of either zero or one the counter 13 thus serves not only as a pulse counter but in addition as a frequency divider for the pulses produced by the clock 11 no provision for reset is made of the counter 13 since in accordance with the invention it is not reset at any time during the conversion cycle the outputs of each of the stages of the counter 13 are connected to the display register 15 the register 15 includes individual units 10 39 s 100 39 s and 1000 39 s buffer registers which are connected to the corresponding stages of the counter 13 the counts of the counter 13 are synchronously transferred to the display register 15 at the completion of the a d conversion cycle the outputs of the three decade stages of the display register 15 are decoded by the binary to 7 segment decoders 17 which in turn control the actuation of the corresponding electrode segments of the liquid crystal display 19 through individual exclusive or gates 21 in order to simplify the drawings only one of the exclusive or gates 21 is.