the present invention in order to increase surface area beyond that of prior art stacked capacitors that are straight cylinders or open boxes in shape although the concave shape of the present invention can be a simple virtually enclosed container the container can also include additional surfaces such as convoluted surfaces various means for achieving desired structural and functional results are used in the practice of the instant methods and in the achieved structures the integrated circuit dram device of the present invention is comprised of dual gate structures that are situated above a substrate on a semiconductor substrate the substrate integrally has active areas that enable the gate structures to function as respective transistors transistor structures of this type are well known in the art in which various capacitor structures for use on an integrated circuit dram have first and second word lines and first and second digit lines the integrated circuit being fabricated on the semiconductor substrate the methods disclosed herein and the achieved structures preferably incorporate a doped or undoped polysilicon storage node which can be employed within a stacked capacitor a polysilicon plug is used to contact the polysilicon storage node a hard mask which is preferably a nitride or oxide layer is described below which is preferably easily formed and sacrificed the cell dielectric is preferably composed of oxide or nitride dielectric materials that deposit and cover thinly and evenly upon storage node materials the cell plate is preferably made of doped polysilicon and is formed by known methods the spacers discussed below are made from polysilicon and oxides or nitrides that can be etched selectively over materials into which the spacers are formed the first twelve embodiments of the present inventive method are methods of stacked capacitor formation in which a polysilicon plug.