solder bumps to the first electrical terminals second electrical terminals are attached to the upper surface of the support second electrical pathways connect the first electrical terminals to the second electrical terminals application_number US 37341403 A description while the making and using of various embodiments of the present invention are discussed herein in terms of a wafer testing interposer and semiconductor wafer assembly apparatus and method it should be appreciated that the present invention provides many inventive concepts that can be embodied in a wide variety of contexts the specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and in no way meant to limit the scope of the invention the present invention provides a wafer testing interposer that can be combined with a semiconductor wafer to form an assembly that can be used to test semiconductor die prior to dicing or singulating this allows several manufacturing steps to be eliminated and thus results in improved first pass yields decreased manufacturing times and improved cycle times additionally the use of the interposer revolutionizes the processing of the semiconductor dies by enabling testing and burn in at the wafer level eliminating the need to singulate and package the dies before testing results in a significant cost avoidance opportunity for chip manufacturers the fact that the use of the interposer accomplishes all of this while adding no impediment to the packaging of the singulated die produced after successful testing is another substantial benefit of the present invention 0021 fig1 shows one form of the invention as a quadrilateral wafer interposer comprising a support 120 which has a set of electrical terminals 130 on the upper surface and solder bumps.