implementation with reference to fig4 an exemplary system for implementing the subject matter disclosed herein includes a hardware device 400 including a processing unit 402 memory 404 storage 406 a data entry module 408 a display adapter 410 a communication interface 412 and a bus 414 that couples the elements 404 412 to the processing unit 402 the bus 414 may comprise any type of bus architecture examples include a memory bus a peripheral bus a local bus etc the processing unit 402 is an instruction execution machine apparatus or device and may comprise a microprocessor a digital signal processor a graphics processing unit an application specific integrated circuit asic a field programmable gate array fpga etc the processing unit 402 may be configured to execute program instructions stored in the memory 404 and or the storage 406 and or received via the data entry module 308 the memory 404 may include read only memory rom 416 and random access memory ram 418 the memory 404 may be configured to store program instructions and data during operation of the hardware device 400 in various embodiments the memory 404 may include any of a variety of memory technologies such as static random access memory sram or dynamic ram dram including variants such as dual data rate synchronous dram ddr sdram error correcting code synchronous dram ecc sdram or rambus dram rdram for example the memory 404 may also include nonvolatile memory technologies such as nonvolatile flash ram nvram or rom in some embodiments it is contemplated that the memory 404 may include a combination of technologies such as the foregoing as well as other technologies not specifically mentioned when the subject matter is implemented in a computer system a basic input output system bios 420.