given priority over segment 12 segment 12 is given priority over segment 13 and segment 13 is given priority over segment 14 the registers and decoder 25 allow the registers in interface queue 10 to be cleared to allow for further processing of requests request hold register 20 holds up to four requests one for each segment until the snapshot register 23 is in a receiving mode the requests are than directed into the snapshot register 23 the snapshot register 23 then directs the requests to the main storage unit 26 in accordance with direction from the priority logic 24 during the time interval the snapshot register is in a non receive mode multiplexer 21 prevents further requests from being sent to the snapshot register 23 that is multiplexer 21 prevents further requests from entering the snapshot register 23 while requests are being processed by the snapshot register 23 thus the non receive mode of the snapshot register 23 is determined by the multiplexer 21 after the snapshot register 23 receives the requests all the requests in the snapshot register 23 are prioritized and handled before the multiplexer 21 allows the snapshot register 23 to receive any new requests this ensures that the low priority requests in the snapshot register 23 will be handled before any later higher priority requests thus ensuring that the high priority requests do monopolize the msu 26 by continually making requests that are serviced first although the dual latch system assures access to the low priority request the dual latch system can waste time for example if a request is made when the snapshot register is empty the request is first captured in the request hold register and than transferred to the snapshot register 23 on the next clock cycle with the.