been predestined by the block 46 report to the counter 50 the counter 50 counts all of the pixel reports from both the block 44 and the block 46 for a full block when the block of pixels begins at the pixel difference block 43 the processor not shown in fig3 enables the counter via enable line 48 at the conclusion of a block the processor resets the counter to zero by the reset line 49 thus the counter 50 is always counting the excess deltas or the pseudo excesses reported by the block 46 as the case may be in one block of video information the number of excess deltas counted by the counter 50 is reported to the comparators 51 which determine whether the counted number of excess deltas exceeded the count threshold 52 for the block reported if they did the comparators 51 report the block condition changed or unchanged to the block update memory 55 which sets a flag for each block that requires updating i e communication to the receiving end when the frame of input video 41 is completed the block update memory communicates the block identities that require communication based on the set flags to the memory controller 58 which causes a download of those blocks from the reference memory to the dvc compression block 59 once a block is identified for transmission the memory 57 provides the blocks that require communication to the dvc compression.