providing the binary k signal is connected to a second input terminal of and gate 42 the output terminals of and gates 40 and 42 are connected to respective first and second input terminals of nor gate 44 as shown hence the logic implemented by gating arrangement 38 corresponds to the boolean expression hk hk shown in fig1 c the decoder gating arrangement 46 for mechanizing the logic to selectively activate the segment of display designated d includes and gate 48 and nor gate 50 the output terminal of flip flop 14 providing the binary k signal is connected to a first input terminal of and gate 48 the output terminal of flip flop 12 providing the binary h signal is connected to a second input terminal of and gate 48 the output terminal of and gate 48 is connected to a first input terminal of nor gate 50 the output terminal of flip flop 13 providing the binary j signal is connected to a second input terminal of nor gate 50 hence the logic implemented by the gating arrangement 46 corresponds to the boolean expression j hk shown in fig1 c the decoder gating arrangement 52 for mechanizing the logic to selectively activate the segment of display designated e includes and gate 54 or gate 56 and nand gate 58 the output terminal of flip flop 12 providing the binary h signal is connected to a first input terminal of and gate 54 the output terminal of flip flop 13 providing the binary j signal is connected to a second input terminal of and gate 54 the output terminal of and gate 54 is.