for example the gate stack layers can be patterned by an anisotropic etch process employing a patterned photoresist not shown as a masking layer to form a gate stack including a gate dielectric 50 a gate electrode 52 and optionally a gate cap dielectric 58 the gate dielectric layer and consequently the gate dielectric 50 can include a dielectric material which can be silicon oxide silicon nitride silicon oxynitride or a stack thereof alternately or additionally the gate dielectric layer and consequently the gate dielectric 50 can include a high dielectric constant high k material layer having a dielectric constant greater than 3 9 in one embodiment the gate dielectric layer can include a dielectric metal oxide which is a high k material containing a metal and oxygen and is known in the art as high k gate dielectric materials dielectric metal oxides can be deposited by methods well known in the art including for example chemical vapor deposition cvd physical vapor deposition pvd molecular beam deposition mbd pulsed laser deposition pld liquid source misted chemical deposition lsmcd atomic layer deposition ald etc exemplary high k dielectric material include hfo 2 zro 2 la 2 o 3 al 2 o 3 tio 2 srtio 3 laalo 3 y 2 o 3 hfo x n y zro x n y la 2 o x n y al 2 o x n y tio x n y srtio x n y laalo x n y y 2 o x n y a silicate thereof and an alloy thereof each value of x is independently from 0 5 to 3 and each value of y is independently from 0 to 2 the thickness of the gate dielectric layer 50 l can be from 0 9 nm to 6 nm.