upon the two sequences producing a large cross correlation product when the two sequences are aligned the result of each correlation is summed by an adder 322 and a running sum of previous correlations occurring within the same clock period is stored in register 323 a counter 324 running at a clock rate clk 349 counts down from n u2212 1 to 0 at which time the terminal count signal 327 goes high thereby activating register 326 to output the accumulated result over the n samples the clk signal 349 is generated by a clock source 340 the clock source 340 includes a voltage controlled oscillator vco 342 a divide by 31 circuit 344 a counter 346 and a sample mode select switch 348 the vco 342 provides a reference signal 343 to the counter 346 and the divide by 31 circuit 344 in the preferred embodiment the reference signal operates at a frequency of 32x the chip rate 1 2288 mhz or 39 3216 mhz the divide by 31 circuit 344 generates a beat clock signal 345 equal to 32 31 x chip rate further discussed below from the 32x reference frequency 343 the counter 346 generates 1x 2x 4x 8x and 16x clock signals 347 a e responsive to a control signal 341 a clock source switch 348 selects either the beat clock 345 or one of the counter.