the same dlct out of the wls connected to these cells while the wl 2 is connected to the swda u the wl 3 is connected to the swda d therefore in the layout of the word line noise decreased memory array of embodiment 1 the wls connected to the two memory cells sharing the dlct are connected to different swd arrays in an overall view of the memory array as the pattern shown in fig1 a is reiterated vertically and horizontally half of the wls connected to the mcs connected to the dl 0 t wl 1 and wl 5 in the diagram are connected to the swda u and the other half wl 0 and wl 4 in the diagram are connected to the swda d further half of the wls connected to the mcs connected to the dl 0 b wl 2 and wl 6 in the diagram are connected to the swda u and the other half wl 3 and wl 7 in the diagram are connected to the swda d accordingly out of all the word lines connected to memory cells connected to any one data line half are connected to one of the two subword driver arrays and the other half are connected to the other subword driver array furthermore swds in the swda u are connected to vssu a common vss line similarly swds in the swda d.