nitride layer in order to form nitride transistor gate spacers 90 referring now to fig1 mask 100 is patterned over p well region 55 which is followed by an p type dopant implant into the non masked p well region 54 to form p type doped source drain regions 101 as an exemplary implementation of the present invention the formation of a typical p type source drain may consist of a p implant using boron species bf249 with an implant dose of 1 5e15 atoms cm 2 at 10 kev referring now to fig1 mask 100 seen in fig1 is removed and mask 110 is patterned over n well region 54 which is followed by an n type dopant implant into the non masked p well region 55 to form n type doped source drain regions 111 as an exemplary implementation of the present invention the formation of a typical n type source drain may consist of a n implant using arsenic species as75 with an implant dose of 2 0e15 atoms cm 2 at 20 kev referring now to fig1 the final inter well isolation structure 50 and intra well isolation structures 51 are shown in their completed form inter well isolation structure 50 provides increased isolation between p channel transistors and neighboring p well region as well as increased isolation between n channel transistors and neighboring n well region isolation is provided between n to n well and p to p well by reducing leakage current due to the reduction of the formation of undesirable leakage paths between opposite biased regions a second exemplary implementation of the.