can be used for compare circuit 128 many such compare circuits 128 are known in the art and could be used so the details are not shown in a schematic for example in one embodiment the compare circuit is composed of a first stage of exclusive or logic circuits each xor circuit receives a bit of the expectant and a bit of the resultant signature word the first xor cell can receive the least significant bits of the expectant signature word and the resultant signature word successive xor cells are connected in a like manner until the final xor receives the most significant bits of the expectant signature word and the resultant signature word a second stage xor cell receives the results of the first stage of xor cells the second stage xor cell provides a verification status at an output pin the output pin of the second stage xor cell is connected to a first input pin of a multiplexer cell having a second input pin connected to the second supply gnd other compare schemes can be used as noted above the test control logic on the chip allows the rom 10 to be placed in test mode the output pin of the compare circuit 128 can be connected to an input pin of an i o pad cell 130 if desired the i o pad cell 130 provides a connection to the external test equipment such as confirm circuit 131 thus the compare circuit 128 structured in the above manner generates the verification status at combinational logic speed of an xor circuit the combinational logic speed of the compare circuit 128 is faster than the equivalent compare operation on standard external.