a plurality of drain regions 22 and a plurality of source regions 24 both of which are impurity diffused layers 20 are formed on a semiconductor chip 10 to extend parallel to each other these impurity diffused layers 20 serve as bit lines a plurality of control gate regions 30 are provided on the semiconductor chip 10 to form a striped shape extending in a direction perpendicular to a longitudinal direction of the drain regions 22 and the source regions 24 a memory cell of the nonvolatile memory is defined at an intersection of the neighboring drain region 22 and source region 24 and one of the control gate regions 30 as shown by a dotted line i in fig4 a accordingly memory cells of the nonvolatile memory of the first embodiment having a bit line assembly consisting of bit lines formed by diffused layers are arranged in an array pattern each memory cell of the nonvolatile memory is provided with a floating gate 40 the floating gate 40 is formed on the semiconductor chip 10 via a floating gate insulation film 45 and the floating gate 40 is arranged between the drain region 22 and the source region 24 the control gate region 30 is formed either on the floating gate 40 via a control gate insulation film 35 or on the semiconductor chip 10 via an interlayer insulation film 50 a width of the drain region 22 along a channel direction and a width of the source region 24 along a channel direction are referred to as a drain width and a source width respectively it should be noted that the channel.