power down and self refresh modes only by the state of the we signal as a result when the memory device 10 transitions out of one of the power down modes responsive to the we signal transitioning from low to high the command decoder 70 signals the memory device 10 to perform no operation thereby avoiding spurious data from being written to or read from the memory device 10 the read commands are signaled by decoding the ras cas and we signals as u201c 101 u201d and differentiated from each other by the state of the a7 address signal latched on the falling edge of the ck signal which is designated as the a7f bit the normal read command read is signaled by decoding the a7f signal as u201c 0 u201d and the auto precharge read command read ap is signaled by decoding the a7f signal as u201c 1 u201d the addresses for a read command are applied to the address register 12 as a7 a0 signals latched on the rising edge of the ck signal c 2 c 9 and the a2 a0 signals latched on the falling edge of the ck signal c 0 c 1 cf which are designated as the a7r a0r and a2f a0f bits respectively similarly the write commands are signaled by decoding the ras cas and we signals as u201c 100 u201d and also differentiated from each other by the state of the a7 address signal latched on the falling edge of the ck signal which is designated as the a7f bit the normal write command write is signaled by decoding the a7f signal as u201c 0 u201d and the auto precharge write command write ap is signaled.