circuit 50 the second pre charge circuit 15 is substantially the same as the pre charge circuit described in relation to fig2 a hence the same number designation in the illustrated embodiment of fig3 a the first pre charge circuit 50 pre charges the output node vbl of the bit line pair bl and bl with a first voltage when the constituent memory device is in a standby state here the first voltage may be equal to one half the power voltage vcc or some other voltage level in other words when the memory device is in a standby state a pair of switching elements 53 and 54 within the first pre charge circuit 50 is turned off such that a first voltage supplied from the first pre charge circuit 50 to the output node vbl is a preliminary voltage ranging between an upper voltage v 1 and a lower voltage v 2 here when the operational state of the memory device transitions from standby to active in response to an externally applied activation signal act or a power up signal vcch the second pre charge circuit 15 also goes active and pre charges the bit line pair bl and bl to exactly one.