by the selector 340 and the decoder 350 outputs 8 bit data corresponding to x 1 y 1 the data of the central one bit and the 8 bit data corresponding to each of x 0 y 0 and x 1 y 1 are stored in a latch abbreviated to lt 370 at the timing recovered by delay elements 368 and 367 the data in the latch 370 is transmitted to a latch 375 and a latch 376 sequentially in response to every clock and 17 bit data is supplied from the latch 376 as recorded data the most significant four bits of the 17 bit data stored in the latch 375 and the least significant one bit of the 17 bit data stored in the latch 376 are connected to a bit correction circuit 380 if the respective bits satisfy the conditions shown in the left of the expression 2 the data pattern in the latches 375 and 376 is converted into the corresponding pattern in the right of the expression 2 also in the case of data patterns shown in the expression 3 similar data conversion is executed along the expression 3 one comparator 300 and one decoder 310 are used in common for the most significant 8 bits and.