or high at the same time the wordline rises up to vcc and the y select signals activate the y select signals are enabled by yselclk in their decoders eventually sufficient differential builds up between the bit line and the reference bit line and this is transferred to node a and node b the romsac signal then goes high which grounds the senseamp latch and forces node a and node b to go to either zero or vcc depending on whether a bit has been programmed a bit is programmed if a bit transistor is present a bit is not programmed if a bit transistor is not present at this point bit information has been ascertained and the senseamp latch is set if a bit transistor is not present node a is at vcc and node b is at zero no current is drawn as shown in fig1 a if a bit transistor is present node a is at zero and node b is high node b wants to be at vcc but there is a current path from the senseamp pullup pmos device on node b through the yref transfer gates and down to ground through the reference bit this current is wasted and needs to be eliminated it is stopped by yselclk going to zero and disabling all the y select signals the yref transfer gate has two purposes one is to duplicate the impedance from the bit line to the senseamp the other is to act as the gate to be turned off to stop the current for every 32 columns there is one reference bit column the 32 columns are selected down to one by the two y select stages thus when an address transition is.