gate 26 will be separated from one of the two n type regions 12 of the fet by only the thin layer of oxide 24 in the overlap area 22 this close proximity creates a capacitance 30 between the gate 26 and the nearer of the two n type regions 12 and may degrade the speed of operation of the fet capacitance 30 may represent either a gate drain capacitance or a gate source capacitance depending upon the circuit configuration in which the fet is employed if the circuit in which the fet is employed involves a significant voltage gain the effect of capacitance 30 may be increased substantially by the miller effect and will severely limit the speed of operation of the fet referring now to fig2 a d there is shown a cross section of the substrate 10 as the fet is fabricated in accordance with the preferred embodiment of the present invention fig2 a 2b and 2d are identical to fig1 a 1b and 1f respectively described above except that no overlap area 22 occurs in the process of the present invention referring now to fig2 c there is shown a single step to simultaneously fabricate both the thin layer of oxide 24 over the channel 18 and the thick oxide layer 23 over the two n type regions 12 of the fet it has been observed that at temperatures below 1000 u00b0 c the rate of growth of oxide over areas of silicon which have been heavily doped with phosphorous to.