store data a series of flag registers 307 and a shift control register u201c scr u201d 360 in the exemplary embodiment the scr 360 is an 8 bit register with the most significant bit designated bit 7 and the least significant bit designated bit 0 the function of the flag registers 307 and the scr 360 will be explained later the pe 200 also includes two registers blocks namely the m block 350 a and the q block 350 b the m block 350 a includes a bus called the m bus 307 a which is coupled to the node communications interface 305 the m bus 307 a is also coupled via logic circuit 308 a to a plurality of registers these registers include the m3 310 m2 311 m1 312 m0 313 and ms 314 registers in some embodiments an optional a g register 320 may also be present the g register 320 may be used for example to store extension bits for use in higher precision calculations in one exemplary embodiment registers m3 310 m2 311 m1 312 and m0 313 are 8 bit registers while register ms 314 is a single bit register logic circuit 308 b couples registers m3 310 m2 311 m1 312 m0 313 ms 314 and g 320 to q bus 307 b alu 301 and dram interface 304 the logic circuits 308 a and 308.