used to identify each 64 bit quadword the column address is the low order twelve bits of the twenty four bit address processor pins a3 a14 and the row address is the high order twelve bits of the twenty four bit address processor pins a15 a26 the three address pins a0 a2 are not considered part of the twenty four bit address in fig4 the twelve column lines 65 from the address bus 24 are used by the interface logic 16 and the processor 12 in a manner similar to that described in connection with fig3 during a page miss operation the interface logic 16 of fig4 stores the row and column addresses and forces the processor 12 to relinquish control of the address bus 24 the interface logic 16 then drives the row and then the column address to the memory unit 18 over the column address bus 65 and thereby also over the interface bus 69 for a page hit operation the processor 12 directly drives the column address over the column address bus 65 and thereby also over the interface bus 69 to the memory unit 18 thus the embodiment of fig4 operates in a manner similar to that of fig3 the interface logic 16 of fig4 is capable of enabling a burst capability when the processor 12.