input to the rising edge detection logic 503 to generate the second digital value tdc_val the second digital value tdc_val is a multi bit digital value with its bit width dependent on the maximally possible timing difference td between the rising edges of the second clock refclk and the dithered pulse signal dps the rising edge detection logic 503 may determine the second digital value tdc_val using the following algorithm in one embodiment the timing error estimator 240 is configured to receive the delayed dither signal dds the first digital value cnt_val the second digital value tdc_val and the second clock refclk and to generate the timing error te fig6 schematically shows details of the timing error estimator 240 in accordance with an embodiment of the present invention the timing error estimator 240 is used to estimate the timing error te in the phase locked loop 100 the timing error estimator 240 includes a rough timing error estimator 600 a fine timing error estimator 610 and a summer 620 the rough timing estimator 600 is configured to receive the first digital value cnv_val and the second clock refclk and to generate a rough timing error 621 the first digital value.