a relatively high voltage and the complementary bit line 106 to a relatively low voltage current flows through and melts the phase change memory element 108 and the complementary phase change memory element 110 to store a data bit value of u201c 1 u201d the bit line 104 is then turned off with an abrupt trailing edge and the phase change memory element 108 cools to the amorphous state meanwhile the complementary bit line 106 is turned off with a gradual trailing edge and the complementary phase change memory element 110 cools to the crystalline state this causes the complementary data bit to store a representation of u201c 0 u201d in order to store a u201c 0 u201d crystalline state in this particular embodiment of the invention in the content addressable memory cell 102 the inverse operations are performed specifically the encoder sets the bit line 104 to a relatively low voltage and the complementary bit line 106 to a relatively high voltage charge flows through and melts the phase change memory element 108 and the complementary phase change memory element 110 the bit line 104 is then turned off with a gradual trailing edge and the phase change memory element 108 cools to the u201c 0 u201d state meanwhile the complementary bit line 106 is turned off with an.