be described in that environment however this should not be construed as a limitation on the scope of the invention since it is well within the skill of one skilled in the art to make minor changes without deviating from the teachings and spirit of the present invention 0033 fig1 shows an architecture for a network processor including the booster cam system 15 according to the teachings of the present invention the booster cam system 15 is coupled to the embedded processor complex epc 12 by communications media 15 a the network processor which may be implemented as a single chip or a plurality of chips include physical layer devices 26 including ethernet packets or ip over sonet pos pmm ingress multiplexed macs 22 and enqueue dequeue scheduling 14 including ingress data storage 42 and ingress switch interface 18 on the egress side the network processor includes egress switch interface 20 enqueue dequeue scheduling 16 and egress data storage 44 still referring to fig1 embedded processor complex epc 12 is coupled over communications media to the ingress eds and egress eds a plurality of different storage modules including internal s rams 28 d rams 32 and external s ram 30 are connected to the embedded processor complex an embedded power pc processor 34 is coupled to the embedded processor complex a pci interface bus provides access from the.