effect semiconductor device and a gate coupled to the drain 114 of fet transistor 108 in this embodiment the gate of fet transistor 108 represents the word line and its source 112 represents the bit line referring to fig2 there is shown a top view of the physical structure of device 200 the central region 206 operates as a poly silicon gate 206 the drain 202 is shown on the left and the source 204 on the right the arrows indicate the flow of current the center arrow depicts the current flow from drain 202 to source 204 in an nfet negative channel field effect transistor assuming positive voltage drops vds active region 208 is shown to the right since there is no doping alteration there is no current loss fig3 a shows a front view of the structure of the embodiment of fig2 the structure comprises the drain 202 the source 204 and a gate 206 in addition a first layer 209 of silicide is deposited over the drain 202 and a second layer 211 of silicide is deposited over the source 204 a layer 207 of gate oxide is located between the gate 206 and the drain to source channel fig3 a shows a standard fet region in the middle of the fet fig3 b shows the same structure but with the silicide layers 209 211 encroaching past the diffusion junction 250 directly touching the soi body 201 the.