also a possibility that the charge on bitline bl 2 102 when wl 1 104 is high will u201c flip u201d the value on node 110 of the sram cell 124 to an opposite value due to charge sharing the sizes of nfet mn 1 116 nfet mn 2 118 nfet mn 3 120 nfet mn 4 122 pfet mp 1 112 and pfet mp 2 114 among other reasons are chosen to provide enough drive strength to hold the drains of nfets mn 3 120 and mn 4 122 in their present state preventing the sram cell 124 from flipping when data is read in addition the sizes of these six fets are chosen to simultaneously optimize for the read access time of the sram cell 124 data may be written to an embodiment of an sram cell shown in fig1 by first driving wl 1 104 to a high logical value after driving wl 1 104 to a high logical value bl 1 100 is driven to either a high or low logical value at the same time bl 2 102 is driven to the opposite value of the value on bl 1 100 typically this causes the sram cell 124 to flip to the logical value imposed by bl 1 100 and bl 2 102 after the sram cell 124 is written wl 1 104 is discharged to a low logical value the power supply voltage vdd used in this example for the sram cell 124 is the same power supply voltage vdd used for all the peripheral circuitry on the sram.