119 the main word lines 117 are formed in the same manner as in the previously described embodiments referring to fig1 a slit type via hole 121 is formed in the upper interlayer insulating layer a main plate line 123 is then formed as previously described modifications of the embodiments described in fig1 18 will now be described with reference to fig1 the modified embodiments are identical to the embodiments of fig1 18 except that the local plate line 115 is not formed in this case the slit type via hole 121 exposes the common top electrode 109 a method of fabricating a ferroelectric memory device according to further embodiments of the invention will now be described with reference to fig2 through fig2 in these embodiments cell transistors a lower interlayer insulating layer and contact plugs are formed in the same manner as in the previously described embodiments referring now to fig2 a conductive bottom electrode layer is formed on the lower interlayer insulating layer 74 and the contact plugs 75 the bottom electrode layer is patterned to form a plurality of bottom electrodes 151 covering the contact plugs 75 a lower insulating layer 153 is formed on the bottom electrodes 151 referring now to fig2 the lower insulating.