parameter in the register and a second execution thread accessing the data from the register application_number US 42611903 A description 0010 fig1 shows a high level block diagram of a multiprocessor computer system including an embodiment of the claimed subject matter this system may in general include several processors for example the processors 100 and 102 in the figure one of the processors in this embodiment is designated the bootstrap processor bsp at startup for example by some deterministic protocol the other processors are termed application processors aps the processors are socketed into a system board using board logic and interconnect the processors are able to access a shared memory subsystem 110 by means of a bus such as a front side bus fsb 140 and a memory controller which is part of an integrated device 120 in other embodiments of the claimed subject matter there may be more than two processors and the bus configuration connecting them to memory and other parts of the system may differ moreover the processors may not be part of a general purpose computer system as depicted in fig1 but rather part of any device that uses digital processing capabilities including digital communication devices such as telephones or network routing devices hand held devices such as personal digital assistants pdas and dedicated subsystems included in other digital devices such as a digital television.