a layer of metal silicide 37 a is formed on an upper surface of the gate electrode stack while a layer of metal silicide 37 b is formed on the source drain regions 31 32 a dielectric sidewall spacer 38 such as silicon oxide is formed on the side surfaces of the gate electrode in accordance with the embodiments of the present invention a conformal undoped silicon oxide layer 39 such as silicon oxide derived from teos by sa cvd is deposited over the gate structures into the gaps in accordance with the present invention bpsg layer 300 is then deposited in situ in the same deposition chamber using essentially the same deposition conditions employed for depositing undoped silicon oxide layer 39 followed by rapid thermal annealing subsequent processing includes forming contact holes 400 as by anisotropic etching in accordance with the present invention a conventional silicon nitride liner is strategically replaced with an undoped silicon oxide liner deposited by sa cvd followed in situ deposition of a bpsg layer in the same deposition chamber thereby improving data retention improving gap filling increasing manufacturing throughput and reducing defects caused by wafer handling the present invention provides microminiaturized semiconductor devices such as eeprom devices with improved reliability increased operating speed improved data retention and increased manufacturing throughput with an attendant reduction in manufacturing costs the present invention enjoys industrial applicability in manufacturing various types of semiconductor devices particularly highly integrated semiconductor devices exhibiting.