computed as the partial product the rearrangement in sign and carry positions has the effect of perfectly matching the resources of a 5 2 adder array in that 5 partial products are produced when a single fused result is needed and when two results are required the 5 2 adder array can be partitioned as shown in fig4 so as to produce both the head and tail results when the operands are all the same size and the size is 2 n bytes the fuse bits at 2 n byte element boundaries are identical so the entire set is just a 4 b thermometer code booth byte multiply was used in the exemplary embodiment because 5 2 is the largest wallace tree that degenerates to a serial array adder simplifying the partition multiplexing of high order and sign bits the enhanced booth circuitry of fig3 eliminates multiplexing the low order bits because disabling the fuse signal automatically converts the two low order partial product bits ppr and ppl to the logic functions after carry ripple shown in detail in fig7 here p1 p2 and f1 f2 are the and and or control inputs to the aoi booth multiplexor respectively or the signals x1pass x2pass x1force x2force respectively preservation of internal accuracy enables ideal signal noise ratios and is especially valuable in algorithms such as newton raphson or sigma delta sensitive to zero crossings when large products cancel two different addition orders may differ at every bit so precision simplifies logic verification the effective internal bandwidth of a lossless matrix.