will be seen with greater detail below the implant process must be carefully designed to achieve three goals 1 small base width for larger gain 2 higher emitter doping than the p well doping for high injection efficiency and less total p 31 dose for less damage by the high energy implant the buried n layer 203 is preferably implemented by p 31 with multiple energies 500 kev and 750 kev with doses of about 1e15 each on current triple well 0 35 micron cmos technology the buried n layer 203 together with the deep n well will serve as the emitter for the bipolar transistor 201 the p well 209 serves as the base and the n region 207 as the collector thus the npn bipolar transistor 201 will be used in u201c common emitter u201d configuration and turned on by gidl current from the gated base collector p well and n structure the trench isolations 205 preferably extend deeper than the p well depth approx 1 micron the trench isolations 205 can be formed by a masking step for a trench etch at the front end of the fabrication process in comparison typical shallow trench isolation structures for 0 35 micron cmos transistors extend only about 0 3 0 5 microns deep thus trench isolations 205 for isolating p wells can also be used as shallow trench isolation structures for cmos transistors the trench isolation technique will result in smaller spacing and is therefore preferred in any case the trench isolations 205 must be at least slightly deeper than the.