memory site represents the bit series 000 in conventional single bit line roms storage of such seven state information would require three separate memory sites in order to read the seven different information states that can be stored at a particular memory site in the circuit of fig2 a and 2b the four bitlines and one wordline associated with that particular memory site must be accessed to read the value of the data stored at memory site 207 wordlines 237 242 are grounded to ensure that the channels within associated fets 215 220 and 222 227 are maintained in a non conductive state simultaneously wordline 243 is supplied with a voltage v dd so that the channels within fets 221 and 228 are placed in a conductive state a connection between decoder circuit 200 and bitlines 229 232 is then effected by supplying bitline control conductor 244 with voltage v dd while grounding bitline control conductor 245 this places the channels within fets 246 249 into conductive states and maintains the channels within fets 250 253 in non conductive states fets 254 256 fig2 b are then clocked sequentially with non overlapping signals clk 1 clk 2 and clk 3 as illustrated in fig3 following one full sequence of the three clock signals the logic devices in fig2 b 257 262 produce an output that is indicative of the fet bitline connections for the fet at the particular memory site being read a logical 1 signal at the q outputs of flip flops 257 262 and the output of and gate 263 correspond to the following bit series ______________________________________bit series logical 1 output at ______________________________________110 q of flip flop 262101 q of flip flop 261100.