adapter pe 222 coupled to the hypervisor adapter driver 114 and a plurality of afu pe 1 3 224 226 228 with afu pe 1 2 224 226 coupled to host os 110 and afu pe 3 228 coupled to host os 112 as shown phb 220 includes isolation facilities 226 provided with afu pe 1 3 224 226 228 computer system 200 includes an input output i o adapter 230 providing a coherent accelerator with transaction layer functions including for example a pci services layer psl 232 providing all functions and facilities consistent with a pcie endpoint function and a plurality of afus 1 3 234 236 238 with the psl 232 coupled to the adapter pe 222 and each afus 1 3 234 236 238 coupled to a respective afu pe 1 3 224 226 228 computer system 200 enables coherent accelerator adapter enhanced functionality with the additional afu pes 1 3 224 226 228 each associated with the respective afus 1 3 234 236 238 when the adapter 230 does dma transactions it encodes the respective one of afus 1 3 234 236 238 performing the transaction for example using alternative routing id interpretation ari techniques into the dma packets this allows for fault isolation down to a single one of afus 1 3 234 236 238 while still only implementing a single pci function with a single configuration space this is an increasingly important and valuable feature as the number of afus on an adapter 230 increases host os mmio activities are governed by the respective afu pes 1 3 224 226 228 each respective afu pes 1 3 224 226 228 advantageously can be frozen such that.