input to each of the logic gates and0 and7 via a transmission line int1 the impedance of the transmission line int1 is represented by a series of resistors r and capacitors c points of the transmission line int1 that serve as inputs to each of the logic gates and0 and7 are designated as int1 0 int1 7 respectively although not shown in a similar manner a second transmission line a second group of logic gates and a second group of registers are associated with i o ports dq8 dq15 in this way the clk1 and doe signals simultaneously control the timing of the output of the internal signals dat0 dat7 on the ports dq0 dq7 respectively and the clk2 and doe signals simultaneously control the timing of the output of the internal signals dat8 dat15 on the ports dq8 dq15 respectively although the clk1 and clk2 signals are affected by their associated transmission line loads the impact on the speed of the device 20 is greatly reduced compared with the device 10 fig3 as shown below referring to fig6 an access time for the entire device 20 is measured from the time the clk0 signal rises at point p3 until the last i o port dq0 dq14 has valid data in the improved circuit of fig5 a transmission line delay trc0 representing the propagation time for the clk1 signal to travel from the clk1 input to the point int1 0 is slightly greater than a transmission line delay trc3 representing the propagation time for the clk1 signal to travel from the clk1 input to the point int1 3.