a collector of a protection transistor 903 and to amplifier 610 and drives it with an analog signal derived from a digital beam landing error correction data word 311 a similarly a d a converter 312 is coupled to amplifier 660 and drives it with an analog signal derived from a digital beam landing error correction data word 312 a during the deflection cycle words 311 a and words 312 a are read out of a memory 305 via a controller or control logic circuit 301 in a conventional manner memory 305 forming a volatile memory space has a sufficiently fast access time for fetching successive words as the beam landing location varies on screen 700 to provide for dynamic convergence an electrically erasable programmable memory eeprom 550 forming a first non volatile memory space and containing digital beam landing error correction data words 550 a is coupled to control logic circuit 301 via a bus 550 b memory 550 includes for example four 2k byte memory spaces not shown for providing words 311 a and 312 a the four 2k byte memory spaces are used when stage 600 operates in a selectable horizontal scan frequency 1h 2h 2 14h or 2 4h respectively where h is equal to 15 734 hz during a mode set up occurring as part of a power up procedure or when a change of for example a horizontal.