clock so that stopping stepping or bursting of the system clock does not adversely affect the refresh cycle for the dram 39 s in the memory array 8 in this way the operations that are scanned in during the standby mode may be executed in the step mode one step at a time or in a short sequence of steps thus for performing single step or short sequence scanning operations the entire scanning process involves shuttling between the standby mode to scan in a normal operation or sequence of operations transferring to the step mode to execute the operations and transferring back to the standby mode to scan out the result in the discussion of the preferred embodiment of the invention below the mode switching order is described with specific constraints to insure data integrity in the dram 39 s used in the memory modules of the array 8 although this order is preferred for the described implementation the present invention can be adapted to another order of mode switching or mode switching with a different number of modes according to design requirements in the preferred embodiment there are four mode switching operations that are made to implement the present invention these mode switching operations are standby to step step to standby step to normal and normal to step from system power on to normal system operation the mode switching order is standby to step followed by step to normal from normal system operation to standby such as required for battery backup during power loss or during scanning the mode switching order is normal to step followed by step to standby from normal system operation to an operation that allows the system clocks to stop the mode switching order is normal to step and step.