processor 108 the second microcode patch 126 comprises a dummy or disabling microcode patch that causes the processors 106 and 108 to become disabled and nonfunctional or cause them to operate in a reduced operational state e g may not be able to perform all tasks a fully operational processor can perform as part of cod server 140 although the microcode patches 124 and 126 are shown loaded in the rom they could be located anywhere and associated with their respective processors as an illustrative example the microcode patch s could be located in memory 116 or provided remotely via cod availability controller 114 or some other remote location in the case the availability status of a processor 102 108 changes while cod server 140 is already booted and operational the cod server 140 would need to be reset or power cycled in order for all of the processors to reboot and the proper microcode patch to become loaded the actual contents of the microcode patch 126 can vary and can also depend on the particular system design requirements in the case where one of the processors 102 108 for example processor 108 includes a plurality of separate processor cores 142 and 144 each individual processor core logical processor that is not supposed to be active gets loaded with the second microcode patch 126 and thus each logical processor can be disabled individually by using the disabling microcode patch 126 as an.