approximately 50 kev and implantation dose ranging from approximately 1 u00d7 10 15 ions cm 2 to approximately 1 u00d7 10 16 ions cm 2 thereafter although not illustrated another inter layer insulation layer is formed on the passivation layer 30 and a typical bit line formation process and a capacitor formation process are carried out in accordance with the first embodiment of the present invention the passivation layer 30 doped with a high concentration of the n type dopant capable of capturing hydrogen ions is formed on top of the oxide based spacer 26 through which the hydrogen ions generated during the formation of said another inter layer insulation layer diffuse because of the existence of the passivation layer 30 it is possible to prevent hydrogen ions from diffusing into a channel region fig3 a and 3b are cross sectional views illustrating a method for fabricating a dram device in accordance with a second embodiment of the present invention referring to fig3 a a device isolation layer 41 is formed in a substrate 40 thereby defining an active region a gate oxide layer 43 and a conductive material 44 including polysilicon and or a metal for use in a gate structure are sequentially formed on the above resulting substrate structure a nitride layer 45 for forming a hard mask is formed on top of.