decoders 32 1 to 32 k in each block each memory cell array 31 1 to 31 k erase gates of a plurality of memory cells are commonly connected and the commonly connected erase gate are connected to the corresponding one of the erase lines el1 to elk erase decoders 44 1 to 44 k are used to select a corresponding one of the erase lines el1 to elk in each block drains of a plurality of memory cells 30 in the same column are connected to a same common drain 43 this common drain 43 is connected via the corresponding one of array select transistors 42 1 to 42 n to the corresponding one of data lines dl1 to dln gates of each of these block select transistors 42 1 to 42 n are connected to the corresponding one of block select lines bsl1 to bslk each of these select lines bsl1 to bslk is connected to the corresponding one of block select decoders 45 1 to 45 k the other structure is substantially the same as that shown in fig1 the description will be directed to the case where the block of the memory cell array 31 1 is erased in this case first the erase decoder 44 1 is selected so that an erase voltage v eg about 20 v is applied to the erase line el1 the other erase decoders 44 2 to 44 k are not selected so the erase lines el2 to elk are set.