connected via respective pulling up resistors pr11 pr1n with respective voltage sources vcc for respectively supplying voltage vcc in this embodiment vcc 5 u00b1 0 25 v the voltage vcc corresponds to a logical level h diodes da1 dan are respectively connected between the respective drains of the fets 11 1n and the signal line ll in these connections the forward directions of the diodes da1 dan are respectively those from the signal line ll to the respective fets 11 1n further the devices dv1 dvn respectively have receiver units the receiver units are respectively used for inputting data rd1 rdn from the signal line ll the receiver units of the devices dv1 dvn respectively comprise inverters iv1 ivn each of the inverters iv1 ivn comprises two combined fets as shown in fig1 each two combined fets comprise a p channel complementary metal oxide semiconductor p channel cmos transistor the source and substrate of which are respectively connected to the voltage source vcc and an n channel complementary metal oxide semiconductor n channel cmos transistor the source and substrate of which are respectively grounded both the drains of each two combined fets are connected with each other and provide received data rd1 the input ends of the inverters iv1 ivn are respectively connected via.