another part of the circuit the pulse divider circuit 26 will produce on its output line 26a thereof pulses which are spaced apart time intervals equal to the basic programmable time interval of the timer system which is 15 minutes in one embodiment of the invention the output line 26a extends to the input of a self resetting pulse counter 109 which resets itself automatically to zero count when receiving a number of pulses representing a 24 hour period it will be assumed that any gate circuit shown in the drawings will be opened when it receives on its control terminal a 34 1 34 binary signal and will be closed when it receives a 34 0 34 binary signal the pulse counter 109 has an output terminal 109b which has a normal 34 0 34 binary voltage state which changes to a 34 1 34 binary voltage state when the pulse counter reaches its maximum count the pulse counter 109 i e every 24 hours will provide a 34 1 34 binary output state every 96 pulses when the pulse divider circuit output produces pulses 15 minutes apart a line 110 interconnects the pulse counter output terminal 109b and the 34 s 34 terminal of.