st 2 and st 3 are coupled between the data line dl and the display cell p 2 between the data line dl and the display cell p 4 and between the data line dl and the display cell p 6 respectively as shown the display cell p 1 comprises a transistor m 1 and a capacitor cs 1 the display cell p 2 comprises a transistor m 2 and a capacitor cs 2 and the display cells p 3 u02dc p 6 are similar to the display cells p 1 and p 2 gates of the transistor m 1 m 3 and m 5 are coupled to the scan lines sl 1 sl 2 and sl 3 respectively drains of which are coupled to the data line dl and sources of which are coupled to capacitors cs 1 cs 3 and cs 5 respectively gates of the transistors m 2 m 4 and m 6 are coupled to the scan lines sl 1 sl 2 and sl 3 respectively drains of which are coupled to the data line dl and sources of which are coupled to capacitors cs 2 cs 4 and cs 6 respectively the switches st 1 u02dc st 3 are formed by transistors m 7 u02dc m 9 gates of the transistors m 7 u02dc m 9 are coupled to the auxiliary signals sw.