inversion code as the pulse train of the receiving signal the timing phase detector circuit of this invention can specifically be implemented as shown in fig2 in the alternative mark inversion code representative of the pulse train used in this implementation 34 1 34 and 34 1 34 of a ternary signal represented by 34 1 0 1 34 occur alternately therefore the pulse train is passed through the equalizer 2 to the decision circuit 3 which in this implementation specifically decides which of 34 1 34 34 0 34 and 34 1 34 the pulse of the pulse train assumes the decision circuit 3 includes two comparators 11 1 and 11 2 respectively having thresholds of u00b1 0 5v relative to a signal amplitude of 1 0v an exclusive or gate 12 an inverter 13 and shift registers 14 1 and 14 2 having a latch function when the alternative mark inversion code is 1 a digital signal of 34 1 34 is produced from the shift register 14 1 in synchronism with an internal clock clk 1 similarly a 34 1 34 digital signal is obtained from the shift register 14 2 in timed relationship with the clock clk 1 when the alternative mark inversion code is 0 zero thus the decision circuit 3 has the function of data decision and an additional function of bipolar unipolar conversion from alternative mark inversion code to nrz code the pattern selector 4 includes shift registers 14 3 to 14 9 and a logical multiplier and circuit 6 3 and produces an output signal of 34 1 34 at the output of the multiplier 6 3 only when the data pattern assumes a specified pattern of.