variations of several per cent are typically specified for power supplies it will also be understood by those skilled in the art that to avoid forward biasing the p s d junctions of pfets 306 310 both of these pfets have well voltages equal to or greater than their source voltages in other words with reference to fig3 vperiphery must be approximately equal to or greater than vcore similarly to prevent forward biasing of the p junctions coupled to output node 312 vperiphery must be approximately equal to or greater than the highest voltage expected at output node 312 pull up pfet 306 is active in both 3 3 volt and 5 volt switching environments pull up pfet 306 is a current source in this circuit additional pull up pfet 310 which is typically made from several legs is controlled by nfet 308 which is connected in series between pull up pfet 310 and the 3 3 volt power supply as described above the gate of nfet 308 is electrically connected to vperiphery that is the same voltage used for biasing the n wells in which pfets 306 308 reside pull up pfet 310 together with nfet 308 also form a current source in this circuit in a 5 volt.