at which the host cpu 210 stores the next drawing commands must be in a region totally irrelevant to the previous transfer the host cpu 210 repeats the processing in steps s 215 and s 216 until there is no need to generate drawing commands intended to be transferred next processing in steps s 231 to s 238 in fig1 is substantially the same as the processing in steps s 71 to s 78 described with reference to fig8 and thus the description thereof is omitted here in step s 239 when the drawing section 232 receives a drawing end instruction or determines that all transferred drawing commands have been processed the drawing section 232 outputs the done signal ds to the dma controller 234 to complete the drawing processing and waits for input of a new drawing commands after completion of data transfer from the main memory in step s 236 the dma controller 234 examines the interrupt permit flag in the control register 235 set by the host cpu 210 in step s 241 if the interrupt permit flag is in the asserted state the dma controller 234 generates and outputs the interrupt signal is to the host cpu 210 and then negates the interrupt permit flag in step s 242 the host cpu 210 uses the timing of the interrupt signal is as the timing at which the next data is transferred or generated thereby transferring the next drawing data to the main memory 20 or generating drawing data to be next transferred in step s 221 in fig1 the host cpu 210 determines whether or not it is necessary to generate.