when an external circuit 512 513 fig5 senses a power down signal it forces the en signal to be high first and then pulses the signal pl on plate line 329 when en is high transistors 322 323 and 324 are turned on so that the voltage between node 109 and plate line 329 will drop across capacitor 312 and the voltage between node 110 and the plate line 329 will drop across capacitor 314 this causes the data on nodes 109 and 110 to be stored on capacitors 312 and 314 respectively as known in the art the signals stored on capacitors 312 and 314 are complementary that is if one is high the other is low and vice versa just before or at the same time that the power is completely down the en signal returns low and ferroelectric capacitors 312 and 314 hold the data via their remnant ferroelectric polarization when the external circuit senses a power up signal it forces the en signal to be high first and then pulses the signal pl on plate line 329 because capacitors 312 and 314 have different polarizations nodes 109 and 110 will be at different voltages which depend on the capacitance ratio of capacitors 312 or 314 to the capacitances connected to nodes 109 or 110 respectively after v sup becomes high this voltage difference will be enlarged so that the lower voltage becomes data.