the conductive structures act as gate electrodes of the transistors parts of the insulation i 2 which are arranged on the second sidewalls of the depressions v act as a gate dielectric of the transistors parts of the substrate 1 which are arranged between the lower source drain regions s du and the upper source drain regions s do act as channel regions ka of the transistors the conductive structures act as bit lines the conductive structures are buried in the substrate 1 and are connected to regions of the substrate 1 namely to the lower source drain regions s du storage capacitors are subsequently produced the capacitors are each connected to an upper source drain region s do of the transistors a memory cell of the dram cell configuration produced by the method described comprises one of the transistors and one of the capacitors connected to the transistor in a second exemplary embodiment a second substrate 2 made of monocrystalline silicon is provided an n doped layer p u2032 having a thickness of approximately 7 u03bcm is arranged approximately 1 u03bcm below a surface of the substrate 2 as in the first exemplary embodiment a mask comprising a first oxide layer o 1 u2032 is produced on a nitride layer and a.