cell 50 is shown memory cell 50 is coupled to word line 52 and to bit line pair 54 bit line equalization block 18 receives signal eq from address buffer decoder 25 and is coupled to each of 128 bit line pairs of memory array 12 column logic decoder 16 receives a column address c0 c1 c2 and c3 wbi and csi column logic decoder 16 is coupled to each bit line pair including representative bit line pair 54 and is coupled to global data line pair 30 and write global data line pair 40 data i o circuit 20 receives signals gdl0 and gdl0 on global data line pair 30 wb cs and input output signals d0 d1 d2 d3 d4 d5 d6 and d7 and provides signals wbi csi and wgdl0 and wgdl0 on write global data line pair 40 in a preferred embodiment memory 10 is configured as a u00d7 8 memory however memory 10 could also be configured as u00d7 4 or a u00d7 1 memory signals gdl0 gdl0 wgdl0 and gdl0 represent signals for data bit d0 other corresponding signals for data bits d1 d7 are not shown for ease of illustration similarly the seven other global data line pairs and write global data line pairs are also not shown address buffer decoder 25 receives enough address bits to select one of 32 blocks it should be apparent that different 93numbers of blocks different sizes of blocks and different organizations could be used in basic operation address buffer decoder 25 receives an address on.