combined and both proceed to the second input of the multiplexer 140 third the control circuit 124 issues an address select signal to the multiplexer 140 to command the multiplexer to select data appearing at its second input instead of data appearing at its first input as is the normal operating mode without an error indication the third function of the control circuit 124 essentially substitutes the corrected parity data 122 for the original parity data 120 after the corrected parity data 122 has been associated with the data word 116 for which it had been generated thereafter the data word 116 and the corrected parity data 122 proceed normally along data path 150 to the ram data register 106 where it is temporarily stored when the alu 110 is ready to process the data word 116 the data word 116 and the corrected parity word 122 are accessed from the ram data register 106 the data word 116 is input and processed by the alu 110 while the parity checker 100 tests the data word 116 against its corrected parity data 122 the test will indicate that the data is good therefore the control circuit 124 will now unpause the destination registers downstream from data path 132 the alu 110 will be allowed to process the data word 116 and the multiplexer 140 will once again select data appearing on data path 146 to output to the ram data register 106 the alu 110 will execute its instructions upon the data word 116 and the output will proceed downstream to destination.