pre charging driver 14 a for the preceding data segment is a simple pmos transistor and a weak keeper 12 a to hold the data line high as shown in fig1 and 3 the pre charging control circuit 16 a that controls the pre charging driver 14 a produces a low signal when both en i and d i are low when the preceding segment is charged i e d i becomes high the pre charging signal goes high and the data line is held high by the weak keeper 12 a unlike previous work the widths of the en i and pre charge pulses are automatically set by the timing behavior of the data lines and need no special circuit sizing spice simulations using a 0 13 pm 1 2 v cmos technology were used to verify the operation of the new transceiver circuits fig6 shows the test setup that is a pipeline 600 consisting of three stages of asynchronous transceivers a data producer and a data consumer wire segments in between are modeled using lumped rc circuits that approximately represent 100 u03bcm wires transistors were sized to achieve 50 ps fall times and 100 ps rise times no further optimization was carried out to illustrate the robustness of the circuits fig7 shows the simulation waveforms.