dynamic clock change for the processor during audio playback can be achieved if the processor clock is decoupled with dac dma 311 309 clock the clock domain grouping number of sets of clock frequencies and isolation is not necessarily required as shown in fig3 fig4 shows a block diagram of the present invention the compressed uncompressed stream 401 is transferred in small chunks from external memory to on chip memory the decoder program 402 decodes the compressed data streaming buffers 403 in on chip memory if the stream is uncompressed such as linear pcm in wav format the decoding operation would be simple streaming or data pass through the input stream buffer 401 is refilled for consumed data for next frame decode the decode data is processed by post processing module 404 in the simplest configuration the post processing module can be an src an src is essential to insure that the fade in and fade out streams are converted to the same sample rate before passing the audio streams on to xfc cross fade controller 15 the post processed data is available for streaming in buffers 405 in the on chip memory the switch 406 controls the streaming data to either switch 407 or 410 the odd numbered streams are passed onto switch 407 and even numbered streams are passed onto switch 410 the first stream is odd and every subsequent stream alternates between even and odd the stream here refers to the streams for cross.