being offset in time by half a clock period both signals risingedge and fallingedge are supplied to the inputs of the logical or gate og which forms from these the divided output signal clkdiv 5 by means of a logical or operation on the signals risingedge and fallingedge due to the time offset of the signals risingedge and fallingedge the output clock signal clkdiv 5 generated by the logical or operation on them stays in the logic state of 1 for 2 u00bd clock periods and in the logic state of 0 also for 2 u00bd clock periods and thus has a pulse duty factor of 1 1 the frequency divider circuit ft can be configured in a simple manner for generating output clock signals having other divider ratios and or other pulse duty factors by storing a different counter end value in the counter end value register zer and or other counter start values in the counter start register zar thus storing a binary counter end value of 111 in the counter end value register zer and the counter start values remaining 01 or respectively 10 produces a frequency division of the input clock signal clkref with the dividing ratio of 13 the output clock signal generated in this case also has a pulse duty factor of 1 1 in general the frequency divider circuit ft of the present exemplary embodiment divides the frequency of an input clock signal clkref by an odd divider ratio t which is given by t 2 ze u2212 1 with a counter end value of ze and the counter start values of 01 and 10 the pulse duty factor of each respective output clock signal is 1 1 in the text which follows an actual embodiment of a frequency divider circuit according.