u2212 v src drain gate voltage v dg v on u2212 v p and drain body voltage v db v on u2212 v src can all become vtt u2212 0 volts if the node v src isn 39 t set by a voltage buffer and goes to zero volts this would be an issue when vtt is greater than the voltage allowed for the t 0 element which can occur in a high swing driver in recent cmos technologies the presence of the coupling circuit and biasing circuit of this invention protects against the degradation of the semiconductor elements which would occur where this voltage difference is imposed during a power down sequence in particular the apparatus of this invention has a differential amplifier circuit as described and illustrated connected to the amplifier circuit are a biasing circuit and a coupling circuit the coupling circuit recognizes a powering down event for the differential amplifier and applies a biasing voltage from the biasing circuit to the differential amplifier circuit during the recognized powering down event the biasing voltage protecting the differential amplifier circuit against degradation otherwise possible due to voltages imposed during the powering down event during a powering down event the current flowing through the resistors r 0 and r 1 goes to zero thus there is no voltage drop across the resistors and voltage v op v on v tt absent the intervention of this invention the biasing voltage is applied through a buffer and may be derived in a number of differing ways what is shown is exemplary only as it is recognized.