may be made without departing from the spirit or scope of the invention the term u201c substrate u201d used in the following description may include any supporting structure including but not limited to a semiconductor substrate that has an exposed substrate surface a semiconductor substrate should be understood to include silicon on insulator soi silicon on sapphire sos doped and undoped semiconductors epitaxial layers of silicon supported by a base semiconductor foundation and other semiconductor structures when reference is made to a semiconductor substrate or wafer in the following description previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation the substrate need not be semiconductor based but may be any support structure suitable for supporting an integrated circuit the term u201c resistance variable material u201d is intended to include chalcogenide glasses and chalcogenide glasses comprising a metal such as silver for instance the term u201c resistance variable material u201d includes silver doped chalcogenide glasses silver germanium selenide glasses and chalcogenide glass comprising a silver selenide layer the term u201c resistance variable memory element u201d is intended to include any memory element including programmable conductor memory elements semi volatile memory elements and non volatile memory elements which exhibit a resistance change in response to an applied voltage the term u201c chalcogenide glass u201d is intended to include glasses that comprise an element from group via or group 16 of the periodic table group via elements also referred to as chalcogens include sulfur s selenium se tellurium te polonium po and oxygen o the invention is now explained with reference to the figures which illustrate exemplary embodiments and where like reference numbers indicate like features fig1 shows array and peripheral circuitry portions of.