a increases at a slower rate than the voltage on node b or gate 310 asserts an enable signal to comparator 312 when the voltage at b exceeds logical high at this point in time and thereafter the voltage at node b exceeds the voltage at node a and the output of comparator 312 is not asserted such a condition indicates that passivation material 112 is present between and around the elements of capacitor 306 fig5 shows an embodiment of voltage over time when passivation material 112 has been stripped from between and or around the elements 116 and 118 of capacitor 306 note that not all passivation material 112 may be removed rather portions of passivation material 112 may be removed from around and or between the elements 116 and 118 of capacitor 306 this may occur as a result of physical tampering with circuit 100 in an attempt to access internal components when the voltage level on node a exceeds logical high or gate 310 enables comparator 312 voltage at node a exceeds the voltage at node b which causes comparator to assert its output signal 314 this condition indicates that passivation material 112 has been removed from around and or between elements 116 and 118 this condition may indicate tampering signal 314 may be employed to disable one or more circuit operations and thus prevent a party responsible for the tampering from obtaining information about internal operations of the circuit elements 116 and 118 may be positioned within circuit 100 such that it may be difficult for a party tampering.