2 simms on this net if only 9 loads on 1 simm are on a chip select net it is likely that termination resistors as described in fig1 are required to prevent excessive ringing these termination resistors could be placed on the simm since the cs lines are not used if the simm is not present fig1 shows the resultant simulated waveform as measured at the sdram there are two unique position for the sdrams and both are shown as expected they are very similar this signal could probably be run faster 100 mhz without difficulty even though it is a single cycle signal to economize of the number of buffers and to make a compact system signals which need only be valid after 2 cycles have more srams assigned to them fig1 shows a preferred topological arrangement of address control buffers transmission lines and sdram address control receivers it follows closely from the cs nets this time sdrams on both the front and back surface are connected together and the center of a group of 3 sdrams this is our preferred topology and can be accomplished with the same via that connects the top surface wiring to the internal surface again the impedance and wire lengths correspond to the memory card of fig1 fig1 shows the resultant address pulse measured at the sdrams for the 2 unique.