the waveform labeled wl one of wl 0 and wl 1 as seen in fig2 the high value on a word line causes all the access transistors of all the memory cells of the associated row of sixteen memory cells to be conductive one entire sixteen bit value is output from the array 2 to the eight column multiplexer demultiplexers the eight column multiplexers 3 10 select one eight bit value to be output onto the data output leads of the memory based on the value of the read address values rca 0 and rca 0 n the differential voltages on selected pairs of bit lines are coupled through the multiplexers of the column multiplexer demultiplexers and onto the input leads of the sense amplifiers of the column multiplexer demultiplexers the resulting eight bit value is output onto the output leads 60 67 of the memory device 1 the outputting of the eight bit data value is illustrated in fig7 at time t 2 in the waveform labeled dout 7 0 read returning to fig6 a one shot circuit 105 detects the low to high transition of the signal iclk after a delay one shot circuit 105 outputs a high pulse of a reset signal this is illustrated in fig7 by the first high pulse in the waveform labeled reset in fig7 the dashed arrow labeled a represents the delay introduced by one shot circuit 105 reset pulsing high causes rclk to transition low because the high value of reset is present on the upper input lead of nand gate 106 of fig6 rdwclk is a digital low so a digital high is also present on the lower input lead of nand gate 106 nand gate 106 therefore outputs a digital low signal thereby causing.