is read from the memory module 110 b when the second synchronization pulse 111 b appears the read mode thus described continues until the last data burst 110 n of the data stream 112 is read from the last parallel connected memory module 105 n when the last synchronization pulse 111 n appears the staggering of the synchronization pulses 111 a u2013 111 n of the synchronization signal 111 over time assembles as illustrated at the bottom of fig2 a data stream 112 comprising the data bursts d 1 a u2013 d 8 a or generally the data bursts 110 a u2013 110 n and allows it to be read via the data bus 110 in the present invention 39 s exemplary embodiment shown in fig1 the inventive sequence of the synchronization pulses 111 a u2013 111 n staggered over time in line with the individual data bursts 110 a u2013 110 n is produced by virtue of the first memory module 105 a being supplied with a first synchronization pulse 111 a of the synchronization signal 111 sync 0 while the rest of the synchronization pulses 111 b u2013 111 n are derived successively from the respective preceding memory module 105 a u2013 105 n this means that when a specific data burst 110 i has been read from the appropriate memory module 105 i a subsequent rising clock edge 102 a of the clock signal 102 generates a synchronization signal 111 i 1 which prompts the.