word line wl coupled to a word line transistor 510 a storage element 520 which can be an mtj storage element as described herein is represented as a simple resistance the transistor 510 and storage element 520 are disposed between a bit line bl and a source line sl during various operations associated with access states such as memory read and write states the write line source line and bit line can be set to and can achieve various levels for example the wl bl and sl can be capable of achieving a h level an l level a floating level f and a v thp u2014 lv level as used herein h is a high voltage or logic level l is a low voltage or logic level f is a floating level that would be achieved due to a high impedance state at the node with respect to a reference and v thp u2014 lv is a level associated with a pre charge threshold voltage level the h and l voltage or logic levels may be supply and reference voltage levels such as vcc and vref or 0v or may be higher or lower than the supply voltages levels.