gate electrode for forming an ldd lightly doped drain structure in source and drain regions of the transistor lightly doped n type ldd regions are formed in the semiconductor substrate corresponding to both sides of the gate electrode then a teos oxide layer or a nitride layer is deposited by lpcvd and is then anisotropically etched to form spacers at both sidewalls of the gate electrode also a highly doped n type diffusion region is formed in the semiconductor substrate the teos oxide layer not shown is formed at a thickness of about 1000 u00e5 by lpcvd and a bpsg layer not shown is formed on the teos oxide layer by hpcvd then a first metal dielectric layer is formed by flowing the bpsg layer by selectively etching the first metal dielectric layer a contact hole is formed to expose the highly doped n type diffusion region and the gate electrode after forming a first glue layer of titanium ti a first aluminum layer for line formation is formed on the first glue layer then a first titanium nitride layer having a non reflective property is formed on the first aluminum layer then the first glue layer the first aluminum layer and the first titanium nitride layer are selectively etched to form a first metal line then a contact hole is etched by plasma subsequently a first teos oxide layer and a first sog spin on glass oxide layer are sequentially coated by pecvd plasma enhanced chemical vapor deposition and then a heat treatment and a planarization.