i and likewise for uf i and uf 512 for different values of n and i requiring different numbers of passes to accomplish the division note that of i and uf i are sampled only in pass 2 the reciprocal correction step and the quotient generation step fig6 shows structures which may be used together with the structures in fig1 to permit the division of 60 bit integers using the same technique as described earlier for floating point numbers the shifter 624 is used to convert the original integer dividend and divisor to binary fractions and to convert the final quotient from binary fraction form to integer form the shift counts replace the characteristics or exponents used with floating point numbers it will be assumed that no room remains in the storage registers 110 for these shift counts so separate storage is provided by the count reg 612 two passes through the shifter 624 are required to convert the dividend and divisor both to fractional form each of these passes will now be described in detail in the first pass the integer divisor b is presented to input in 610 this input is applied to both a normalize count generator 614 and the shifter 624 the norm count gen 614 produces a normalize count whose value is equal to the number of left shifts required to normalize in 610 this count may be between 0 and 59 inclusive inputs of zero will cause a final result of zero or division by zero and may safely produce an arbitrary normalize count field 0 for each of selectors 618 620 and 622 is selected the shifter 624 is in leftshift mode adder 628 is in subtract a.