the layout it is sufficient to place the inversion diffusion layer 3 provided on the substrate nwell 1 only between the substrates pwell 2 and nwell 1 the same shall apply to the case where a protective circuit 22 shown in fig2 is used for the latch up prevention to further improve the area efficiency of the layout it is sufficient to provide the protective circuit 22 only between the substrates pwell 2 and nwell 1 the same effects are achievable not only by a dynamic circuit as shown in fig1 but also by a circuit formed of a high resistance element which is provided on the nwell 1 in place of the pmos transistor the high resistance element is implemented by using the polysilicon 2 or the diffused layer 1 when the respective gates oxide films of the mos transistor formed on the substrate pwell 1 and the mos transistor formed on the substrate pwell 2 have different thicknesses or are made of different materials a structure in which the number of series connected mos transistors is large is adopted in other words a mos transistor with a large gate leakage current is selected as each of the mos transistors formed on the substrate pwell 2 when the mos transistor formed on the substrate pwell 1 and the mos transistor formed on the substrate pwell 2 have different thresholds a structure in which the number of series connected mos transistors is large is adopted in other words a mos.