the circuit of fig2 in accordance with the principles of the present invention does not provide a matching of the input impedance z e to the output impedance z o of the preceding stage but rather halves the noise optimum source impedance from approximately 100 ohm to approximately 50 ohm referring to fig3 real transistors represent noise sources that are viewed as ideal noise free transistors in the equivalent circuit in front of whose base terminals b 3 b 4 noise voltage sources u n3 u n4 are disposed noise current sources i n3 i n4 connect the base circuit to the emitter circuit the influence of the parallel circuit and the two transistors t 3 and t 4 on the noise behavior is described with reference to fig3 the signal to noise ratio for an individual transistor for example transistor t 3 is greatest when the source impedance is selected at equ5 where the value of the source impedance z o is defined here as the noise optimum source impedance z o opt defined by the noise source u n and the noise current source i n is approximately 100 ohms an analysis of the signal to noise ratio for the parallel circuit of fig3 produces the result for the signal part i as in the output current i a where s is the steepness of transistor t 3 or t 4 u o is the voltage and p o is the power of the signal source when all noise sources u n and i n are negligible correlated the noise parts i an in the output current i a is defined by the signal to.