one another by the shallow trench isolation further a shallow trench isolation 43 is present on the insulation 24 subsequently the silicon nitride layer 3 and the silicon oxide layer 2 are removed and a thin silicon oxide layer is generated that is employed as thin scattering oxide layer during the ion implantation that now follows what is referred to as an n well 15 is generated in the second region 33 of the substrate by the ion implantation later the p channel transistors are arranged in this n well 15 the insulation 24 thereby separates the n well 15 from the surrounding substrate 1 what is referred to as a p well 14 is generated in the first region 31 of the substrate by a further ion implantation subsequently the thin silicon oxide layer is removed so that a further silicon oxide layer u2014 what is referred to as the gate oxide not shown u2014 can be generated on the surface of the substrate a layer of polysilicon 18 is deposited onto the gate oxide and a metal silicide layer 19 for reducing the resistance is in turn deposited on said layer of polysilicon 18 the metal silicide layer 19 and the silicon layer 18 are structured in order to generate what are referred to as the gate tracks the transistors 25 26 and 28 are finished by the subsequent ion implantation of arsenic or respectively boron the structure resulting from these steps is shown in fig1 in a plan view fig1 schematically shows the structure of the semiconductor component manufactured in.