high speed complex logic is not desirable so use of subtraction as one of the count modes shown in table 1 above for the counter state machine 308 is not desirable as a substitute the counter 508 is delayed by one cycle for example about 0 64 ns so that the offset allows the post processing arithmetic or count modes to be 1 2 and 3 instead of u2212 1 0 and 1 respectively which is shown in table 2 below for count mode of 2 the or gate 602 outputs a logic high signal through and gate 604 to d flip flop 608 which then outputs the adj signal to the or gate 614 of counter 508 as a result incrementer 616 of counter 508 is able to increment for one additional cycle for the count mode of 1 the xor gate outputs a logic high signal to flip flops 610 and 612 to reflect a u201c 1 u201d in the 0 th bit cnt 0 finally for a count mode of 3 the incrementer 616 increments for an additional cycle and a u201c 1 u201d is indicated in the o th bit cnt 0 as a result of using timing circuit 300 several advantages can be realized for example a latency measurement accuracy of 651 ps which is 20 times better than current cpri obsai systems additionally because the amount of high speed circuit has been reduced the overall power consumption can be reduced also because there can be a single bit data transfer from a low speed clock domain to a high speed clock domain the likelihood of detecting a.