connected via a first and second coupling capacitor c1 c2 to the input e and to the output of the delay section u03c4 respectively the inputs of the second stage of the first differential amplifier and of the first stage of the second differential amplifier are connected to the input a while the input of the first stage of the third differential amplifier is connected to the input b the inputs of the second stage of the first differential amplifier and of the first stage of the second differential amplifier are connected via the fifth resistor r5 and the inputs of the first stage of the first differential amplifier via the seventh resistor r7 to the first reference voltage source ur1 so that without signal all stages contain the same bits the capacitor c3 inserted between the reference potential and the second stage input of the second differential amplifier serves to short circuit the resistor r7 ac wise the first stage of the third differential amplifier is connected via the resistor r6 and the second stage of the third differential amplifier is connected via the resistor r8 to the second reference voltage ur2 in addition a blocking capacitor c2 is provided between the input of the second stage of the third differential amplifier and the reference potential thus without signal the inputs of the two stages of the third differential amplifier are also at the same potential in view of the cascade connection of the three differential amplifiers the potential of the second reference voltage source ur2 is more negative than the potential of the first reference voltage source ur1 a second integrated circuit ic2 wired as a current mirror as known in the art and connected to the.