s that reside between the first 205 a 205 b and second 206 a 206 b inverters 0030 fig2 b corresponds to an embodiment of a transistor level design for the level shifting approach of fig2 a referring to fig2 b note that a higher transistor gain corresponds to larger transistor current magnitude e g where transistor gain corresponds to transistor transconductance as measured by output ids current per input vgs voltage as such in order to achieve small rise and fall times at the first inverter 205 a 205 b output the transistors q 5 and q 6 that drive the first inverter 205 b output may be designed with a larger gain e g transconductance than that associated with the transistors q 2 and q 4 within the level shifter 201 a b the second inverter 206 a b provides the logical inverse of the first inverter output signal 205 c and in so doing effectively provides the logical values originally presented by the level shifter output signal 204 c that is the logical inversion provided by the first inverter 205 a b is effectively reversed so that the output signal out 207 c corresponds to a level shifted version of the non inverted input signal in 202 c the small rise and fall times achieved with the first inverter 205 a b may be rippled through.