0016 fig1 is a schematic block diagram of a dram cell configuration 5 in accordance with an embodiment of the present invention the dram cell 5 includes a pass transistor 10 and a storage transistor 20 the pass transistor 10 acts as a pass gate to enable reading and writing of a data bit a data bit line 14 connects to the source node 11 of the pass transistor 10 a read write enable line connects to the gate node 12 of the pass transistor 10 a storage node 100 is formed by the connection of the drain node 13 of the pass transistor 10 and the drain node 21 of the storage transistor 20 a bias voltage is applied to the gate node 22 of the storage transistor 20 the source node 23 of the storage transistor 20 is left floating the capacitance associated with the storage transistor 20 allows the storage transistor 20 to act as a storage device for a data bit by sharing the drain nodes between the pass transistor 10 and the storage transistor 20 the space available for the storage node may be increased when the dram cell is implemented on a chip using embedded cmos technology as a result the effective storage capacitance is increased fig1 a.