the data is received by the memory device 400 over the dq lines 460 the data is provided to the memory cells in the array 410 from the dq lines 460 through the i o circuitry 440 data is read from the memory cells in the array 410 when the write enable signal is high and the output enable signal and the chip enable signal are both low the antifuse circuit 100 may be used in the memory device 400 for configuring the memory array 410 for example defective memory cells may be replaced with redundant cells by programming certain antifuse transistors 110 as is well known in the art the antifuse circuit 100 may be integrated with the memory array 410 or may be a separate circuit on the memory device 400 a block diagram of an information handling system 500 is shown in fig5 according to yet another embodiment of the present invention the information handling system 500 includes a memory system 510 a processor 520 a display unit 530 and an i o subsystem 540 the processor 520 the display unit 530 the i o subsystem 540 and the memory system 510 are coupled together by a suitable communication line or bus 550 over which signals are exchanged between them the processor 520 may be for example a microprocessor one or more of the memory system 510 the processor 520 the display unit 530 and the i o subsystem 540 may include one or more of the circuits and devices described above with respect to fig1 4 according to embodiments of the present invention the particular embodiments disclosed above are.