the device layer 906 and electrically connected to the device layer 906 where the anchor 910 is electrically isolated by trenches or vias 912 each via 912 includes a core 916 formed of a non monocrystalline conducting material and electrically insulated by a dielectric layer 914 the asic wafer 902 includes planarized poly insulator electrodes for driving and sensing mems structures formed in the device layer 906 the asic wafer 902 also includes diffused hermetic underpasses under the bond 904 to handle high level signals fig1 shows the via cap wafer 908 of fig9 where the via wafer 908 is fabricated by processing a flat dsp wafer via the steps described in conjunction with fig2 d 2j with the difference that the via wafer 908 may not include any marker mask 210 fig2 c as such the process for fabricating the via wafer 908 is not repeated for brevity fig1 a 11b show a process for fabricating the device layer 906 of fig9 in accordance with another embodiment of the present invention as depicted in fig1 a a standard silicon wafer 1102 is fusion bonded such as silicon silicon fusion bond to the via wafer 908 then the silicon wafer 1102 may be ground to the thickness of 60 u03bcm and polished by cmp technique it is noted that a silicon on insulator soi vendor could supply a wafer 1102 that is processes to this stage then a bond metal layer 1106 may be deposited and patterned on the wafer 1102 note that the bond metal layer 1106 is needed if the bond 904 between the asic wafer 902 shown in fig9 and.