to 3d this invention further discloses a method for manufacturing a power transistor 100 on a substrate 105 the method includes the steps of a forming an initial oxide layer 188 on a top surface of the substrate and etching away the initial oxide layer to define an active area 140 for manufacturing a plurality of transistor cells thereon b growing a gate oxide layer 120 in the active area followed by depositing a polycrystalline silicon gate layer 130 thereon and c applying a polysilicon gate mask 128 for patterning a plurality of gates for each of the transistor cells and an edge wrap around polysilicon extension layer extended from the gates 130 wherein the edge wrap around polysilicon extension layer is patterned to cover the initial oxide layer 188 and extended over edges of the initial oxide layer 188 to wrap around and cover edges of the initial oxide layer whereby structural damages on edges of the initial oxide layer are reduced in a preferred embodiment the step of patterning the edge wrap around polycrystalline silicon extension layer to wrap around edges of the initial oxide layer is a step of controlling a width of the gate oxide layer u03b1 formed next to the initial oxide layer 188 padded underneath the polycrystalline silicon extension layer 130 to be shorter than a lateral diffusion length of a body dopant d l provided for forming a body region 115 having a portion diffused underneath.