causing a logic high output of bit line driver circuit 10 to appear on the interconnected drains of pmos transistor 40 and nmos transistor 45 to activate bit line 50 to a logic low state signals bitpub and bitpd are both high causing a logic low output of bit line driver circuit 10 to appear on the interconnected drains of pmos transistor 40 and nmos transistor 45 finally to tri state the bit line driver 10 signal bitpub is high while signal bitpd is low causing both transistors 40 and 45 to be switched off upon activation of pmos transistor 40 or nmos transistor 45 a significant current may be quickly conducted through either transistor at the same time the voltage on bit line 50 may increase or decrease to operating levels the time required for the voltage on bit line 50 to reach operating level is known as the slew rate and may depend upon the characteristics of transistors 40 and 45 as may often be dictated by the speed requirements of the memory device unfortunately rapid slew rates often lead to sharp current spikes as illustrated in fig1 b fig1 b illustrates typical voltages and currents which may be experienced by bit line driver circuit 10 upon activation of transistors 40 and 45 this may occur for example during a write instruction in which all bit lines are activated it is apparent that as the input driver signal bitpub transitions from a high to low state transient currents i vss and i vcc are produced i vss and i.