considered especially preferred since it avoids the risks of thermal oxidation that are especially present in very small devices fig9 shows a number of layers on a substrate 50 the layers include insulator layers 52 made of an oxide for example other materials may be used such as high k gate dielectrics for example lightly doped semiconductor channel regions 54 are provided between the insulator layers 52 a gate electrode layer 56 is provided on the uppermost insulator layer 52 a hard mask layer 58 is provided on the gate electrode layer 56 as in earlier described embodiments the gate electrode layer 56 may be formed from a heavily doped silicon or silicon germanium layer and the channel layers 54 may be formed of a lightly doped silicon or silicon germanium material the conductivity types of the dopants in the gate electrode layer 56 and the channel layers 54 are of opposite types in the described exemplary embodiment for purposes of explanation and illustration the gate electrode layer 56 is considered to have been heavily doped with n type dopants while the channel layers 54 will be considered to have been lightly doped with p type dopants following the formation of the layers in fig9 a dry etching is performed to shape the gate the results of which are depicted in fig1 the gate electrode 56 a is thus created with the dry etching stopping on the gate insulator layer 52.