US 6959064 B2 abstract a multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal the phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services application_number US 73594400 A description in fig1 the digital phase locked loop pll 1 receiving a line rate input clocks received data out from receive buffer 2 the incoming atm cell stream is reassembled in reassembly engine 3 in the adaptive scheme shown in fig2 buffer fill level information is returned from the receive buffer 2 to the input of the pll 1 in the srts scheme shown in fig3 the receive srts circuit 4 recovers timing information from the incoming time stamps and provides an input to pll 1 in fig4 the line rate input is fed to transmit srts circuit 6 which generates residual time stamps to be included in the cell stream by segmentation engine 5 by including the clock recovery pll as shown in fig5 the circuit can be used to de jitter an incoming clock before it is used to generate srts time stamps and at the receiver another instance of the circuit can be used to generate the outgoing clock from the srts this is important because the sampling effects of the time stamp process alias the jitter frequencies downward where they are harder to filter for the receiver pll.