245 and the memory cell block 213 are connected by the bit lines bl 1 bl 1 bl 3 and bl 3 the memory cell block 213 the switching block 246 the sense amp block 224 the switching block 247 and the memory cell block 214 are connected by the bit lines bl 2 bl 2 bl 4 and bl 4 the memory cell block 214 the switching block 248 and the memory cell block 225 are connected by the bit lines bl 1 bl 1 bl 3 and bl 3 the controllers 271 to 274 receive the enable signal act to output the control signals bis 1 to bis 4 respectively the outputted control signal bis 1 is inverted through an inverter in 1 and transferred to the switching blocks 241 and 242 the outputted control signal bis 2 is inverted through an inverter in 2 and transferred to the switching blocks 243 and 244 the outputted control signal bis 3 is inverted through an inverter in 3 and transferred to the switching blocks 245 and 246 the outputted control signal bis 4 is inverted through an inverter in 4 and transferred to the switching blocks 247 and 248 hereinafter cases where the memory device is in an operation mode and a waiting mode will be separately described when the memory device is in the operation mode in order to designate matrix type memory cells row addresses and column addresses are applied to the memory cells through the word lines wl 1 to wl 4 and the bit lines bl 1 bl 1 bl 2 bl 2 bl 3 bl 3 bl 4 and bl 4 simultaneously the enable signal act is applied to the controller 271 to 274 then the controller 271.