bl 0 bl 1151 are wired in the wiring region 16 digit lines dq 1 dq 3 are wired in the wiring region 17 digit lines dq 4 dq 6 are wired the memory cell groups 14 and 15 have a memory capacity of 288k bits namely the respective memory capacities are increased by 32k bits 512k bits 16 more than that of the above described conventional dram see fig7 9 a c because memory cells to which parity data is to be assigned are additionally required the number of word lines is 256 wl 0 wl 255 similarly to that of the conventional device further since the memory cell groups 14 and 15 respectively have a memory capacity greater than that of the abovedescribed dram by 32k bits the number of bit line pairs is increased by 128 pairs resulting in 1152 pairs bl 0 bl 1151 in the figure respective three digit line pairs dq 1 dq 3 dq 4 dq 6 in the figure are provided in wiring regions 16 and 17 so that data can be inputted to the respective memory cell groups 14 and 15 and outputted therefrom by three bits the correspondence relationship between.