fig2 c shows a silicon nitride liner layer 120 is deposited atop the semiconductor substrate on the sidewall spacers and atop the word line gate stack the region between the word line stacks is then filled with a doped oxide such as bpsg and the surface is planarized such as by chemical mechanical polishing cmp an additional oxide layer 124 such as teos is then deposited then an anti reflective coating arc layer and a photoresist layer not shown are deposited and patterned the patterned layers are then used to mask an etching of the additional oxide layer 124 and the doped oxide layer 122 then the exposed portions of the silicon nitride liner layer 120 are etched to expose the regions of the semiconductor substrate that are to contact the bit lines however as fig2 d shows the etching of the silicon nitride liner layer 120 also causes substantial erosion in the nitride gate cap layer 108 the erosion of the nitride gate cap layer 108 reduces the effective insulation between the conducting layers of the word line stack and the subsequently deposited bit line conducting layers and possibly creates an electrical short between the word line conductor and the bit line conductor when sufficient gate cap nitride is removed to expose the word.