and s 6 in operation both signal dependent boost switch s 5 and signal independent cmos switch ss are employed switch ss is a small cmos switch to support infinite time for sampling as the coupling capacitor c 1 to switch s 5 may lose the charge for a very long sampling duration during non sampling time switch s 1 s 6 and s 4 are closed and switches s 2 s 3 s 5 and ss are open this causes the capacitor c 1 to be charged to a fixed dc voltage for example vdd vee additionally closed switch s 4 maintains at the high voltage nmos switch s 5 in an u201c off u201d state during the non sampling time during sampling time switch s 1 s 6 and s 4 are open and switches s 2 s 3 s 5 and ss are closed closed switch s 2 and s 3 apply an input dependent boost voltage for example input votlage vdd u2212 vee at the gate of nmos switch s 5 input dependent boosting of switch s 5 also helps to provide linear resistance for switch s 5 over all input ranges also during sampling time switch ss also remain closed to support infinite sampling time duration as a result of implementing this configuration several advantages can therefore be realized for example this configuration allows for better total harmonic distortion thd with a lower sampling time for all ranges with multiple channels associated with it also this implementation separates the path of the reference voltages.