33 mhz clock signal for example a clock signal for a 266 mhz processor can be divided by 7 to generate the 33 mhz clock a 200 mhz processor clock signal would be divided by 6 in one embodiment the integrated circuit 300 of fig3 includes a programmable divider counter to permit accommodating more than one processor clock speed placing the programmable divider in the circuit before the pll may result in an undesirable propagation delay across the programmable divider so that adequate relative synchronicity between the three plls cannot be achieved fig4 illustrates one embodiment of the integrated circuit of fig3 including programmable dividers integrated circuit 400 includes pll 410 420 and 430 programmable dividers 450 and 460 are associated with plls 420 and 430 respectively the plls typically have matched input paths coupled to a phase detector for example pll 420 includes matched input paths 422 and 424 the matched input paths ensure that any propagation delays contributed by the input paths are identical phase detector 426 provides an output signal in accordance with the phase relationship of the input signals in order to allow for synchronization of signals of different frequencies programmable divider counter 450 gates one of the inputs to phase detector 426 in the illustrated embodiment the reference clock signal to one input of the phase detector is gated with the divided clock signal from programmable divider counter 450 in particular the reference clock input signal is gated with the output of programmable divider counter 450 using and gate 429 in input path 424 the gated signal is then provided to phase detector 426 in order to ensure that the pll input paths 422 and 424 remain propagation delay matched input path 422 includes and gate 428 and gates 428 and 429 are designed to.