for the first capacitor 721 and the second capacitor 722 can be carried out much faster for shortening the interval t 10 so that the analog buffer 700 is able to perform analog signal buffering operations at a higher speed when the second control signal p 2 the first enable control signal ea and the fourth enable control signal q 1 b are set to be enabled signals and the first control signal p 1 the third control signal p 3 the second enable control signal eab and the third enable control signal q 1 are set to be disabled signals during the interval t 11 the output voltage vout is changed from the preset voltage vpreset to the voltage v 1 u00b1 u03b4v 11 based on the voltage v 1 of the input voltage vin in conjunction with the capacitor voltages of the first capacitor 721 and the second capacitor 722 since the third gate source voltage of the first transistor 711 and the third transistor 713 in turn on state is compensated by the capacitor voltage the first gate source voltage of the first capacitor 721 and the fourth gate source voltage of the second transistor 712 and the fourth transistor 714 in turn on state is compensated by the capacitor voltage the second gate source voltage of the second capacitor 722 the variation error is reduced to u03b4v 11 however the third gate source voltage and the fourth gate source voltage are not completely compensated by the first gate source voltage and the second gate source voltage respectively consequently the third capacitor.