logical links are maintained in the present example alternatively a greater or smaller number of lanes may be supported typically when port 24 receives a packet over one of these virtual lanes it passes the packet through switching core 22 to one of the other ports of switch 20 in accordance with routing tables held in the switch the other port transmits the packet over one of its own over one of its own virtual lanes until the packet reaches its final destination 0038 fig2 is a block diagram that schematically shows details of data structures in a buffer 25 in port 24 in accordance with a preferred embodiment of the present invention a similar structure is preferably maintained in entity 27 and in other entities that communicate over the fabric the structure of buffer 25 contains transmit queues 26 and receive queues 28 labeled txq and rxq respectively in practice transmit queues 26 are preferable u201c virtual queues u201d in the sense that buffer 25 does not actually hold any packets that are waiting to be sent over link 29 rather packets that are received by other ports and destined for transmission over link 29 are either cut through switching core 22 for immediate transmission over the appropriate vl on link 29 or are held in the buffers of the input ports that received them until the desired output port is available for transmission and credits are available on the appropriate vl in other words buffer 25 effectively serves as both the receive buffer for this port 24 and as a part of.