1 of 0 to the reset pulse input terminal r of the counter 63a since the counter 63a is adapted to be resetted by a binary signal of 0 applied to its input terminal r as previously noted it has its count value held at zero to generate an output s 2 of 0 even when its counting pulse input terminal is supplied with pulses from the oscillator 63b when abnormality occurs in the power transistors tr 1 tr 4 the stator coils l 1 l 4 of the pulse motor 5 the wiring connecting between the power transistors and the stator coils the wiring in the feeding system for the stator coils etc one of the exclusive nor circuits 62a 62d has its two input terminals supplied with respective binary inputs of 1 or 0 which are equal in level consequently an output s 1 of 1 is outputted from the nor circuit to the reset pulse input terminal r of the counter 63a through the or circuit 62e the counter 63a is thus released from its resetted state to start counting pulses generated by the oscillator 63b upon counting up the predetermined number of pulses corresponding to the predetermined period of time ta e g 2 seconds the counter 63a generates an output s 2 of 1 fig3 this output s 2 of 1 is applied to the alarm device 16 to actuate the same while simultaneously it is also applied to the common bases of the.