priority signal input terminal 61 is pulled up so that the signal of the 34 h 34 level is always applied thereto because there is no chip having the higher priority when the first priority signal pi 34 l 34 level signal is inputted from the priority signal input terminal such 34 l 34 level signal is transferred to a chip in the rear stage side as the second priority signal po 34 l 34 level signal via a gate circuit 63 in addition this chip is also provided with the last stage flag register 71 a logic 34 1 34 is written in the stage of initialization to the last stage flag register of the chip connected to the last stage while a logic 34 0 34 is written to the other chips when a logic 34 1 34 or a logic 34 0 34 is written to the last stage flag register 71 the last stage flag register 71 outputs the signal of 34 h 34 level or 34 l 34 level the storage area 30 of the chip 10 comprises a first area 31 for storing in the sequence of read addresses the data a common to a plurality of cascade connected chips a second area 32 for storing the data b differed from each chip and a third area 33 for storing the data c common to a plurality of chips like the first area 31 in this second embodiment for discrimination purpose the area having a younger read address than that of the second area 32 to store the data common to a plurality of chips is called the first area 31 and the area having an older read address than that of.