which is obtained by adding the error signal c to the level which is about a middle of the reading signal a since the slice level b is always generated following the reading signal a a problem that the slice level b is established preceding the reading signal a is solved further since the error signal c is also taken into consideration output data are neither outputted preceding the reference clock nor outputted following the reference clock namely in the present embodiment output data can be stabilized and phase correction operations similar to those of the conventional apparatus shown in fig8 can be conducted fig4 is a circuit diagram showing another embodiment of a slice level generating section structural elements in fig4 which are the same as those in fig2 are given the same symbols as in fig2 in the present embodiment peak detection and bottom detection section 30 sample and hold circuit 31 and slice level signal generating section 32 in fig1 are combined the sample and hold circuit 31 is composed of switch sw and capacitor c 1 an output of buffer amplifier 23 is connected with the switch sw whose end portion is connected with the capacitor c 1 a contact point of the switch sw is turned on closed first and it is turned off after synchronization as a result an output of the buffer amplifier 23 after synchronization is held in the capacitor c 1 whereby slice level b is stabilized in the present embodiment.