only in the power up section 401 of the first power vdd and at the low level u201c 0 u2019 when the first power is constantly supplied in the sections 403 and 405 when the second set signal pdpde is shifted to the high level u201c 1 u2019 after a predetermined time 401 passes after the output buffer 60 is powered up the output buffer reset signal evcchb_dq is at the high level u201c 1 u201d a 11 the output buffer reset signal evcchb_dq is at the low level u201c 0 u201d simultaneously when the first signal preset is shifted to the high level u201c 1 u201d a 21 the second set signal pdpde is a signal to enable the power down of the semiconductor device and is shifted to the high level u201c 1 u201d during power down 403 the first signal preset is a predetermined command signal input before the read command signal is input to the semiconductor memory device the first signal preset is a predetermined command signal input before the read command signal is input to the semiconductor memory device for example the first signal preset is a predetermined command signal input before the read command signal is input and may be a precharge signal a refresh signal a write signal an mrs mode register set signal and an active signal thus the output data of the memory device 20 for example a flash memory of the multi chip package 10 of fig1 is not affected at all until the other memory device 30 for example a dram is accessed while the output buffer.