from sending an additional uart frame in the default state between uart frame transmissions each tx buffer 215 is configured to drive its tx pin to the supply voltage level through the high output impedance at some point device 202 would clear its receive buffer such that rx buffer and receive flow control logic circuit 210 would command its rts control circuit 230 to again assume its default input high input impedance mode the drive from tx buffer 215 in device 201 would then recover the voltage on its tx pin which is detected by the corresponding cts control circuit 220 analogously to the detection of the asserted cts signal in a conventional uart interface upon detecting the high voltage on its tx pin cts control circuit 220 in device 201 would then signal this high voltage detection to the corresponding tx buffer and transmit flow control logic circuit 205 in response tx buffer and transmit flow control logic circuit 205 may initiate another uart frame transmission if the fifo buffer in device 202 were not full its rx buffer and receive flow control logic circuit 210 would not change the default high input impedance mode for its rts control circuit 230 the tx buffer 215 in device 201 would then maintain its tx.