lines and 1024 columns or bit lines dram block 50 differs from dram block 10 depicted in fig1 primarily in the position of column decoder 20 and the orientation of data lines 52 unlike the data lines 22 in dram block 10 of fig1 the data lines 52 of dram block 50 in fig5 run parallel to the direction of the columns instead of the rows of memory cell array 12 because data lines 52 are parallel to the columns of memory cell array 12 the additional space used by conventional methods to deliver more bits per clock cycle is not required by the method and system consequently the method and system require significantly less area in order to deliver a large number of bits compared to conventional methods and systems fig5 depicts one embodiment of an array 100 of eight dram blocks 50 fig4 in accordance with the method and system the array 100 is capable of delivering one hundred and twenty eight bits per clock cycle all 128 bits are delivered through bus 102 to data sense amplifiers 120 in the array 50 100 the block decoder 110 selects which block 50 will be activated in order to deliver the bits in the embodiment shown in fig5 only one block 50 is activated during one clock cycle because only one block is activated significantly less power is utilized than in conventional methods and systems which activate greater.