transfer transistor 21 and will remain within the well of the photodiode region as shown in fig6 after the integration period ends a voltage readout occurs as illustrated in fig7 in which the voltage at the photodiode 11 is now read out by the source follower transistor 17 and row access transistor 13 onto the column line 15 following an initial readout illustrated in fig7 a second readout occurs where a gate voltage to the transistor 21 is applied to lower the barrier potential 29 this causes charges stored on capacitors c 1 and c 2 to be redistributed to equalize voltage levels as illustrated by charge 47 in fig8 this voltage level is continually read out by the source follower transistor 17 and row select transistor 13 onto the column line 15 finally as shown in fig9 the transistor t 3 is turned on lowering barrier potential 31 which couples charge stored at capacitor c 3 to the charge stored on capacitors c 2 and c 1 which is illustrated as voltage level 49 since the charge stored on capacitor c 3 during integration charge was nill the voltage 49 which is read out at this point is very small fig2 9 illustrate operation of the fig1 pixel cell during a low light condition operation of the fig1 circuit in a medium fight condition will now be described with reference to fig1 5 and 10 13 the pixel cell of fig1 operates to reset and begin charge integration as described above with reference to fig2 6 when the accumulated charge 45 generated by photodiode 11 begins to approach the barrier level 29 set by a.