85 mhz yet the data rate to the ate is only 17 mhz will have been accurately sampled table 1______________________________________seq 1 10l0l010 01010101 11111111 00000000j 1 2 3 4seq 2 10101010 01010101 11111111 00000000j 5 6 7 8seq 3 10101010 01010101 11111111 00000000j 9 10 11 12seq 4 10101010 01010101 11111111 00000000j 13 14 15 16seq 5 10101010 01010101 11111111 00000000j 17 18 19 20seq 6 10101010 01010101 11111111 00000000j 21 22 23 24______________________________________ therefore undersampling digital testability circuit 20 samples the repeating 32 bit sequence thus accurately testing each high speed data transfer it should be noted that this test methodology ignores 16 of 20 data transfers in the continuous 32 bit data stream this means that individual random failures may be missed however since each eight bit word is sampled over a period of time as shown in table 1 the same probability exists that the random failure will be discovered for a given number of comparisons therefore circuit 20 is effective in catching failures the example provided above used the relation n m i 1 for undersampling the transferred data however circuit 20 is not limited to this undersampling solution the above relation is desirable only because the sampled words come out in the same sequence in which they were input this is not necessary as long m and n are mutually prime numbers circuit 20 will sample every word once every m n clock cycles since an engineer has control of the values of m and n the engineer will also know the appropriate output sequence of words to expect and can.