10 a in accordance with an embodiment of the present invention processor 10 a includes multiple cores 12 a 12 c each having disparate isas while the illustrative embodiment depicts three cores having different native isas it is contemplated that any desirable arrangement and number of cores may be included within a processor in accordance with an embodiment of the present as long as at least one of the processor cores has an isa differing from that of the other cores for example in an 8 core processor one core may support an isa that is infrequently required while the other seven cores implement the most universal isa in the illustrated embodiment core 12 a supports the powerpc ppc instruction set as originally promulgated by the apple ibm motorola aim alliance core 12 b supports x86 instruction sets as originally promulgated by intel corporation and implemented by many present day manufacturers and core 12 c supports an instruction set optimized for the system z operating environment such as the z9 integrated information processor ziip instruction set as promulgated by international business machines corporation other types of cores such as special purpose co processors and accelerator engines could also be included but are.