emitters pins 2 3 4 12 13 and 14 full current drive capability of the multiple or gate output structure is obtained fig1 and fig2 show one led driver configuration in which the normal logic function is preserved the input source 40 is wired to pin 5 v bias 36 is the led 33 bias voltage that is the cathode of the led 33 is connected to the v cc pin 5 of the gate while the anode of the led is connected to v bias 36 r e 37 which is a current setting resistor is connected to pins 2 3 4 12 13 and 14 the value of r e 37 is selected to provide the desired current for the emitter coupled pair and in turn the led current v ee 39 the most negative power supply voltage usually 5 2 volts is at pin 8 v tt 38 a termination resistor voltage supply for the outputs is nominally 2 0 volts when v ee is 5 2 volts v tt 38 or v ee 39 is connected to output terminals through r e 37 the v cc v ee voltage differential is generally limited to less than 8 volts v cc is the higher bias value and is generally 0 volts ground this allows the gate inputs 9 10.