from the comparator 18 the bit inversion circuits 15 a 15 b invert every one bit of the transmit data in n bit section when the comparison result of the comparator 18 is u2018 0 u2019 sign accordance output and they do not invert the transmit data when the comparison result is u2018 1 u2019 sign disaccord output further the operation of the data processing equipment in the embodiment will be detailed the timing chart in fig6 and 7 shows an example of transmit data 6eh cah 9bh b7h bfh dfh 3eh efh section a 1 in fig6 81h c3h 3bh 63h 2ah 39h 85h 89h section b 1 in fig6 and 4ah b2h 61h 24h 4bh cch 9ah 58h section c 1 in fig6 and 7 which are hexadecimal data and are sequentially transmitted from each lsb least significant bit for example when u2018 63h 01100011 u2019 is transmitted from lsb u2018 11000110b u2019 is sent out though data in section a 1 are not completely shown in fig6 they are equal to a 2 shown in the transmit data tx 2 data in section b 1 are output by every two bits trough the multiplexer 19 then shifted totally by 64 bits by the 32 bit shift registers 13 a 13.