2 inverts and delays the signal s 1 to output the signal s 2 and the inverter i 3 inverts and delays the signal s 2 to output the signal s 3 accordingly when the delay time each of the inverters i 1 i 2 and i 3 is equal to the time td if the signal e 1 of the h level is provided the inverters i 1 i 2 and i 3 produce the pulse signals s 1 s 2 and s 3 with the duty cycle of 50 and the period of 6td the pulse signals s 1 s 2 s 3 are individually the signals toggling in order with the delay time td from the rising edge of the signal e 1 turning to fig5 a detailed circuit of a ring oscillator 38 according to the embodiment of fig2 constituted of the same elements as those of the ring oscillator 400 of fig4 is indicated generally by the reference numeral 500 the ring oscillator 500 differs from the ring oscillator 400 in that an inverted set signal sb is input to a gate of the pmos transistor p 3 and the reset signal r is input to a gate of the nmos transistor n 3 in the ring oscillator 38 in operation of the circuit 500 when the signal e 2 of the l level is input.