displacement field to a particular base address selected by the instruction 39 s base register field if an overflow is detected indicating that the resulting address encroaches on the next segment operation is aborted it will thus be understood that the address range which each instruction can access using the approach disclosed in u s pat no 4 251 860 is limited to a single segment the preferred embodiment of the present invention illustrated in fig1 maintains the narrow data path advantages of u s pat no 4 251 860 while on the other hand making it possible for the same instruction to generate addresses capable of accessing data in a plurality of different segments as will become evident from the description which follows thus referring to fig1 it will be understood that as typically occurs during data processing operations an instruction to be processed is fetched and placed in an instruction register 10 as shown a typical instruction includes an opcode op which designates the operation to be performed and an address portion comprised of an index i and a displacement d which as will be described hereinafter together cooperate in the generation of a virtual or logical address typically the opcode op is sent to the data processor 39 s execution unit not shown for performance of the operation designated by the opcode on the data in memory corresponding to the generated address the particular manner in which such execution may be performed is not part of the.