is applied to primary winding 14a of a rotary transformer winding 14a is magnetically coupled to secondary winding 14c which winding 14c supplies a signal to data reconstructor circuit 22 reconstructor 22 comprises a pair of ecl emitter coupled logic threshold circuits 50 and 52 which circuits respectively provide pulses representing positive and negative going edges to the s set and r reset inputs respectively of an ecl s r flip flop 54 the output waveform of flip flop 54 is shown in fig4 c and comprises the output of reconstructor 22 source 10 also provides clock pulses for the nrz information which pulses have no d c content to clock driver 20 which driver comprises a delay line 56 having a time delay selected to provide best restrobing of the data and an amplifier 58 having an input coupled to the delay line in the present embodiment the delay of line 56 was selected so that the positive going edges of the recovered clock pulses occur at about the middle of the recovered data pulses of fig4 c driver 20 supplies clock pulses to primary 14b of the rotary transformer secondary winding 14d is magnetically coupled to primary 14b and thus receives the clock signal since the clock signal has no d c content and is of constant frequency unlike the nrz information signal its edges retain their timing when passing through the rotary transformer the clock pulses are applied to clock receiver 24 which can comprise an ecl amplifier with its input terminated in the characteristic impedance presented by secondary 14d this termination prevents reflections that may cause timing errors in the recovered clock pulses data restrobe circuit 26 comprises an ecl d type flip flop with.