architectures that allow for several instruction to be in various stages of execution at each processor clock cycle additionally in one embodiment the processor itself manages the instruction pipeline and the instruction cache in another embodiment of the present invention the instruction pipeline and instruction cache may be managed by hardware associated with the processor but not actually considered part of the processor as mentioned above it is possible that one processor may manage these components for another processor as an illustrative example of an embodiment of the invention consider the following set of processor instructions in this exemplary set of processor instructions program execution will jump from the u201c branch cond l 1 u201d instruction to the u201c inst c 0 u201d instruction at label u2018 l 1 u2019 if u2018 cond u2019 is u2018 true u2019 or non zero otherwise program execution will proceed to the u201c inst b 0 u201d instruction first if the instructions at the u2018 l 1 u2019 label are not in the processor 39 s instruction buffer at the time the u201c branch cond l 1 u201d instruction is executed the processor may incur a branch penalty to further elaborate on this exemplary use of the conditional pre fetch instruction consider the above sample set of processor instructions at execution time when the branch is taken and the instructions at u2018 l 1 u2019 are not present in the processor 39 s instruction buffer exemplary clock cycles have been provided for further illustration as indicated the condition pre fetch operation may advantageously save a significant number of processor clock cycles when compared with a similar scenario that does not use a conditional pre fetch as described above in another example of using a conditional.