the memory in fig5 b a calculation function is shown which receives a signal corresponding to a delay d exhibited by the delay line and calculates configuration parameters p c as a function of the delay d in accordance with the general relationship as with fig5 a the function f may be one of many possible functions which provide a mapping from the delay d to the configuration parameters p c for instance the amount of the delay d is likely to be proportional to the access latency of the memory and so a simple relationship between the delay d and a number of clock cycles required to accommodate an access latency of the memory could be provided it will be appreciated that while the functions illustrated in fig5 a and 5b could be provided as alternatives it is possible to provide a function which relates voltage v clock frequency f clk and the delay d to one or more configuration parameters p c referring now to fig6 an example memory controller 600 is schematically illustrated the memory controller 600 comprises interface circuitry 630 which provides a connection to a memory not shown and control circuitry 610 which is operable to set configuration parameters for controlling an access operation to read data from or write data to the memory the control circuitry 610 sets the configuration parameters in dependence on a signal received at a first input 604 which is indicative of a supply voltage v and on a signal received at a second input 606 which is indicative of a clock.