memory circuit 10 input voltage v dd3 is continuously applied to a high voltage logic section 18 of memory circuit 10 responsive to the presence or absence of an input backup signal bkp from elsewhere in memory circuit 10 than from any of the elements thereof shown in fig1 high voltage logic section 18 manages the functioning relationships among the other elements of memory circuit 10 that are included in fig1 high voltage logic section 18 does so through a variety of output signals a select few of which are included in fig1 these include a regulator enable signal rgn that is communicated to internal ldo power supply regulator 16 as well as an isolate signal iso and a memory array backup signal bka that are transmitted to ram section 12 during backup operation of memory circuit 10 responsive to appropriate of these output signals from high voltage logic section 18 internal ldo power supply regulator 16 is turned off and ram section 12 operates without the benefit of internally regulated low voltage v dd memory circuit 10 is configured so as to minimize the electrical charge consumed as leakage current during any period in which memory circuit 10 is powered down or inactive and all of the data states set in ram section 12 are to be preserved all circuit elements concerned with the preservation of the data state in ram section 12 are high voltage components that exhibit low leakage.