the memory device of the present invention control circuit 100 receives input signals including clock clk 102 latching signal a rlat 104 column access signal col 106 pre charge or iopu signal 108 upon a clk signal 102 of an active command rlat signal 104 is pulsed to set latch 110 the setting of the latch 110 sends node voltage a to a logical low level in starting a read write function write signal 114 is fired along with col signal 106 the write signal 114 along with clk signal 102 is input into nandgate nand 116 the output 118 of nand gate 116 is ultimately used as the input to nandgate 120 along with node a 112 a high column signal 106 along with a clk signal 102 will provide a high column signal 106 into nand gate 120 forcing iopu end high because of the delay circuitry 122 the firing of a column signal 106 ultimately will reach node a after a brief delay 112 and upon the next clock pulse will force node a 112 high upon the falling edge of the clk signal to low with node a 112 high iopu end 115 will thereafter rise and fall based upon clk pulse 102 until a.