98 via adhesive and chip 98 is mounted on a substrate 102 also using adhesive a first side not visible of chip 98 is mounted on substrate 102 chip 100 is mounted on the second side 99 of chip 98 chip 100 includes conductive pads as shown that are connected via wire bonds like wire bond 104 to conductive line 34 a portion of conductive line 34 is exposed by an opening 106 etched into passivation layer 50 in the manner shown in fig3 this permits wire bond 104 to be electrically connected to the conductive line by a bonding process as a result internal circuitry of chip 100 is electrically connected to conductive line 34 via a chip pad on chip 100 and wire bond 104 this redistributes the connection point for the internal circuitry of chip 100 another opening 108 over conductive line 34 provides access to the conductive line for bonding one end of another wire 110 to conductive line 34 the other end of wire 110 is bonded to a terminal 112 on substrate 102 other terminals on chip 100 are bonded to other conductive lines via wire bonds like wire bond 104 as shown and these other conductive lines are in turn bonded to terminals like terminal 112 on substrate 102 via wire bonds like wire bond 110 in this manner the connections to circuitry in chip 100 are redistributed to facilitate wire bonding in a manner that obviates problems associated with the length height and bonding angles of the conventional approach chip pads or terminals on first semiconductor chip 98 are connected to terminals like terminal 114 on substrate 102 via.