g an asserted latch signal as described below from comparator 520 of fig5 this halts the adaptive ramp amplitude controller from further programming the targeted nv memory cell at the second ramp rate and causes the output voltage provided by the adaptive ramp amplitude controller see fig7 to realize a voltage reduction this reduced output voltage is maintained until the end of the coarse cycle is reached as detected by deassertion of a course end coarse signal concurrently the adaptive ramp amplitude controller includes a memory circuit which stores a voltage realized when the comparator has disabled the adaptive ramp amplitude controller as described in more detail in fig7 this voltage value is approximately a stepback voltage v stepback lower than the actual stop voltage in order to protect the targeted nv memory cell from being over programmed in the succeeding fine cycle in this embodiment v stepback is approximately 1v although another voltage may be used when the analog ic storage device begins the fine cycle 650 a first fine ramp pulse 655 initially increases at a third ramp rate 660 preferably the third ramp rate 660 is approximately equal to 2v u03bcs it is contemplated that another ramping rate may be appropriate provided third ramp rate 660 is greater than the.