the source 112 and the drain 114 are formed in the substrate 110 separately the first oxide 120 is formed on the substrate 110 the floating gate 130 is formed on the first oxide 120 the second oxide 122 is formed on the floating gate 130 the control gate 140 is formed on the second oxide 122 the flash memory cell 100 comprises a channel region 116 the channel region 116 in the substrate 110 is disposed between the source 112 and the drain 114 the floating gate 130 is located above a part of the channel region 116 the floating gate 130 has a curved top surface 132 that is depressed at the center of the curved top surface 132 the floating gate 130 has at least one sidewall 134 that intersects the curved top surface 132 to form a sharp edge 136 the second oxide 122 covers the sharp edge 136 and the sidewall 134 of the floating gate 130 the control gate 140 is over the substrate 110 and covers a part of the floating gate 130 including the sharp edge 136 of the floating gate 130 the substrate 110 is doped with p type ions and the floating gate 130 is heavily doped with p type ions on the contrary the control gate 140 is heavily doped with n type ions and the source 112 and the drain 114 are also.