100 to 300 nm the semiconductor structure is shown with a patterned photo resist layer 40 formed on top of the gate material layer 30 the photo resist layer 40 has a thickness of from 500 to 800 nm the resist pattern is made so as to protect the areas where active devices will be formed this patterning may be accomplished by means of standard lithography and etching techniques which are well known in the art in fig1 a by way of example the patterning of the photo resist layer 40 creates a window or hole 45 by which a particular portion of the gate material layer 30 may be implanted with ions of a particular type after the photo resist layer 40 has been patterned an n type dopant such as phosphorus arsenic or aluminum is then implanted onto the semiconductor structure the region of the gate material layer 30 directly underneath the window or hole 45 is doped with the n type dopant thereby forming an n region within the gate material layer 30 for ease in explanation the region of the gate material layer 30 directly underneath the window or hole 45 will be called a first region fig1 b.