u201c electrically connected u201d etc are used interchangeably herein to generally refer to the condition of being electrically connected it is further noted that various block diagrams circuit diagrams and timing waveforms shown and discussed herein employ logic circuits that implement positive logic i e a high value on a signal is treated as a logic u201c 1 u201d whereas a low value is treated as a logic u201c 0 u201d however any of the circuit discussed herein may be easily implemented in negative logic i e a high value on a signal is treated as a logic u201c 0 u201d whereas a low value is treated as a logic u201c 1 u201d fig4 is a simplified block diagram of a delay locked loop dll 36 according to one embodiment of the present disclosure as noted before the dll 30 is one type of synchronous circuit that can be internal to any integrated circuit including for example an sdram memory unit as shown for example in fig1 it is pointed out that throughout the discussion herein the same reference numerals are used to designate identical circuit elements or signal waveforms and or to also facilitate ease of discussion a comparison of the dll in fig1 and the dll 36 in fig4 shows that the dll 36 additionally includes a clk 180 decoder 38 interchangeably referred to herein as the u201c clock decoder u201d or the u201c decoder u201d 180 however the overall function of the dll 36 is identical to that of the dll 10 which is to synchronize the external clock 12 with the internal clock 14 as shown.