where each color pixel element consists of an interconnection of these individual pixel devices fig4 is a planar view of a color pixel element 100 which consists of one each red 73 and green 75 emitting pixels and two blue emitting pixels 76 and 76 39 the darker cross hatched metal of fig4 is a second metal layer 72 insulated from and above a common ground layer with connections 109 and addressed through a power bus with a connection 107 the full color pixel 100 is therefore comprised of an array of red 73 green 75 and blue 76 and 76 39 pixel devices whose column addresses are connected in parallel and whose row gates are addressable by color thus row gate addressing by color addressing through the connections 101 103 and 105 and column addressing through the connection 107 achieves a full color addressable pixel element the topology illustrated in fig4 may be used in a manifold redundancy as a single color pixel in a large area color panel displays each color pixel is expandable principally in the indicated y dimension in fig1 to the requirements of the pixel density the minimum area required by the topology of fig4 depends upon the minimum dimension set for the line width indicated as w and the spacing between lines indicated by s in fig4 the minimum line width of state of the art manufacturing process continues to shrink toward 0 1 micron the result of such decreasing dimensions is to allow pixel densities to increase well beyond 10 million per square inch such pixel densities meet the most demanding requirements.