and the flip flop 25 has the set input s coupled with the output of the timer 3 the outputs of the flip flops 23 and 24 are respectively the drive signals hside and lside for the transistors hs and ls the circuit 100 also comprises a timer 26 which when the input is at a low logic level has a low output initially the set reset flip flops 23 and 25 are reset while the flip flop 24 is set when the signal vfb falls below the value vref the comparator 21 sets the flip flop 23 in this manner the signal hside is raised while the signal lside is lowered and the voltage vout rises above the value of the voltage vref after a period given by the turn on time ton of the transistor hs the timer 26 changes the signal in output taking it to a high logic level said signal resets the flip flop 23 which in turn lowers the signal hside and raises the signal lside the circuit 100 also comprises a timer 27 suitable for establishing the minimum turn off time toff of the transistor hs in this manner the stability is assured in relation to the noise induced by the switching of the transistors hs and ls the signal dis is the signal q in output from the flip flop 25 in fig1 the time diagrams of the signals vout vfb vref il and min_freq are shown it can be observed that the.