sections ds 1 ds 2 and ds 3 are one of the combinations of 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0 and 1 1 0 the combination of 0 0 0 indicates that the threshold value of the memory cells has not got to the u201c 00 u201d first step write verify voltage by the n u2212 1 th write step the combination of 0 1 0 indicates that the threshold value of the memory cells has got to the u201c 00 u201d first step write verify voltage but not to the u201c 00 u201d second step write verify voltage by the n u2212 1 th write step the combination of 1 1 0 indicates that the threshold value of the memory cells has got to the u201c 00 u201d second step write verify voltage it is not possible that the threshold value of the memory cells has got to the u201c 00 u201d second step write verify voltage but not to the u201c 00 u201d first step write verify voltage by the n u2212 1 th write step so that the combination of 1 0 0 does not exists in this embodiment if the threshold value of the memory cells has not got to 2 2v which is the u201c 00 u201d first step write verify voltage by the n th write step the detection outcome of the u201c 00 u201d first step write verify operation is not satisfactory so that the data in the data storage sections ds 2 are not changed if on the other hand.