network topology clearly appears in vertical direction three levels j j 1 and j 2 are shown whereby j may generally represent integral numbers from 1 to m in horizontal direction the level j consists of several backplanes bpi where i can assume integral numbers from 1 to n each backplane bpi may in turn contain a plurality of central units pk where k represents integral numbers from 1 to p p is therefore representative of a multiprocessor system which is installed on a backplane a backplane is understood to be a board having a plurality of layers in which the plug in points installed on it are connected to circuits it can be compared roughly to a typical at bus plate which is however not multiprocessor capable like the backplane bp of fig1 and 2 only the multiprocessor capability makes it possible for the communications protocol on the network of level j 1 to correspond to the communications protocol on the backplane by contrast with fig1 and 2 as well as with the fig3 yet to be discussed representing examples of embodiments of the invention circuits of the state of the art are explained in fig4 a and 4b concerning fig4 a it was already explained in the beginning why this topology is time intensive collision prone and has little structure the network topology of fig4 b which would be a possible alternative of.