layer 12 to form trenches 28 for interconnection lines and holes 26 for via studs to expose metal line 24 the foregoing steps are initial process steps of the method conventionally known in the art as a double damascene method the present invention is implemented at the point in the process where the combined via stud 26 and interconnection line 28 patterns are etched in composite layers 12 14 16 18 to expose portions of metal line 24 referring now to fig3 c a dielectric layer 30 of preferably pecvd deposited sio 2 of approximately 150 nm thickness is deposited the dielectric layer 30 may be deposited by electron resonance cyclotron ecr sputtering high density plasma pecvd cvd spin coating or any combination of these methods the dielectric layer 30 may also be made of polyimide silicon nitride alumina phospho silicate glass yttrium oxide magnesium oxide or any combination of these materials the low k dielectric 14 and dielectric layer 30 must not be the same material as dielectric layer 30 must be denser and more robust than low k dielectric 14 next substrate 10 and insulating layers 12 14 16 18 30 are subjected to a directional etch for example a reactive.