is performed for each bit by first stage decoder 1 the quotient for each bit is applied to addition circuit 4 by way of line 106 and the remainders are applied to adder 5 by way of line 105 the output of adder 5 is applied to second stage decoder 2 for every bit of the binary number decoding for division by the divisor is performed for each bit by second stage decoder 2 quotients produced by second stage division are applied to addition circuit 6 by way of line 109 and the remainders are similarly applied to addition circuit 7 by way of line 108 the output of addition circuit 7 is applied to third stage decoder 3 for each binary number bit third stage decoder 3 also performs decoding for division by the divisor for each bit and the quotients are applied to addition circuit 8 by way of line 112 the remainders for each bit of third stage decoder 3 are applied to corrective decoder 10 by way of line 102 at corrective decoder 10 corrective output of the quotient is applied to addition circuit 9 if the sum of the remainder output of each third stage decoder 3 is greater than the divisor and the remainder is outputted as the final remainder by way of line 120 if the sum of the remainder of third stage decoder.