to and retrieves output test data from the chip functional circuitry via the chip in and chip out lines the scan out line for any particular pad scan circuit 14 is also the scan in line for the next pad scan circuit 14 in the ring a test access bus 20 comprising three conductors is also illustrated in fig1 connected to each of the pad scan circuits 14 the test access bus 20 carries control data controlling the operation of each pad scan circuit 14 as will be more fully explained in conjunction with the discussion of fig2 as will be more fully appreciated after the discussion of fig2 test data can be entered into the chip via any of the i o pads 12 and the results taken off chip for analysis via any of the i o pads 12 thus it is not necessary to have an i o pad and corresponding integrated circuit pins dedicated for providing test data to the chip or retrieving test results from the chip however the present invention does not pre empt the use of dedicated pins for input and output test data if so desired the use of the pad scan circuits 14 for each i o pad allows complete testing of two paths overlooked in prior art test techniques in the prior art designs after the chip is inserted into a system the signal path from each pad to the first scanning test register cannot be tested completely without the aid of external devices this is due to the loss of access to individual chip pads once a chip leaves its test environment the present invention allows test data to be serially clocked into each or any.