video data into the image memory 64 will be described the computer 61 sets the access mode to the image memory 64 to the video data write mode consequently the data selector 1 is put into a condition wherein it selects the digitized video data 12 and the fifo memory write request selector 2 is put into a condition wherein it selects the video data write request signal 14 the digitized video data 12 digitized by the analog to digital converter 62 and the video data write request signal 14 are rendered active and the write counter 41 of the fifo memory controller 4 increments its count value further the fifo memory write control circuit 42 outputs a fifo memory write control signal 24 to the fifo memory 3 in accordance with the count value of the write counter 41 to write the write data 23 in this instance digital video data into the fifo memory 3 meanwhile also the up down counter 45 of the fifo memory controller 4 increments its count value and the memory access request circuit 46 outputs a memory write access request signal 26 to the fifo memory controller 4 the memory access controller 6 controls the count values of the x and y direction address counters 10 and 9 in the address controller 7 in accordance with the address select signal 31 to effect write access to the image memory 64 then the memory access controller 6 outputs a one write access end signal 28 to the fifo memory controller 4 and outputs to the address controller 7 a count up signal 30 for incrementing the x direction address counter 10 meanwhile the memory access controller 6 simultaneously controls the memory access signal 32 after the one write access end signal 28 becomes.