the background art shown in fig6 in that the pc 10a includes a comparing circuit 1 having a stop request interrupt line 8 which is connected to cpu 11 details of the comparing circuit 1 are shown in fig2 comparing circuit 1 comprises a sequence program partial run condition entering unit 2 which is composed of a data entry memory 2a a device entry memory 2b and an access method read write entry memory 2c a logic circuit 3 which is composed of four and elements 3a to 3d connected in a tree configuration completes the comparing circuit a data bus 5 is connected to the and element 3a together with an output line 4a of the data entry memory 2a an address bus 6 is connected to the and element 3b together with an output line 4b of the device entry memory 2b a control bus 7 is connected to the and element 3c together with an output line 4c of the access method read write entry memory 2c the data entry memory 2a and the data bus 5 the device entry memory 2b and the address bus 6 and the access method read write entry memory 2c and the control bus 7 are anded by the and elements 3a to 3c respectively the output from these three and elements are further anded by the and element 3d and its output is entered into the cpu 11 via the stop request interrupt line 8 if the output of the and element 3d is high i e 34 1 34 it is a sequence program stop request to the cpu 11 if the output is low i e 34 0 34 no stop operation is performed fig3 is a ladder.