a sample of a voltage within the pll 30 that represents phase error at a time when the transient phase error should be at a minimum the sampling switch 47 is preferably coupled to the phase detector 38 to sample the error signal pulses that are generated by the phase detector 38 the sampling switch 47 is preferably a field effect transistor fet however the scope of the invention includes using other controllable devices such as bipolar junction transistors a memory device 45 stores the voltage level of the sampled error pulse preferably until another sample is received the scope of the invention includes using both digital memory devices as well as analog memory devices examples of digital memory devices include a processor controller in combination with memory to store a digital representation of the phase error examples of analog memory devices include sample and hold circuits active filters and inductive storage circuits the memory device 45 in the presently preferred embodiment is an amplifier configured as an integrator in response to receiving an error pulse the integrator generates an output voltage that is incrementally increased or decreased according to the charge represented by the product of the error voltage level and pulse duration of the error voltage the output.