u00b0 out of phase clocking signals as discussed above as a result the shift times of the two memory modules 48a 48b or 48c 48d will automatically be displaced by one half cycle of the clocking signals while memory modules 48c 48d also operate with the twin multiplexing arrangement just described it is noted that the clocking signals fed to such memory modules 48c 48d are delayed 90 u00b0 therefore the loading signals st1 b st2 b st1 c st2 c st1 d st2 d are fed to memory modules 48b 48c and 48d respectively as shown in fig2 such loading signals are produced by the pulse generator 606 fig6 such that the pulses and lines st1 b st2 b are delayed here 4 ns with respect to the pulses on lines st1 st2 respectively the pulses on lines st1 c st2 c are delayed here 2 ns with respect to the pulses on lines st1 st2 respectively and the pulses on lines st1 d st2 d are delayed here 6 ns with respect to the pulses on lines st1 st2 respectively the condition described for the input sampling whereby an array of digital circuits can be arranged to take samples of a signal with a frequency beyond the capability of one individual circuit does not hold for the output multiplex portion of the memory 12 where the outputs of the four memory modules 48a 48d must be combined to reconstruct the original signal this output multiplexer must have a true bandwidth equal to the effective sampling rate here 500 mhz to operate successfully the data produced at the outputs of memory modules 48a 48d are combined in a diode.