about 800 u00b0 c and 1000 u00b0 c or by using chemical vapor deposition with a thickness of between about 50 and 300 angstroms the gate electrode trench and the conductor electrode trench are then filled with polysilicon using low pressure chemical vapor deposition and doped to the desired concentration level using pocl 3 doping or ion implantation the polysilicon is then etched back to leave polysilicon only in the gate electrode trench 24 and the conductor electrode trench 23 a thin oxide layer 27 between about 100 and 1000 angstroms thick is then formed over the surface of the substrate as shown in fig5 the source drain regions made up of n or p regions 40 and n or p regions 42 are formed using ion implantation the thin oxide layer 27 is then etched away from the contact end of the conductor electrode trench the top part of the gate oxide 26 formed on the side walls and end wall at the contact end of the conductor electrode trench is then etched away using reactive ion etching with chf 3 o 2 or the like or dipping in hf content solution forming the contact cavity 44 the alignment of the lithography steps required are not critical as shown in fig6 the contact cavity is then filled with a conductive contact material 28 such as doped polysilicon metal or a silicide using chemical vapor deposition or physical vapor deposition the surface of the substrate is then etched back so that the conductive contact material remains only in the contact cavity the surface of the substrate is then covered with a layer of pre metal dielectric 30 the completed device after the patterned metal layer 32 has been formed is shown in.