to the comparator 26 sensing vout becoming less than vthresh the switching logic 28 deactivates the transistor 20 b and activates the transistor 20 a thus causing a charging current to flow from vin through the inductor l to the filter capacitor c and to the load 12 ideally the rising vthresh and falling vout u201c meet u201d at vref such that vout becomes less than vref at the same time that it becomes less than vthresh this charging current causes vout to rise assuming that in a steady state the load 12 draws a constant current the actual rate of this rise depends on the capacitance and equivalent series resistance esr of c in one embodiment the capacitance and esr of c are sufficiently large such that vout increases at a substantially constant rate i e straight line as shown also at time t 0 in response to activating the transistor 20 a the switching logic 23 generates a disable signal which causes the threshold signal generator 24 to u201c discharge u201d the node 32 to the base voltage of vref u2212 voffset at time t 1 which is a predetermined constant time after t 0 the switching logic 23 deactivates the transistor 20 a and activates the transistor 20 b thus allowing the current stored in the inductor l to continue flowing as this current decays vout falls when vout falls below vthresh the above described cycle is repeated also at time t 1 in response to deactivating the transistor 20 a.