signal layer of the printed circuit board this scheme works to minimize extrinsic skew originating from the different operating conditions on each layer of the board such conditions include the propagation velocity of signals along traces as well as noise from other parts of the circuit board any condition specific in some way to the signal layer will be borne equally by each of the traces and its effect on the relative skew between the traces will be therefore minimized wide traces 5 with relatively high intrinsic capacitance help counteract extrinsic skew originating from small manufacturing variances in the capacitance of the various loads 6 these variances are typically on the order of about 3 pf to about 8 pf the relatively high capacitance of the traces 5 translates into a correspondingly lower characteristic impedance in the presently preferred embodiment of the invention the characteristic impedance of the 10 mil traces is on the order of 40 u03c9 laying the traces 5 out in parallel from the metal island 4 reduces the impedance as seen by the clock driver 1 even further for instance with four parallel traces each with characteristic impedances of 40 u03c9 each the effective impedance seen by the driver 1 is only 10 u03c9 standard design rules for high speed digital circuits usually call for impedance matching at the trace ends.