frequencies of the overflow output terminal o and the clock input terminal of u03b4 u03c3 modulator 60 after programming an integer 200 into the register 70 for example the adder 65 then outputs 200 or 201 to the multi modulus divider 55 as the long term average it generates a frequency being divided by u201c 200 5 16 u201d however the multi modulus divider 55 is rather challenging to be implemented please refer to fig4 which illustrates a fractional n pll frequency synthesizer 200 comprising a phase frequency detector 210 a charge pump 220 a loop filter 230 a vco voltage controlled oscillator 240 and a u03b4 u03c3 modulator 250 a reference signal with a reference frequency fref is generated by a reference oscillator not shown and the reference signal and an overflow signal from the u03b4 u03c3 modulator 250 e g a u03b4 u03c3 numeric counter enter the phase frequency detector 210 the phase frequency detector 210 detects a phase and frequency difference between the reference signal and the overflow signal and then outputs a phase difference signal to the charge pump 220 the charge pump 220 then generates a corresponding output current pulse to the loop filter 230 according to the duty cycle of the phase difference signal for example the width of the charge pump current pulse is proportional to the duty cycle of the phase difference signal the loop filter 230 integrates and transforms the output current pulse of the charge pump 220 into a control voltage to the vco 240 where the vco 240 adjusts its output frequency fvco in accordance with the control voltage the clock input terminal of the u03b4 u03c3.