the actual first delay period and second delay period differ from a preset value target delay period for example the above comparator 9 may comprise a phase detector 6 detecting the phase difference second delay period between the original system clock applied thereto and the delayed system clock outputted from the delay array through point u201c d u201d and a counter 7 generating the control signal according to the phase difference received from phase detector 6 obviously the above counter 7 may be configured to generate the control signal according to the difference between a preset value and the detected phase difference or second delay period in other words counter 7 calculates according to the phase difference to what extent the first delay period shall be adjusted and generates the control signal according to the calculation the phase lock circuit is so configured that when the second delay period or the phase difference is bigger than the preset value the control signal is generated in such a way that both the first delay period and the second delay period are reduced respectively by the strobe delay element 5 and the delay array 8 to both of which the control signal are applied and when the second delay period is smaller than the preset value both the first delay period and the second delay period are increased respectively by the strobe delay element 5 and the delay array 8 to both of which the control signal are applied the above data array 8 comprises a group of serially connected clock delay elements.