clock signals ck 1 to ck 3 are used to adjust timing but it is acceptable that a plurality of clock signals having different delay time is used b the numbers of the combinational circuits and the ff groups are not defined they can be set freely in accordance with the function and scale of a semiconductor integrated circuit applied as described above according to a first aspect of invention the hard macro has the first ff for holding data given from the first data path at timing delayed from the clock signals and the third ff for holding data to be outputted at timing advanced from the clock signals accordingly limits on the delay time of data paths on the input and output sides are relaxed and the processing time can be shortened according to a second aspect of the invention the semiconductor integrated circuit has the delay devices for generating the clock signals for the input and output ffs and the adjusting unit for adjusting the timing of the clock signals to be fed to each of the first to third ff groups in the hard macro accordingly the timing of the clock signals does not need to be adjusted outside and the hard macro can be operated at proper timing according to a third aspect of the invention the semiconductor integrated circuit has the clock terminals and the clock wiring lines for inputting the clock signals from outside the clock signals are given to the first to third ff groups in the hard macro accordingly the clock signals can be given at any given timing and the optimum time control can be totally performed according to a fourth aspect of the invention the semiconductor integrated circuit has the timing supplying unit for giving a.