description is presently contemplated as the best mode of carrying out the present invention this description is not to be taken in a limiting sense but is made merely for the purpose of describing the principles of the invention the scope of the invention should be determined by referring to the appended claims fig1 shows a block diagram of a conventional system for testing scan based integrated circuits using an ate the system 101 includes a tester or external automatic test equipment ate 102 and a circuit under test cut 107 which contains scan chains 109 the ate 102 applies a set of fully specified test patterns 103 one by one to the cut 107 via scan chains 109 in scan mode from external scan input pins 111 as well as from external primary input pins 113 the cut is then run in normal mode using the applied test pattern as input and the response to the test pattern is captured into the scan chains the cut is then put back into scan mode again and the test response is shifted out to the ate via scan chains from external scan output pins 112 as well as from external primary output pins 114 the shifted out test response 104 is then compared by the comparator 105 with the corresponding expected test response 106 to determine if any fault exists in the cut and indicates the result by the pass fail signal 115 in the conventional.