at the porous silicon layer the porous silicon may then be selectively etched off leaving a uniform silicon layer fig1 is a drawing illustration of a layer transfer process flow in another alternative of the invention u201c layer transfer u201d is used for construction of the underlying circuitry 814 102 is a wafer that was processed to construct the underlying circuitry the wafer 102 could be of the most advanced process or more likely a few generations behind it could comprise the programming circuits 814 and other useful structures and may be a preprocessed cmos silicon wafer or a partially processed cmos or other prepared silicon or semiconductor substrate wafer 102 may also be called an acceptor substrate or a target wafer an oxide layer 112 is then deposited on top of the wafer 102 and then is polished for better planarization and surface preparation a donor wafer 106 is then brought in to be bonded to 102 the surfaces of both donor wafer 106 and wafer 102 may be pre processed for low temperature bonding by various surface treatments such as an rca pre clean that may comprise dilute ammonium hydroxide or hydrochloric acid and may include plasma surface preparations to lower the bonding energy and enhance the wafer to wafer bond strength the donor wafer 106 is pre prepared for u201c smartcut u201d by an ion implant of an atomic species such as h ions at the desired depth to prepare the smartcut line 108 smartcut line 108 may also be called a layer transfer demarcation plane shown as a dashed line the smartcut line 108 or layer transfer demarcation plane may be formed before or.