203 and the sti 102 as shown in fig3 b the dummy gate 204 the insulation film 203 and the silicon substrate 101 in the region where sti is to be formed are then removed by lithography and rie reactive ion etching consequently the active area aa is determined as shown in fig3 c an insulation film is buried in the region where sti is to be formed at this time a surface of the insulation film is flattened by cmp chemical mechanical polish the sti 102 is thus formed as shown in fig4 a the dummy gate 204 is removed when the insulation film 203 is used as the tunneling dielectric film 103 it remains as the tunneling dielectric film 103 when the insulation film 203 is not used as the tunneling dielectric film 103 the insulation film 203 is removed temporarily and then the tunneling dielectric film 103 is newly formed further a polysilicon film 205 serving as a material for the floating gates fg 1 and fg 2 is deposited on top and side surfaces of the sti 102 and on the tunneling dielectric film 103 the polysilicon film 205 is anisotropically etched by rie as shown in fig4 b the first gate part fg 1 and the second gate part fg 2 are formed so as to be separated from each other on the side surface of the sti 102 and on the tunneling dielectric film 103 the first gate part fg 1 and the second gate part fg 2 are divided.