products wp and accumulated sum of products u03c3wp each multiply unit receives a 16 bit weight w and an 8 bit pixel p to produce a truncated 22 bit product added to the accumulated sum of products u03c3wp from preceding multiply units fig8 shows seven such multiply chips 30 arranged to multiply each of a succession of pixels by a set of weights w 1 through w 35 prestored in the chips to form a pipeline active filter 40 fig9 shows how 35 such active filters 40 may be connected to the train of pixels through line delays 42 to form a filter 50 used to multiply the succession of pixels by a kernel of 35 by 35 weights note that as the products wp are formed they are added to products of previous multiply units in each line of pixels and that the accumulated sum of products for each line is added to the accumulated sum of products of the next line so that the final pixels are weighted by the 35 by 35 kernel of predetermined weights and finally fig1 illustrates how the 35 by 35 pipeline active filter is connected to a data processor 52 through a bus 54 and.