invention the above problem is solved by providing an extra eco cell consistent with the present invention fabricating a high performance eco cell by minimizing capacitance components in drain or source terminals of a transistor when fabricating the eco may be achieved moreover the size of the eco cell in accordance with the related art is increased by a diffusion spacing rule in contrast consistent with the present invention adjacent cells can be isolated through the gate isolation method so the diffusion spacing for isolating cells or transistors from each other is not required so that a desired cell may be obtained within a small size hereinafter an eco cell and a method for arranging and routing the same in accordance with a preferred embodiment consistent with the present invention will be described in more detail with reference to the accompanying drawings fig3 is a top view showing an inner pattern of an eco cell in accordance with a first embodiment consistent with the present invention and fig4 is a top view showing an inner pattern of an eco cell in accordance with a second embodiment consistent with the present invention the eco cell consistent with the present invention is a continuous diffusion type eco cell having a continuous inner diffusion layer and is used in a design using a standard cell library that is the previously fabricated logic function cells are arranged and the eco cell consistent with the present invention is used in re routing an element having the logic function cells eco cell 100 in accordance with.