additionally the configuration of the layers of metal need not be as shown in the figures but rather may vary depending upon the device to be fabricated as previously mentioned the wafer 10 would be received for example as shown in fig1 from the cmos foundry thereafter the wafer 10 will be subjected to post processing fabrication steps although it is anticipated that the post processing fabrication steps will take place in a facility different from the cmos foundry which fabricated the wafer 10 that is not a requirement of the present disclosure turning to fig2 a cmp process back side grinding a reactive ion etch rie a dry reactive ion etch drie or other process is performed on the back side of the wafer 10 to thin the wafer to 50 u2013 100 u03bcm depending on the process selected for thinning the wafer it may necessary to take steps to protect the top side of the wafer turning to fig3 a layer of adhesive 34 is used to attach a first carrier wafer 36 to the back side of the substrate 14 openings not shown may be provided in the carrier wafer 36 and or adhesive layer 34 to provide for cooling of the substrate 12 additionally those of ordinary skill in the art will recognize that depending on the amount of substrate 14 being removed and the process being performed it may be necessary to attach a temporary carrier wafer not shown to the top side of wafer 10 to provide support for the thinning process if such a temporary support is needed it is removed after first carrier wafer 36 is attached as.