shown in table 1 fig8 illustrates an embodiment of the layout structure of column pass transistors connected with sixteen column memory cells wherein sixteen transistors for column memory cells are arranged in two columns with the bit line pairs connected with memory cells section data line pairs are arranged in parallel to the bit line pairs in the commonly arranged active regions of thirty two transistors between the eighth and ninth memory cells mc 8 mc 9 all the transistors arranged in the same row are connected as one also thirty two non shared active regions are respectively connected with bit lines bl or bit line bars blb respectively belonging to their own areas spaces of a predetermined size are formed for gate signals y 1 y 16 of transistors at both sides of the total sixteen column memory cells the layout structure shown in fig8 is similarly formed to that of the first embodiment of the present invention described above so that repeated descriptions will be omitted it is preferable that the contact lines should be arranged to make a short contact between the active regions and bit lines or section data lines on the other hand dummy cell arrays are positioned between the layout space of transistors and memory cells 0052 fig9 illustrates an embodiment of the layout structure of nmos column pass transistors connected with thirty two column memory cells in fig9 the section data line pairs are arranged in parallel to the bit lines in each space having described specific preferred embodiments of the invention with reference to the accompanying drawings it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by one skilled in the art without departing.