and operation on the bus slave input control signal and the bus master output control signal a counter 20 which receives and counts the signal output from the and gate 10 for a period enabled by the input clock signal a comparator 30 which compares the count value from the counter 20 with a prestored count value and a pre counter 40 which updates if necessary and stores the lower count value from the counter 20 the period enabled by the input clock signal i e the enabled time represents the period in which the logic levels of the bus slave input control and the bus master output control signals are equivalent as shown in fig4 a and 4b the operation of the atm cell bus monitoring apparatus will next be explained first an and logic operation is performed on the bus slave input control signal and the bus master output signal the logically added signal is counted by the counter 20 for the enabled time if noise or jitter is generated due to circumstances of the internal or external environment while the counter 20 counts the counter 20 resets and restarts counting the logically added signal the count value of the counter 20 is stored in a memory device not shown and input to the comparator 30 which compares the received count value to a prestored count value namely the prestored count value is a count value of a period necessary for the atm switching system to transmit or receive an atm cell via the atm cell bus and is stored in.