low phase noise in the overall pll circuit output signal at those frequencies application_number US 201514680174 A description as illustrated in fig1 in an illustrative or exemplary embodiment of the invention a pll circuit 10 includes a first pll sub circuit 12 a second pll sub circuit 14 and a crystal oscillator xo 16 first pll sub circuit 12 includes a first pll 18 a numerically controlled oscillator nco 20 and a multiplier 22 one input of first pll 18 which is also the input of first pll sub circuit 12 is configured to receive an input signal 24 as will become more apparent from the descriptions below pll circuit 10 is configured to remove the undesirable effects of jitter in input signal 24 pll circuit 10 can be used for example to drive circuitry not shown that requires a low jitter input clock signal an example of such circuitry that requires a low jitter input clock signal or more specifically a low close in phase noise clock signal is dsl circuitry another input of first pll 18 is configured to receive a feedback signal 28 generated by second pll sub circuit 14 a signal input of nco 20 is coupled to the output of first pll 18 a control input of nco 20 is coupled to an output of xo 16 via multiplier 22 xo 16 is a free running fundamental mode oscillator that generates an oscillator signal 26 an input of multiplier 22 is coupled to the output of xo 16 that provides oscillator signal 26 the output of.