in fig2 a a substrate 26 of silicon for instance is prepared step 2 as shown in fig2 b the inter layer insulation layer 3 of silicon oxide for example is deposited about 400 nm in thickness on the substrate 26 the cvd method for instance is used at the deposition step following this contact holes 13 are formed with generally used lithographic and etching techniques during these steps since the element underlying the inter layer insulation layer 3 is the flat substrate 26 the surface of the inter layer insulation layer 3 is also flat step 3 as shown in fig2 c a barrier metal film consisting of a tin film of 10 nm and a ti film of 10 nm for example and a w film of 300 nm for instance are formed such that the contact holes 13 are filled up with these films the cvd method for instance is used at this step following this the w film and the barrier metal film on the inter layer insulation layer 3 are removed by the cmp method whereby the contact plugs 12 filling the opening portions are obtained step 4 as shown in fig2 d the inter layer insulation layer 3 is further deposited and then patterned thereby forming wiring.