i all the voltage islands that use l i are selected and a rectangular region r is created by drawing the bounding box surrounding these islands step l 4 in fig4 obviously to reduce the number of voltages islands it is advantageous to merge all the islands at voltage level l i into one merged island having a shape r unfortunately r may overlap with other islands thus making the floorplan infeasible additionally creating a merged island having a shape r significantly increases the area overhead as there can be significant dead space therein the loop l 7 to l 18 in fig4 resolves the aforementioned problems by recursively subdividing region r into smaller regions together with island level floorplanning to better describe the merging algorithm fig5 illustrates an example that provides a step by step explanation of the island merging process fig5 a shows an instance of a section of the initial floorplan of a chip image as shown in step l 4 of fig4 the initial rectangular region r is the external bounding box of fig5 a because it overlaps with an alien island u03c0 a which uses a different voltage level i 2 creating a merged island with the size of this bounding box is not feasible additionally such a solution will also contain a significant amount of dead space code l 6 to l 18 in fig4 is used to.