vmid applied to both plates of c y when y is low and zd is high therefore the leakage resistor r yl across c y has no effect on the voltage across c y in the integration phase with y low the senex node is connected to vssa the short circuit across c y will make integrator saturation even deeper and no fold back anomaly will occur in order to protect the vmid voltage source from an overpressure short circuit resistors r r 3 are provided in integrator 40 shown in fig3 resistor r 1 is placed between switch sw 2 and vmid resistor r 2 is placed between switch sw 4 and vmid resistor r 3 is placed between switch sw 7 and vmid the values of the resistors are chosen in such a way that the average dc current leak from vmid to vssa is always below 100 microamps at the same time the rc time constant is reasonably small so that first stage integrator 40 will settle as required in order to demonstrate the automatic fold back suppression a simulation of circuit operation was performed using hspice software the results are illustrated in fig7 a and 7b and fig8 a and 8b fig7 a and 7b are an example of the.