performed when violations are detected at lha 340 level the violations 370 are directly reported to hdl report database 390 the violations 370 detected at sha 350 level are first back referenced 380 to lha 340 for the purpose of identification of the violation in the logical representation the error is then reported to the hdl report database 390 the violations 370 detected at fgna 360 are first back referenced 380 to the back reference stage of sha 350 and then back referenced to lha 340 stage this allows for the identification of the error also in the higher levels namely the structure and the logic levels allowing for an easier correction of the error detected directly at the hdl level the error is then reported to hdl report database 390 referring to fig4 the process is schematically described the process begins with a hdl 410 that goes through a synthesis process 420 the result of the synthesis is a gate level design 430 the gate level design is then analyzed 440 and if errors are found design changes take place 450 this process may be a repetitive process until such time where the design is error free the advantage of the proposed system and method is in the fact that all the user intervention is done at the highest.