chain 620 data output y does not undergo a full voltage transition as in fig2 instead during the time between transitions 704 and 708 y is driven as follows due to the substantially low voltage on y_ resulting from transition 704 pmos transistors 616 and 622 are almost completely activated while nmos transistors 618 and 628 are almost completely deactivated at the same time the relatively strong logical 1 being driven on selector input s results in the substantially complete deactivation of pmos transistor 624 and the substantially complete activation of nmos transistor 626 because pmos transistor 624 has been completely deactivated transistors 622 and 624 exert essentially no influence on data output y partially activated transistor 616 drives y towards a logical 1 at the same time partially deactivated transistors 618 and 628 as well as completely activated transistor 626 drive y towards a logical 0 because the drive towards logical 0 is substantially stronger than the drive towards logical 1 data output y will take a voltage close to but not equal to a logical 0 at transition 706 the connection between transitions 704 and 706 is shown by arrow 712 transition 708 occurs when pmos transistor 610 is activated and nmos transistor 612 is deactivated driving the voltage of signal y_ down to a full logical 0 as a result of this change in y_ transistors 616 and 622 become.