the present invention the interfaces of the signal processors 20 and 21 each include a type selector 200 a simplex duplex selection gate circuit 201 and a time slot selector 202 such a signal processor structure is provided in common for the n signal processors when a select signal sa is input to the simplex duplex selection gate circuit 201 if the select signal sa is logic 1 simplex is selected and if the select signal sa is logic 0 duplex is selected then when the time slot selector 202 receives a select signal sb it selects either the first or the second time slot in the frame signal which is transmitted by the communication channel device 1 a a desirable circuit can be employed as the time slot selector 202 as an example resistors are arranged in two stages and when sb 0 the first time slot ts 1 if there are a ts 1 and a ts 2 is output while when sb 1 the last time slot ts 2 if there are a ts 1 and a ts 2 is output in the embodiment in fig3 since the select signal sb 1 the 0 signal processor 20 selects the first of the two time slots and the 1 signal processor 21 selects the last of the two time slots in addition in fig3 in order to change the simplex duplex switching system so that it can handle a simplex configuration upon receipt of the select signal sa 1 the simplex duplex selection gate circuit 201 regards the output of the time slot selector 202 as being valid furthermore in this embodiment the time slot selector 202 of the 0 signal processor 20 selects the first time slot while the time slot.