173 and 171 are kept at an u201c on u201d state for the pulse width of the pulse signal and are turned off after the pulse width in one embodiment the pulse signal is generated at a rising edge of the oscillating signal as a result the transistors 173 and 171 are not turned on until a next pulse signal is generated accordingly during the standby mode only a relatively small current may be provided to the memory device fig2 is a schematic block diagram of a voltage regulator circuit 20 in accordance with another embodiment of the present invention referring to fig2 the voltage regulator circuit 20 is similar to the voltage regulator circuit 10 illustrated in fig1 except that for example an active mode voltage regulator 25 replaces the active mode voltage regulator 15 in fig1 specifically the active mode voltage regulator 25 may include an operational amplifier 250 a second oscillator 251 and a charge pump 253 the operational amplifier 250 which may serve as a comparator includes an inverting terminal coupled to a point between the resistors r 1 and r 2 and a non inverting terminal coupled to a reference voltage v ref the second oscillator 251 is coupled between an output not numbered of.