period 6h 6 times the horizontal line duration to generate a delayed field reference pulse dfr fig5 c occurring on line 13 a signal h 4 fig5 d i e a signal at one fourth the horizontal line rate and having a 50 percent duty cycle is also provided the timing logic circuit 26 of fig4 receives the signals dfr h 4 and cs and generates signals dfr cs h 4 and h 4 the signal dfr is applied to a modulator 28 through a shaping circuit 30 and the continuous subcarrier wave sc is applied to the modulator through a phase shifter 32 which delays the subcarrier wave by 9 1 degrees the signals cs h 4 and h 4 are applied to current sources 34 and 36 which are turned off when the respective input signals are high and the outputs of the current sources are applied to a shaping circuit 38 the output fig5 e of the modulator 28 is passed through a harmonic filter 40 and the outputs of the circuit 38 and the filter 40 are combined and applied to an output amplifier 42 when the output signal fig5 f from the amplifier 42 is applied to a waveform monitor operating at field rate and line 13 is selected for display the display is as shown in fig3 a phase shifter 44 is used to shift the phase of composite sync in order to achieve the desired phase relationship with subcarrier it will be appreciated that the invention is not restricted to the particular.