flop 42 a first inverter 44 a second flip flop 46 a nand gate 48 a second inverter 50 a third inverter 52 and a third flip flop 54 the clk inputs of the first second and third flip flops are connected to the clk input of fine resolution delay element 22 inputs clrz of the first second and third flip flops are connected to the clrz input of fine resolution delay element 22 output qz of the first flip flop is connected to input j of second flip flop 46 to an input of first inverter 44 and to an input of nand gate 48 the output of first inverter 44 is connected to input kz of second flip flop 46 output q of second flip flop 46 is connected to output clk 4 of synchronous divide by 8 circuit 36 output qz of second inverter 50 is connected to a second input of nand gate 48 the output of nand gate 48 is connected to the input of second inverter 50 an output of second inverter 50 is connected to input j of third flip flop 54 and to the input of third inverter 52 the output of third inverter 52 is connected to input kz of third flip flop 54 output q of the third flip flop is connected to clk8 output of synchronous divide by 8 circuit 36 fig7 is an enlarged view of halfstep switching logic circuit 38 halfstep switching logic circuit 38 comprises two inverters four and gates one or gate.