as not to unnecessarily obscure aspects of the present invention with reference to fig2 a risc processor 200 communicates with a risc processor bus interface unit 204 via the amba asb bus 202 the risc processor bus interface unit 204 contains an asb slave interface which is described in co pending u s patent application ser no 09 304 034 filed concurrently with the present invention entitled u201c slave interface circuit for providing communication between a peripheral component interconnect pci domain and an asb domain u201d by b lo and a pan assigned to the assignee of the present invention and which is hereby incorporated by reference the risc processor bus interface unit 204 also may include a clock domain handshake circuit which is described in co pending u s patent application ser no 09 186 209 filed nov 3 1998 entitled u201c method and circuit for providing handshaking to transact information across multiple clock domains u201d by b lo and a pan assigned to the assignee of the present invention which is hereby incorporated herein by reference the risc processor bus interface unit 204 is coupled to a memory interface unit 208 via an internal bus 206 the memory interface unit 208 accesses a memory unit 210 a pci interface unit 212 is coupled to a pci device 218 via a pci bus 216 the pci interface unit 212 contains a fifo circuit as described in u s patent application ser no 09 138 943 now u s.