and the anode of d 6 pin p 1 a of sub circuit pft 1 a is connected to capacitor c 6 rload sub circuit ifb pin out u2212 and to node b u2212 with sub circuit pwfm pin clk high buffer amp output pin ga 2 charges the gate of transistor switch q 111 switch q 111 conducts charging capacitor c 10 through nsme pft 1 a from source vbat and storing energy in pft 1 a feedback output pin fbc from sub circuit ifb is connected to sub circuit pwfm pulse width adjustment pin pw 1 sub circuit ifb removes current from pwl commanding pwfm to reduce the pulse width or on time of signal clk after sub circuit pwfm reaches the commanded pulse width pwfm switches output pin clk low turning u201c off u201d q 111 stopping the current into pft 1 a the energy not transferred into regulator sub circuit cp load is released from nsme pft 1 a into the now forward biased diode d 6 charging capacitor c 6 by modulating the u201c on u201d time of switch q 111 the converter buck voltage is regulated regulated voltage is developed across nodes b u2212 and b sub circuit ifb provides the isolated feedback voltage to the sub circuit pwfm when sub circuit ifb senses the converter output nodes b and b u2212 is at the designed voltage current from ref is removed from pm 1 sinking current from pm 1 commands the pwfm to a shorter pulse width thus reducing the converter output voltage in the event the feedback signal from ifb commands the pwfm to minimum output gate drive to.