two or more layers can be made using the same set of process steps advantages of the second embodiment over the first embodiment include 1 more uniform and greater strength of the bond because of greater surface area of the bonding resin 2 critical alignment of the mounted wafer with the base wafer for bonding is eliminated since the resin openings are self aligned with the pass through and 3 reduced void regions in the bond and 4 elimination of the photolithographic steps to pattern the resin disadvantages include 1 critical etch step which when using an etchant gas containing oxygen to penetrate the resin layer at the base of the pass through opening without compromising the conductivity of the subjacent bond pad in a third embodiment of this invention a stack of two interconnected integrated circuit layers is formed by first bonding two silicon wafers and then thinning one of the two wafers thereby eliminating the need for temporary bonding to a separate handler the first wafer is a blank unprocessed wafer and the second wafer has an integrated circuit layer comprising a masterslice layer consisting of active and passive silicon devices and a personalization layer comprising wiring circuitry terminating in bond pads on a top passivation layer in addition the embodiment also illustrates how a multilayer integrated circuit package can be prepared for dicing during stack formation referring to fig1 a first un processed blank silicon wafer 210 is provided an insulative layer 227 preferably silicon oxide between about 500 and 1000 nm thick and a barrier passivation layer 229 preferably silicon nitride between about 50 and 100 nm thick are sequentially deposited on the underside of the wafer 210.