not gate 112 and the output pl1 of the not gate 111 an and gate 115 receives the output iza of the current level monitor circuit 105 and the output izb of the current level monitor circuit 107 a time delay circuit 116 receives the output chg of the voltage monitor circuit 101 and generates an output tm2 34 1 34 after a predetermined time t2 from when it is supplied with the signal that the output chg has become 34 1 34 a time delay circuit 117 receives the output qk of the and gate 115 and generates an output tm3 34 1 34 after a predetermined time t3 from when it is supplied with the signal that the output qk becomes 34 1 34 an and gate 118 generates an output m2b when it receives the output tm2 of the time delay circuit 116 and the output pl1 of the not gate 111 an and gate 119 generates an output m2a when it receives the output tm2 of the time delay circuit 116 and the output pl1 of the memory circuit 108 an or gate 120 receives the output tm3 of the time delay circuit 117 and the output m2b of the and gate 118 an or gate 121 receives the output tm3 of the time delay circuit 117 and the output m2a of the and gate 119 an and gate.