techniques such as chemical vapor deposition cvd sputtering physical evaporation or ion beam deposition referring to fig2 c a pattern of interconnects 227 is defined in the barrier layer 226 utilizing for example standard plasma etching techniques in the preferred process a layer of photoresist is spun onto the barrier layer 226 then exposed and developed to define the desired interconnect pattern the barrier metal layer is then dry etched with a flourine or chloride based plasma which selectively attacks the barrier layer material although this approach removes the attractiveness of self alignment of the barrier material to the contact holes it is completely acceptable in many device applications the interconnects 227 formed by the patterned barrier layer 226 are then coated with an insulating layer 228 preferably pvx which is then planarized as depicted in fig2 d the planarization is preferably implemented utilizing the technique previously described in conjunction with fig1 g and 1h once the upper surface of the insulating layer 228 is planarized via holes can be generated in the layer 228 by etching and a refractory material can thereafter be deposited and patterned forming vias this enables the formation of an additional interconnect layer in a manner similar to that described with respect to the previous embodiment in conjunction with fig1 i in a manner similar to the previously described a vertical multi level interconnect structure can be fabricated referring now to fig3 there is shown in diagrammatic form the processing stages of yet another alternate preferred method for constructing a device in accordance with the present invention once again the description of this alternate preferred method begins with a bipolar transistor device generally designated 300 having contact regions 310 312 and 314 formed in a.