transistor 48a when the voltage on the reference gate exceeds the voltage on the input gate as the voltage at the reference gate approaches the input voltage the reference fet device 42b begins to conduct more heavily and diverts current from the input fet device 42a the effect is reflected in the output of comparator transistor 48a which begins to turn off resulting in a voltage rise at the base of the trigger transistor 60 of the pulse generator 28 as the trigger transistor 60 begins to conduct the intermediate stage transistor 64 and the output stage transistor 68 are turned 34 off 34 and the second intermediate stage transistor 66 and the complementing output transistor 70 begin to turn 34 on 34 considering the propagation delays by the time the complementary transistor 70 is turned on the trigger transistor 60 is saturated in the conducting mode the output of the output transistor 68 is sent back to a timing network 94 to turn on the accelerating transistor 62 to maintain the intermediate stage transistor 64 in the nonconducting state the output of the intermediate stage transistor 66 is coupled through a diode 96 to turn off the trigger transistor 60 thereby resetting it for a new pulse however the timing network 94 maintains the accelerating transistor 62 in conduction the leading edge of the output pulse produced by the output transistors 68 70 of the pulse generator 28 is applied to the ramp switch transistor 82 84 turning them on which reapplies the full 10 volt potential to the ramp capacitor 86 this results in the reapplication of a 10 volt signal to the gate of the reference fet.