each clock signal clock is delayed for a time t d as compared with the rising edge of each c signal but the clock signal clock returns to the off state immediately at the end of each c signal if within a predetermined time period no c signal is received the selection gate 14 selects to directly output the signals transmitted from the wire as shown in the right side of the figure the clock signals clock follow the signals transmitted from the wire by comparison between the first and second waveforms it may be seen that the present invention in addition to what have been described includes an additional advantage that there is no concern for signal set up time or hold time in the present invention the format of data signals is c 1 0 c while the clock signal to receive the data is not on until the start of the second c signal in the preferred embodiment there is a delay of t d so it is even safer so the signal set up time is at least a complete clock of the transmitting side the clock signal returns to off state at the end of the c.