of an address codeword an idle codeword is transmitted a battery saving controller 13 which is essentially constructed of a counter and logic circuit in a well known manner is responsive to clock pulses from clock source 4 to normally generate a periodic power control pulse having a period of 32 bits of the incoming signal equivalent to the duration of each codeword at sychronization intervals this power control pulse activates a power switch 15 to feed power from battery 16 to the high power drain unit i e the front end 2 the radio pager is thus periodically rendered active for the duration of a codeword to permit the preamble detector 5 to detect a preamble and reamains inactive for a period of 15 codewords for power saving purposes if a preamble is detected the preamble detector 5 produces an output which is applied through an or gate 14 to the battery saving controller 13 on the other hand the verification circuit 7 cooperates with the clock recovery and window pulse generation circuit 6 to determine whether the incoming signal is valid if it is the verification cicuit 7 supplies an output through or gate 14 to the battery saving controller 13 in response to a signal from or gate 14 the battery saving controller 13 enables the sync detector 8 to search for a sychronization codeword and whereupon the address detector 9 is allowed to search for a match between a received address codeword and a user 39 s unique codeword stored in the address memory 10 which is implemented by a programmable read only memory if there is a match the address detector 9 will cause a.