word being written by the central processing unit core 14 has as its least significant bit bit0 a 34 1 34 and accordingly the i o clk signal is not suspended fig5 illustrates the manner in which the clock signal to the central processing unit core 14 may be blocked so saving power whilst allowing other circuit elements such as the video driver circuit 10 and the video data memory 28 to continue to communicate via the signal bus such communication allows the video data memory 10 to supply the video data memory 28 and so provide a continuous display output to the user fig6 illustrates the exiting of the suspend mode a keystroke at the keyboard 6 is detected by the user input interface circuit 4 which then issues an asynchronous event signal event1 that is supplied to the suspend controller 20 the suspend controller 20 reacts by removing the bus request signal req and the cpusus signal and then asserting the pseudo bus acknowledge signal ack the action of removing the cpusus signal allows the fast clock signal fclk to again be supplied to the central processing unit core 14 the bus acknowledge signal ack also unblocks the memory clock signal mclk by the bus controller the central processing unit core 14 sees the suspend mode as a single write operation of an indefinite length having exited the suspend mode the central processing unit core 14 is again supplied with a.