lines a 40 59 and memory device 220 3 using 20 address lines a 60 79 each memory device communicates data with packet processor 210 over its own 72 bit data bus dq 0 71 for device 220 0 dq 72 143 for device 220 1 dq 144 215 for device 220 2 and dq 216 287 for device 220 3 a memory system controller 212 within packet processor 210 handles the memory accesses for the four memory banks concurrently a memory process configuration table mpct 214 stores access instructions for different types of processing configurations an example shows one set of tables and two processing configurations illustrating the use of an embodiment in the example including fig3 and 4 five different tables are stored in memory as follows in table 1 the column u201c table name u201d indicates the usage of the table i e u201c l2 fib u201d is a layer 2 forwarding information base u201c l2 acl u201d is a layer 2 access control list u201c ing vlan u201d is an ingress virtual local area network table u201c egr vlan u201d is an egress vlan table and u201c nhop u201d is a next hop table the column u201c table width u201d indicates the number of bits used to store one entry in each respective table while the column u201c table size u201d indicates the maximum number of entries set aside for that table the column u201c mapping u201d shows which memory devices are used to store data for that table e g the entry 1 1 0 1 for the l2 fib indicates that memory devices 220 0 220 1 and 220 3 store the l2 fib entries and memory device 220 2 does not the column u201c mode u201d can be either u201c h u201d.