the sample rate timing clock nr s is actually recovered in the clock tracking loop 220 and the symbol timing clock r s is obtained through division by n for output from clock synthesizer 222 the normal invert if frequency translation signals are procured with respect to the sample clock divided by two it will be appreciated that the above described modulator and demodulator can be provided by an if sampling mechanism accommodating a continuously variable rate operation by software changes thus the preferred embodiments of the modulator and demodulator can be obtained without any hardware changes moreover it will be appreciated that the gear shifting permits maximum image separation of the modulator and demodulator carrier if frequencies which results in a reduction in the complexity of the image rejection filter additionally the use of gear shifting permits maintenance of the sample rate at a factor of four times the if frequency over the entire range of symbol rates to be processed other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure and teachings in an exemplary case representing yet another embodiment of the cvifs technique the overall sample rate would be doubled i e sampling at 8 s s for the highest symbol rate of operation while centering the if frequency at 2r s advantageously this has the effect of permitting easier image rejection albeit at the expense of reducing the maximum rate of operation by half it will be appreciated that rr and aa filters 114 and 202 respectively with slightly different characteristics can advantageously be used e g.