the phase voltage if the lower nfet is turned off too early the phase voltage will remain low being sensed as a logical low or u2018 0 u2019 digital state of the phase voltage this sensed vp state is coupled to flip flop 330 and applied from its q output to the a input 371 of the up down counter 370 at the next pwm pulse which as shown in fig4 begins at the termination of the tristate pulse tristate the contents of the up down counter 370 will be either incremented or decremented depending upon the state of the a input 371 the sensed phase voltage state for a first binary state of input 371 e g u2018 1 u2019 indicating that in the previous cycle the lower power fet was turned off too late the contents of up down counter 370 will be incremented one bit by the pwm pulse for a second binary state of up down counter input 371 e g u2018 0 u2019 indicating that in the previous cycle the lower power fet was turned off too early the contents of up down counter 370 will be decremented one bit by the pwm pulse the resultant count value as output by the respective d2 d1 and d0 outputs 375 376 and 377 of the counter 370 now defines the states of the relay drive inputs 381 391 and.