t of the flip flop circuit 41 reset terminals r of the individual flip flop circuits 41 are served as reset signals with outputs of the comparator 62 of the synchronizing signal separator circuit 6 outputs on the side 34 0 34 of the individual flip flop circuits 41 are input to their own data terminals d and to the trigger terminals t of the flip flop circuits 41 of the subsequent stages outputs on the side 34 1 34 of the individual flip flop circuits 41 serve as binary signals for the counter 4 and are counted up upon each receipt of clock signal from the clock generating circuit 7 output on the side 34 1 34 of the flip flop 41 of the second stage is sent as a clock signal clk to the sampling circuit 8 and to a shift register 9 that will be mentioned later further output of the side 34 1 34 of the flip flop 41 of the final stage is sent to drivers 11 and 13 of the liquid crystal panel 2 as a signal m for switching the drive level of the liquid crystal panel 2 the shift register 9 stores the data in an amount of one horizontal period and shifts the data produced by the sampling circuit 8 according to a predetermined shift clock clk the latch circuit 10 works as a register for temporarily storing the data in the shift register 9 when the data of an amount of one horizontal period is stored in the shift register 9 the data in the shift register 9 is set to the latch circuit 10 in parallel responsive to a horizontal synchronizing signal h sync the shift register 12 is reset by a vertical synchronizing signal v sync produced by.