g4 is arranged to receive an input vertical synchronizing signal by being connected to the third input terminal 3 it is assumed that only the composite synchronizing signals are input in this time since a vertical synchronizing signal is not input from the third input terminal 3 and only the vertical synchronizing signal separated from the composite synchronizing signal is output to the second output terminal 5 via the fourth exclusive or gate g4 as a second case an account of the instance is given in which a horizontal synchronizing h sync signal is input to the second input terminal 2 without an input of a composite synchronizing signal and of a vertical synchronizing signal is input separately to the third input terminal 3 the second exclusive or gate g2 with its one terminal connected to the second input terminal 2 generates an output synchronizing signal according to the input signal from the second input terminal 2 due to grounding of the other terminal of the exclusive or gate g2 when a horizontal synchronizing signal is input to the second input terminal 2 to attain a logic high level an output in logic high level is generated from the second exclusive or gate g2 according to the operating characteristics of the exclusive or as stated above and applied to the base of the fifth transistor q5 through resistance r12 at this juncture the fifth transistor q5 will not operate because the base potential level is logic high and the emitter stays at a logic high level owing to supply voltage vcc so collector voltage in logic high level.