a l1 cache an l2 cache or any other type of cache as shown in fig1 the cache 100 includes two portions a most recently used mru portion 102 and a most frequently used mfu portion 104 in one embodiment of the invention the mru portion 102 of the cache 100 is configured to store blocks i e a block of data that have or had at one time at most one active reference i e there is or was another block referencing the block in contrast the mfu portion 104 of the cache 100 is configured to store blocks that have or had at one time two or more active references each of the aforementioned portions of the cache 100 is sub divided into two sub portions evictable 106 110 and non evictable 108 112 in one embodiment of the invention the evictable sub portions 106 110 of the cache 100 include blocks that have no active references in contrast the non evictable sub portions 108 112 of the cache 100 includes blocks that have one or more active references depending on whether the non evictable sub portion corresponds is associated with the mru portion 102 or the mfu portion 104 of the cache blocks in the evictable sub portion 106 110 may be moved to the non evictable sub portion 108 112 if the block is subsequently referenced i e there is an active reference to the block similarly blocks in the non evictable sub portion 108 112 may be moved to the evictable.