the present invention it is merely necessary to load the appropriate bit of the pattern to be matched into out latch 20x prior to invoking the pattern driven interrupt function in this manner each two bit line pair 14x will carry one input data bit and the appropriate pattern bit to which the input bit should match fig3 illustrates in greater detail pattern driven interrupt logic 15 of fig1 a bit comparator 30x has inputs coupled to bit lines ax and bx from interface 12x the other seven bit comparators which have inputs coupled to the a and b bit lines from the seven other i 0 interfaces are omitted from fig3 for reasons of clarity bit comparator 30x also has an enable input coupled to a bit pcex storage location of pdi control register 16 pdi control register 16 stores a pce bit for each bit comparator each of the omitted bit comparators has its enable input coupled to the appropriate one of the remaining seven bit storage locations of pdi control register 16 as is familiar bit comparator 30x provides one of two indications at its output a first indication if the data values on bit lines ax and bx match and a second indication if the values do not match bit comparator 30x is designed so that if it is disabled by its input from pdi control register 16 it provides the same output as if its inputs ax and bx match the ability to disable selected bit comparators by storing the appropriate control word in pdi control register 16 provides the apparatus with significant flexibility if a four bit pattern is to be matched the remaining four inputs bits.