input terminal 16 thus before lockout v dis transmits a low signal accordingly the nor gate 22 will transmit a high latch enable signal in response to the low wcbr signal input once the appropriate inputs are decoded to change the value of v dis to a high signal the nor gate 22 will continue to transmit a low signal regardless of further low wcbr signals until the output vectors are reset in addition to using other logic units one could choose to enable a lockout mode in response to different inputs in fig5 the test vector decode circuit 10 is once again configured to enable latching in response to a high signal in this embodiment however the enabling signal comes from the output of an and gate 24 furthermore v dis is initially transmitting a high signal rather than a low one thus latching will occur during this v dis state when the wcbr signal is high rather than low in order to lock out further wcbr signals the v dis vector must be changed to low by decoding the proper input values fig6 depicts yet another embodiment wherein the test vector decode circuit 10 is configured to allow latching in response to a low signal output from a nand gate 26.