condition select bit from opcode fig4 shows details of the select logic 200 and 210 the select logic for each element position 400 is controlled by designated bit field of control source vector register 233 corresponding to the respective element each select logic for a given vector element could select any one of the input source vector elements or a value of zero thus select logic units 200 and 210 constitute means for selecting and pairing any element of first input vector register with any element of second input vector register as inputs to operators for each vector element position in dependence on control register values for respective vector elements the present invention could also be used for a one source vector case where source vector 231 is mapped based on control vector register 233 using select logic 200 and results of execution unit 240 are written to destination vector register 234 if the mask bit is not set for a given element this is useful for unary operations such as a negation operation where operations on certain elements are to be disabled and leaving corresponding output vector elements unchanged this is also useful for combining an element re ordering step with other operations fig5 shows the operation of.