invention in the folded architecture a single memory array 20 39 includes memory cells 12 arranged in rows and columns located at each of the intersections of word lines w 0 through w n and complementary bit line pairs bit 0 bit 0 through bit 3 bit 3 again only the first four bit lines are shown in fig7 two columns of dual output reference cells 14 39 are also included in the single array and are addressed through the ref and ref word lines note that the first column of reference cells 14 39 addressed by the ref word line is associated with the bit 0 bit 1 bit 2 and bit 3 bit lines wherein each reference cell 14 39 provides a reference voltage for a corresponding pair of bit lines i e bit 0 is paired with bit 1 and bit 2 is paired with bit 3 likewise a second column of reference cells 14 39 addressed by the ref word line is associated with the complementary bit 0 bit 1 bit 2 and bit 3 bit lines wherein each reference cell 14 39 provides a reference voltage for a corresponding pair of bit lines bit 0 with bit 1 and bit 2 with bit 3 note also in array 20 39 that for each dual output reference cell 14 39 there are two corresponding rows and hence there will be two corresponding addressed memory cells 12 a column of sense amplifiers designated sa 0 through sa 3 is placed at.