itself in a network employing the circuit 10 however an external capacitance is normally connected between node 21 and ground the value of this external capacitance may be adjusted in order to compensate for the parasitic capacitance associated with the bottom plate of c3 so that it will not have an adverse effect on the operation of the circuit 10 thus the switched capacitor circuit 10 will be generally insensitive to bottom plate capacitance effects in a network employing it the lossless discrete integrator ldi and the bilinear transformations are commonly used in deriving a discrete time domain filter from a continuous time domain filter the ldi loss less discrete integrator and bilinear transformations are equ1 where t is the sampling period and z e st in circuits characterized by both the ldi and the bilinear transformations the differential charge voltage relationship for a capacitor is the charge voltage relationship for an inductor that is characterized by the ldi transformation is equ2 where l is inductance the charge voltage relationship for an inductor that is characterized by the bilinear transformation however is equ3 substituting the algebraic identity in equation 4 the relationship in equation 4 for an inductor may be rewritten as equ4 for the ldi transformation comparing the expressions in equations 3 5 and 7 it will be noted that an inductor in the ldi domain equation 7 is equivalent to an impedance element in the bilinear transformed domain comprising the parallel combination of an inductor of the same value l equation 5 and a capacitor having a negative capacitance t 2 4l equation 3 in framing an analysis of the switched capacitor circuit in fig1 it is assumed that the parasitic capacitance associated with the.