and the other being connected to each processor 110 11 m through bus matrix 120 interrupt generation unit 230 also has two ends with one being connected to control logic unit 220 and the other being connected to each processor 110 11 m through at least an interrupt signal line 140 the bus includes a reset line an enable line a clock line a write line a plurality of address lines a plurality of write data lines and a plurality of read data lines fig3 a and fig3 b show the semaphore module register set and the registers included in the semaphore respectively as shown in fig3 a a field 321 is the register name a field 322 is the register type read and or write and a field 323 is the register function semaphore module register set 210 includes a semaphore number register 301 a processor number register 302 a random allocation register 303 an allocated semaphore list register 304 an interrupt semaphore list register 305 an interrupt processor list register 306 an interrupt clearance register 307 and a plurality of allocation registers 310 31 n it is worth noticing that the size and the number of the registers can be varied to meet the different system requirements semaphore number register 301 is for storing the number of total semaphores processor number register 302 is for storing the number of total processors in system 100 random allocation register 303 is for returning the number of a non allocated semaphore after receiving a read operation from any processor 11 m allocated semaphore list register 304 is for storing the bits representing the list of all the allocated semaphores interrupt semaphore list register 305 is for storing the bits representing the list of all the semaphores issuing interrupt signals the.