the operating cycle t 1 ms and the enable time te 10 us the enable time is 1 of operating cycle the consumed quiescent current of the embodiments in present invention may be just 1 of the consumed quiescent current of prior art and the bias current of the failure detector circuit 10 still maintains to iss to guarantee the normal operation of the failure detector circuit 10 accordingly the failure detector circuit according to the embodiments of the present invention may consume much less quiescent current so that improves the circuit efficiency one with ordinary skill in the art should understand the failure detector circuit according to the embodiments may be applied to detect the failure of over voltage over current over temperature or other failure status on the protected circuit correspondingly the output signal s of the protected circuit and the reference signal r which are received by comparator circuit 102 are signals that monitor voltage current temperature or other parameters in the protected circuit fig4 schematically illustrates a circuitry of a delay circuit 40 according to an embodiment of the present invention as shown in fig4 the delay circuit 40 comprises an n bit counter n is a positive integer wherein a clock terminal clk of the counter receives a clock signal with a cycle tc the value of n satisfies td 2n u00d7 tc configured to detect the status of comparative result signal cout during the given delay period td an enabling terminal d of the counter receives the comparative result signal cout a set terminal r 1 of the counter is coupled to an output terminal of an inverter inv an.