to those skilled in the art from consideration of the specification and practice of the invention disclosed herein it is intended that the specification and examples be considered as exemplary only the decoder 240 as shown in fig3 is a conventional address decoder it 39 s inputs are cpu address and control lines when the address and control lines output by cpu 100 on bus 105 matches the pre defined address of cam 150 decoder 240 activates its output signal 145 which directs cam 150 to place it 39 s data on bus 125 hardware register 220 provides a real time indication of changing events for example when h w register 220 is connected to i o port circuitry h w register 220 can provide indication that a u2018 frame u2019 of data has been received this indication is provided by one or more bits changing state in the data which is read from h w register 220 by cpu 100 h w register 220 may also provide supplemental information such as the destination address of the frame just received h w register 220 typically has u2018 destructive u2019 reading characteristics which means that one or more of the data bits read by cpu 100 will change state after the cpu read completes as shown in fig3 in addition to outputting it 39 s data on bus 125 h w register 220 also.