it can be seen that the output signal voutcmp of the comparator 5 results to be the input of a further logic gate type and called and 2 it can also be noted that a latch 22 in this embodiment possesses only one output q 22 negated connected to the gate terminal of the transistor m to the logic gate and 1 and in addition is connected to said logic gate and 2 and in addition possesses two inputs s 22 and r 22 to which are respectively connected said fixed frequency signal clk and said pulse width modulation signal pwm the logic gate and 2 has an output line 8 connected with a time block 7 said time block 7 has an output line 9 connected to said logic gate and 1 when the comparator 5 detects voltage present on the line vcmp that is lower than the reference voltage vref that is the voltage presents at the leads of c b lower than the reference voltage vcmp the comparator 5 places a high value on the output voutcmp and contemporarily when the output q 2 negated of the latch 22 is high and the logic gate and 2 has two high inputs such to place a high value on the output 8 said value present on the line 8 activates the time block 7 that places a high value on the output 9 in this manner there are two high values on the input.