means 210 and outputs the lower address to the output timing adjusting means 205 the output timing adjusting means 205 outputs a ram address to the writing means 212 and the reading means 214 the lower address generating means 202 comprises a counter unit 203 and a lower address selector 204 the counter unit 203 comprises counters 2032 2034 u02dc 203 n u02dc 203 c 1 corresponding to channels ch 2 ch 3 ch 4 ch 5 u02dc chn chn 1 u02dc chc 1 chc respectively the counter unit 203 outputs lower addresses for every two channels to the lower address selector 204 the lower address selector 204 outputs the lower addresses to the output timing adjusting means 205 further the address generating means 223 comprises an upper address generating means 224 a lower address generating means 225 and an output timing adjusting means 221 the upper address generating means 224 outputs a ram upper address to the output timing adjusting means 221 and the lower address generating means 225 outputs a ram lower address to the output timing adjusting means 221 the output timing adjusting means 221 outputs a ram address to the writing means 212 and the reading means 214 the select signal generating means 210 the address generating means 200 and the address generating means 223 serve as an input.