a block or step 102 a block or step 104 a block or step 106 a block or step 108 a block or step 110 and a block or step 112 the block 102 may comprise an integrated circuit or chip design specification gathering step the block 104 may comprise an intellectual property ip existing block gathering step the block 106 may comprise a new block specification writing step the block 108 may comprise a representative or dummy block generating step the block 110 may comprise a development step for generating real register transfer level rtl representations of the new blocks the block 112 may comprise a trial implementation flow step in the block 102 specifications for an integrated circuit or chip design may be gathered in the block 104 information e g register transfer level rtl representations may be gathered for ip and existing or complete blocks specified in the integrated circuit design in the block 106 specifications for new or incomplete design blocks contained in the integrated circuit design specification may be written or generated when the specifications for the new design blocks are complete the specifications may be used to generate representative or dummy blocks e g in the block 108 and to develop final or actual rtl representations for the new blocks e g in the block 110 the generation of the representative blocks and the actual rtl representations may be performed in parallel in general the representative blocks comprise representations of the actual rtl for the new design blocks which has yet to be written in one example the information from the development of the actual rtl for the new design blocks may be used to refine the representative blocks generated in the block 108 in the block 108.