specify more than two processor states the power management controller 120 applies the actual power actions to the processors the power management controller 120 decides which of the states to implement based on factors such as interrupt rate direct memory access dma activity etc for example the operating system 165 may request a sleep state but the power management controller 120 may instead elect to place the processor in a halt state based on the system activity hence if the power management controller 120 identifies a higher system activity the shallower halt state is applied thus the power state requested by the operating system 165 does not necessarily match the actual state of the processor core 110 that is implemented by the power management controller 120 the power management controller 120 also controls the transitioning of the system 100 into a hardware system sleep state independent of the operating system 165 conventional s3 states are controlled by the operating system 165 in the illustrated embodiment the power management controller 120 implements an alternative hardware system sleep state s0a3 that differs from the conventional s3 system sleep state in that both memory contents and communication connectivity are maintained during the alternative sleep state this arrangement decreases the exit latency associated with the s0a3 state as compared to the conventional s3 state the s0a3 hardware system sleep state is tailored for shorter duration sleep events than the conventional s3 sleep state the s0a3 hardware system sleep state is hardware initiated by the power management controller 120 rather than being software initiated by the operating system.