cycle i e after data from a pipeline stage has been saved to an associated register to permit seamless context switches fig5 illustrates a block diagram of a pipeline processor 500 built in accordance with pipeline processor architecture 400 that processes two threads t 1 t 2 in one implementation pipeline processor 500 includes an instruction fetch unit 504 a decoder 506 a register file 508 issue logic 510 a two stage execution unit 512 a re order buffer 514 and a programmable thread allocation controller 516 pipeline processor 500 further includes a first set of registers a 1 a 6 that corresponds to processor thread t 1 and a second set of registers b 1 b 6 that corresponds to processor thread t 2 pipeline processor 500 further includes program counters t 1 t 2 multiplexers 550 and de multiplexers 552 in one implementation during an instruction fetch if stage instruction fetch unit 504 retrieves an instruction to be executed from for example instruction cache 502 instruction fetch unit 504 retrieves instructions in accordance with program counters t 1 t 2 in one implementation program counter t 1 indicates an execution status of processor thread t 1 i e where pipeline processor 500 is with respect to an instruction sequence associated with processor thread t 1 and program counter t 2 indicates an execution status associated with processor thread t 2 during an instruction decode stage id instructions retrieved by instruction fetch unit 504 are decoded during an instruction issue stage is in one implementation the decoded instructions are sent to re order buffer 514 through issue logic 510 re order buffer 514 stores the decoded instructions until the decoded instructions are issued for.