that it would turn on if enabled when the drive strength of the output is detected as needing to be changed by external circuitry not shown a new update value may be stored in drive strength update register 35 of fig2 in the illustrated embodiment this value is a logic one thus a logic one is present at the one input of m 1 and shown as update_val_ 1 in row two of fig4 at timing mark t 6 update signal 95 is activated correspondingly multiplexer m 1 of fig3 is switched to select the update_val_ 1 input the logic one on the input is provided to the input of ff 1 where upon the next rising edge of clock 90 it is latched by ff 1 and fed back to the zero input of m 1 as shown at timing mark t 7 the logic one from the output of ff 1 is also provided to the input of ff 2 and ff 3 at timing mark t 8 of fig4 on the falling edge of clock 90 it is latched by ff 2 as p channel enable_ 1 and provided to one input of nand gate a 1 thus providing an enabling condition for the p channel transistor however since clock 90 is low during this time causing the output of nand gate a 1 to be a logic one the p channel portion of driver circuit 1 x is normally off then on the next rising edge of clock 90 at timing mark t.