demanded to the former then a cover film 148 of a silicon oxide film with a thickness of 50 to 150 nm was formed only on the transistor region as shown in fig1 c it was then annealed for 4 to 20 hours at a temperature between 550 and 650 u00b0 in an argon or nitrogen atmosphere containing more than 50 volume percent of oxygen or hydrogen phosphine ph 3 may be used instead of oxygen or hydrogen however the annealing temperature is preferable to be less than 800 u00b0 c because if the annealing temperature is too high phosphine is thermally decomposed and diffuses within the semiconductor lowering the resistivity on the contrary diborane b 2 h 6 may be used when the impurity region of the resistance is p type while a sheet resistance of the impurity region of the transistor was 20 to 800 ohm sheet that of the impurity region of the resistance was 2 k to 100 kohm sheet by the process above then a silicon oxide film with a thickness of 300 to 1000 nm was formed across the whole surface by a sputtering method as an interlayer insulator 149 this may be a silicon oxide film formed by a plasma cvd method a silicon oxide film having a good step coverage can be obtained by the plasma cvd method especially using.