is charged with the difference u03b4c 2 between the voltage v 6 and the voltage v 8 in the comparison phase f 3 the hall element 1 goes into the second detection state t 2 and the switch s 1 turns off the capacitor c 1 stores u03b4c 1 and hence the voltage v 5 is represented by expression 55 at the same time the switches s 2 and s 3 turn off and the switch s 4 a turns on as a result because the capacitor c 2 stores u03b4c 2 the voltage v 6 is represented by expression 56 accordingly in the comparator 4 the voltage v 5 represented by expression 55 and the voltage v 6 represented by expression 56 are compared with each other and an h signal vdd or an l signal gnd is output next the signal transmission is calculated assuming that a differential output voltage in the output terminal pair of the hall element 1 is vh an in phase voltage is vcm u2248 vdd 2 an element offset voltage is voh a gain of the differential amplifier 3 is g an input offset voltage at the first input terminal is voa 1 an input offset voltage at the second input terminal is voa 2 and an input offset voltage of the comparator 4 is voa 3 the calculation is made based on expressions 53 to 56 described above because the output voltage component of the hall element 1 is reversed in phase between the first detection state t 1 and the second detection state t 2 the element offset component is in phase in the first sample phase f 1 voltages at the respective nodes are represented as.