with large u03b1 dielectric then the dielectric will shrink faster than silicon during cooling down from the elevated temperature of deposition or annealing the active area will experience a tensile force laterally toward the trench as shown in fig1 similarly if the active area is surrounded by trenches filled with u201c small u03b1 u201d dielectric then the dielectric will shrink slower than silicon during cooling down from the elevated temperature of deposition or annealing the active area will then experience a compressive force from the trench laterally as shown in fig1 furthermore if the active area is surrounded by trenches filled with both u201c small u03b1 u201d and u201c large u03b1 u201d dielectrics in a symmetrical manner then the active area will experience tensile stress in one direction and compressive stress in another direction as illustrated in top view in fig1 prior art methods for controlling stress are very complex the process of the present invention provides a simple and effective method for controlling stress in the silicon active area controlling stress provides the ability to enhance device performance e g idsat by enhancing the electron and hole mobility the idsat of an n mosfet can be increased significantly by applying tensile stress along the channel area due to electron mobility increase the idsat of p mosfet can be increased significantly by applying compressive stress along the channel area due to hole mobility increase it is also known that tensile stress can enhance hold mobility but compressive stress is more effective for best cmos performance the n mosfet and p mosfet can be optimized under tensile and compressive stress respectively there are other stress related effects that are desirable e g shallower junction formation for p type under compressive stress large u03b1 dielectrics include dielectrics having an.