using low pressure chemical vapor deposition lpcvd procedures at a temperature between about 520 to 580 u00b0 c to a thickness between about 1000 to 2000 angstroms first polysilicon layer 5 can be obtained using an in situ doping deposition procedure where either phosphine or arsine is added to a silane ambient the doping of first polysilicon layer 5 can also be accomplished by ion implantation of either arsenic or phosphorous into an intrinsically grown first polysilicon layer 4 a capping insulator layer 6 is next deposited on underlying first polysilicon layer 5 using either lpcvd or plasma enhanced chemical vapor deposition pecvd procedures at a temperature between about 300 to 700 u00b0 c to a thickness between about 300 to 600 angstroms capping insulator layer 6 can either be a silicon oxide layer a silicon nitride layer or a composite layer comprised of overlying silicon nitride on underlying silicon oxide at a thickness between about 1500 to 2500 angstroms photoresist shapes 7 shown schematically in fig2 are formed on the surface of eeprom cell 30 defining subsequent gate structures an anisotropic reactive ion etch rie procedure is next employed using photoresist shapes 7 as a mask to define control gate structure 40 as well as initial select gate structures 45 shown schematically in fig3 the rie procedure is performed using c 4 f 8 as an etchant for capping insulator layer 6 cl 2 as an etchant for first polysilicon layer 5 stopping on gate oxide layer 4 after removal of photoresist shapes 7 using plasma oxygen ashing and careful.