minimal threshold voltage variation for next implantation application_number US 22819905 A description fig1 illustrates an exemplary embodiment of a method for reducing threshold voltage variations due to gate length differences a semiconductor substrate is provided preferably a silicon substrate a plurality of mos transistors 12 arranged in arrays are then formed on the semiconductor substrate 10 wherein the heights of the mos transistors 12 are h and the actual length s of the gate s 14 are l ideally the actual length s l of the gate 14 are equal to target lengths furthermore a space s exists between each mos transistor 12 ion implantation step 16 is performed to form a pocket implant region 20 to adjust the threshold voltage vth of the transistor the direction of ion implantation 16 crosses normal vectors of the substrate by an angle u03b1 the mos transistor 12 utilized as a shield for ion implantation efficiently preventing the ion implantation regions approaching the edge of the gate 14 of the mos transistor the the threshold voltage vth of the transistor with ion implantation is represented by the following formula i wherein a b and c are constant and a and b are both greater than zero moreover a u00d7 l u2032 represents the impact of the threshold voltage by gate lenth and b u00d7 s u2212 h u00d7 tan u03b1 means the.