to n 1 and then loop back to 0 and start over in another embodiment the byte alignment logic in the pld core determines that the byte boundary should be slipped but not by how much and raises control signal 148 bslipcntl high once control logic 243 253 etc responds to that signal by causing barrel shifter 242 252 etc to slip the byte boundary by one bit if one bit of slippage is not sufficient the byte alignment logic in the pld core will continue to detect misalignment and will again raise signal 148 high so that control logic 243 253 etc will again cause barrel shifter 242 252 etc to slip the byte boundary by one bit this will continue iteratively with the byte boundary slipping one bit per cycle until the misalignment is completely eliminated the foregoing examples apply to the case where the data bus is ten bits wide by changing the widths of registers 241 251 and programming the appropriate limit for the counter in any embodiment in which the counter is used as described above busses of any width can be used because receiver 200 is part of a pld it is designed to allow use with other signaling formats therefore a respective multiplexer 245 255 etc is provided between output register 244 254 etc to allow selection of the data in register 244 254 etc or e g data 246 256 etc from another serial data receiver not shown in receiver 200 dynamic phase aligner 121 122 etc preferably is formed from a phase locked loop u201c pll u201d such as digital phase locked loop u201c dpll u201d 221 222 etc together with a single pll 260 which cooperates with all of the dplls providing the eight phase delayed clock.