in any given u201c bit time u201d defined here as that period of time between the rising edge of p n and the falling edge of p n 1 either a n or b n will pulse high depending on the state of d n while all the other ax and bx x u2260 n remain low the and gates 62 and 64 can be straightforward cmos logic implementations or can be more elaborate constructions in reference also to fig1 biasni and biasn 2 are controlled such that the pulses on nets a 0 2 and b 0 2 in fig1 are all the same width the u201c duty cycle control u201d circuit 43 controls biasp such that the duty cycle at p 2 and by extension at p 0 and p 1 is substantially equal to 50 fig2 is a circuit diagram 44 c illustrating one exemplary embodiment of feedback circuit c according to the present invention the loop dominant pole is set by c f 70 other methods of compensation are possible this feedback circuit 39 s stable operating point is when the time averaged currents i 0 i 1 and i 2 are all equal when equal this means that the signal pulse widths on an and bn n 0 1 2 are all equal this is the desired condition by including cascade transistors 72 and 74 connecting to biasnc and biaspc systematic current mirror gain which can result in phase errors in p 0 2 is reduced the voltage on biasnc and biaspc is nominally vdd 2 but other voltages can be used with good results it will be apparent to one skilled in the art after reading the present application that circuits other than.