i e w x 1 and then passes the transaction with adjusted address window to the next bridge port the exception is for transactions that enter the bridge for the w 0 address window which are mapped to the device 39 s local internal memory when one device wishes to send data to another device in the ring the cpu of the initiating device selects a cpu of a target device the initiating cpu then determines which port left or right that it needs to interface with in order to reach the cpu of the target device assuming n devices in the ring the initiating cpu then selects a memory window 0 to n u2212 1 and its corresponding memory address on the nt port for the desired target device finally the initiating cpu begins a desired memory transaction e g read or write data to the cpu of the target device using the nt port memory address fig5 is a diagram showing exemplary memory address translations between the respective pcie bridges of three devices 10 e 10 g connected in the ring topology of the present invention for example suppose a ring supports 8 devices each bridge would need at least 8 memory windows in its nt port setup as illustrated in fig5 each window is a relative location to a device on the ring for example device.