245 _ 3 are coupled to level 2 data cache 250 level 2 data cache 250 is coupled to main memory 270 through system bus 260 fig3 illustrates the use of multiple program micro caches in accordance with one embodiment of the present invention as explained above when multiple threads share a single program cache program instructions in the program cache for a first thread may be replaced while the processing core is executing a second thread in accordance with the principles of the present invention multiple program micro caches are used simultaneously to reduce the replacement of program instructions in multithreaded processors multithreaded processors generally switch execution between a limited number of u201c active threads u201d in some embodiments of the present invention a processor system would include a thread program micro cache for each active thread however for embodiments of the present invention that support a large number of active threads the plurality of thread program micro caches can be shared because some program instructions are used by many threads the embodiment of fig3 includes a global program micro cache for example bios basic input output system instructions are likely to be used in many threads in operation if both a first thread and a second thread use the same instructions it is less likely that instructions needed by the first thread is replaced while processing core.