is high when the clock signal is low the output state remains unchanged each latch introduces a phase shift of 0 5 clock cycles in this embodiment pulses in the signal output by xor gate 106 have a nominal duration of one clock period pulses output by xor gate 105 vary in duration from 0 5 to 1 5 clock cycles advantageously critical timing paths through the circuit exhibit similar propagation delays this is achieved by ensuring that signals pass through the same number of bistable devices the circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together as they would in an integrated circuit implementation using bistables or other components having characteristic properties similar to those required of latches in this construction in place of the latches would achieve a similar purpose but at the possible cost of occupying a greater surface area in an integrated chip implementation similar replacement of the d type bistables by circuits having the requisite characteristics would be evident to a person skilled in the art example signals at selected points in the circuit shown in fig4 are shown in fig5 the signals shown are a an example clock signal and b an example data signal followed by c the q201 output signal from d type 201 d the q202 output of d type 202 e the q3 output of latch 203 f the q204 output of latch 204 g the phase signal output from xor 105 and h the reference signal output from xor 106.