all in the opposite on or off condition from the one state both states are stable and neither flip flop branch conducts absent an applied direct current voltage to read the cell 32 a row address signal is applied to a row address decoder causing the word line 38 of the addressed row to go to a high logic state as a result the nodes 56 and 66 for the cells on the addressed word line couple to the local bit lines 34 and 36 the data in the cell pulls one of the bit lines 34 or 36 lower the differential signal between the bit lines 34 and 36 is then detected if the cell is in a one state then the transistor 58 is off and transistor 60 is on after the word line 38 goes high current flows from the bit line 18 through the transistor 68 and 60 to the v ss or ground node 74 as a result the bit line 36 becomes lower in voltage than the bit line 34 and this differential condition is detected as a logic one state if the cell stores a logic zero state current flows through the transistors 54 and 58 to v ss or ground 74 as a result the bit line 34 becomes lower than the bit line 36 the data stored in the cell 32 is unaffected by the read operation the bit that is read out onto the bit lines 16 and 18 is conveyed to a data bus 27 shown in fig1 from the data bus the bit is transferred to a sense amplifier 28.