clk1 next pulses low this 34 1 34 data bit will be transferred to the drain d1 34 39 and to the gates g2 34 39 and g3 34 39 of the transistors t2 34 39 and t3 34 39 this will open gate g3 34 39 so that the voltage of the drain d3 34 39 drops to zero and this value appears at the intermediate node int at the interface between the module 15 and the module 17 that comprise the circuit in fig8 this performs the standard bit inversion operation if a 34 0 34 data bit arrives at the source s1 34 39 of transistor t1 34 39 when the clock source clk1 next goes low this 34 0 34 data bit will be transferred to the drain d1 34 39 and to the gates g2 34 39 and g3 34 39 of the transistors t2 34 39 and t3 34 39 this will open gate g2 34 39 so that the voltage at drain d2 34 39 at the intermediate node int and at gate g7 34 39 becomes equal to v cc this opens gates g7 34 39 and forces the voltage at drain d7 34 39 to ground potential thus reproducing.