or voltage coupling element 224 additionally it should be understood that the inverter circuits illustrated in fig2 and 3 may be replaced with other logic functions such as a nand and nor functions and are not limited to the inverter logic function referring back to fig2 or 3 when the signal at the in 1 terminal 202 is high typically representing a logical 1 the p channel transistor 210 is turned off and the n channel transistor 212 is turned on in such an embodiment a current path is established from the inner signal node 226 and the v ss voltage terminal 208 such as the ground voltage terminal with the n channel transistor 212 conducting the voltage on the inner signal node 226 is low thus providing a low voltage level as an input to the second inverter 240 when the low voltage signal is provided to the second inverter 240 the p channel transistor 214 turns on and the n channel transistor 216 turns off when the p channel channel transistor 214 is conducting a current path is established between the supply voltage v dd terminal 206 and the output out 1 terminal 204 and the current increases the voltage of the output out 1 node to approximately the v dd value thus with a high level input signal at the in 1 terminal 202 the buffer circuits 200 and 300 generate a high level output signal at the out 1 terminal 204 in a steady state the body voltage 218 of the p channel transistor 210 will increase approximately.