this is the case then this intra level dielectric should be coated with another insulating material such as sio 2 sin sion or the like in the preferred embodiment the wafer surface is planar after the construction of conducting layer 44 this planarization may be achieved through chemical mechanical polishing cmp or other method commonly in use for ic manufacturing fig4 shows the formation of a cavity 51 in which the mems resonator or filter will be constructed the cavity material 52 is first deposited by a means such as plasma enhanced chemical vapor deposition pecvd or other method e g sputtering spin on etc that keeps the temperature below t max in the preferred embodiment the cavity material should be a layer or set of layers of an insulator which will not be etched by an oxygen plasma such as sio 2 sin sion or the like the cavity 51 is patterned by any typical method such as reactive ion etching rie or wet chemical etching in fig5 a layer of sacrificial material 61 is deposited and patterned to expose anchor points 62 the space occupied by sacrificial layer 61 will later form the gap between the input or output electrodes and the resonating member of the mems resonator or filter as such sacrificial layer 61 should be made the same thickness as the desired gap spacing we propose the use of carbon based materials that can be easily removed.