34 divide by n 34 circuit and which stops pulse synchronizer 22 it will be appreciated that the counters in delay circuit 21 are counting at the rate of n times f whereas counter 24 is only counting at the lower rate of f therefore the effect of delay circuit 21 is to effectively delay receipt of a notch pulse from channel two by pulse synchronizer 20 only a few percentage of a revolution of shaft 10 of fig1 however this is sufficient and effectively allows n number of starting points for starting the recording of the first pixel of the next track for example if channel one of optical encoder 6 has sixteen times the number of opaque lines and transparent portions as the desired recording frequency f the length of time ordinarily consumed by recording one pixel is divided into sixteen parts the beginning of each of which the recording of that pixel can be initiated by the circuit of fig2 referring now to fig3 there is seen a schematic of a typical suitable circuit for performing the functions described in connection with the block diagram of fig2 the resistances shown in fig3 can all be suitably selected to have a value of about 1 000 ohms all integrated circuit components depicted in in fig3 can be obtained from either texas instruments or fairchild corporation under the following items numbers pulse synchronizers 20 and.