12 is not the typical coded value but rather it is a bit vector which is thirty two bits long with a single one of those thirty two bits set to indicate a byte position this byte position indicates the first byte in the instruction the length of which is being measured the instruction is furnished by a rotator 14 in response to the pointer value the rotator 14 uses this value to furnish from the instruction stream fourteen bytes of instruction data aligned at the beginning byte of the first of two instructions being processed the details of the circuitry by which the instruction is furnished by the rotator 14 are described in the patent application referred to above entitled two stage window multiplexors for deriving variable length instructions from a stream of instructions the instruction data is transferred by the rotator 14 to a flip flop 15 used in the circuit 10 to provide an appropriate timing delay the instruction data is then transferred to a decoder 16 which begins the translation of the information contained in the instruction the decoder circuit 16 includes a number of programmed logic arrays which look at the various elements of the fields of the instruction and provide useful data the method by which this is accomplished is not the subject of this patent and therefore is not detailed here u s patent application ser no 07 823 881 now abandoned entitled microprocessor with apparatus for parallel execution of instructions e grochowski filed jan 23 1992 and assigned to the assignee of the present invention describes in detail the circuitry and operation of the decoder.