through the input terminal 4 for selecting the scan paths 1 to which the clock signal u03c6 2 is to be applid this selection operation is identical with the selection operation already described with reference to fig5 during the test the clock signals such as shown in fig1 2 are applied so that the clock signal u03c6 1x and the clock signal u03c6 2 which is the output of the selected and gate 13 are coupled to the selected scan paths 1 the test data signal s t is applied through the input terminal 4 for carrying out desired tests the testing operation is essentially the same as the one in the circuit shown in fig1 during the normal mode of operation the clock signals u03c6 1 and u03c6 3 are maintained high as shown in fig1 3 this causes the clock signal u03c6 1x to be at a low level so that no scan paths can operate the test mode signal tm is at a high level to render the transistors 3 conductive accordingly necessary connections are made between the successive circuit blocks 2a 2b 2n and the normal operation can be performed the low level clock signal u03c6 1x does.