parasitics are advantageously used herein thus if a large inductor was integrated on chip then the dominating inductance parasitics would become negligible and in fact would allow a reduction in package size reducing cost the implementation shown below can provide the improved impedance matching along with enhanced common mode emi rejection and filtering within the same package aspects of the present invention include the usage of series elements flow through routing and distributed esd stages with respect to series elements inductance presents high impedance at high frequencies and fast pulse edge rates esd event limiting current and voltage to the dup and the resistance drops or attenuates a high voltage at high current reducing the voltage observed at the dup at low signal currents during normal operation the resistance creates some signal attenuation in the pass band reducing available signal but at acceptable levels within the interface devices recovering sensitivity or transmit level requirements such that the overall system still meets signal integrity requirements with respect to flow through routing packaging bondwires don 39 t hinder esd protection they help specifically packaging bondwires can be used as is shown in fig3 b to tune the transmission line 39 s impedance i e cancel effect of esd stage capacitance which improves signal integrity by making the dut more transparent distributed esd stages multiple stages in particular based upon the flow through approach as described above the present invention uses a different approach with respect to pcb traces than conventional in particular rather than having pcb traces run physically under and electrically parallel to the esd device.