of one embodiment of a switched mode power supply in accordance with the teachings of the present invention all of the circuitry shown in this schematic is used to control the switching of the power mosfet 2 the timing of the switching is controlled by oscillator 5 oscillator 5 generates three signals clock 10 dmax maximum duty cycle 15 and sawtooth 20 the rising edge of clock signal 10 determines the beginning of the switching cycle as shown in the illustrated embodiment when clock signal 10 is high output latch 90 is set which results in a control signal output from output latch 90 to enable power mosfet 2 to begin conducting the maximum conducting time is determined by dmax 15 signal being high when dmax 15 signal goes low latch 90 is reset thus causing the control signal output from latch 90 to disable power mosfet 2 from conducting the intrinsic current limit is to the first order proportional to the voltage on node 22 as stated earlier the goal of the invention is to generate an intrinsic current limit proportional to the time elapsed in the switching cycle the saw tooth waveform 20 can be used to perform this task as the base voltage of npn transistor 30 rises the emitter voltage also rises at the same rate thus the current through resistor 25 is linearly increasing with time elapsed during the switching cycle after mirroring this current through current mirror 40 the linearly increasing with elapsed time current source 27 is derived the current limit threshold 22 is thus proportional to the product of the combination of linearly increasing current source 27 and constant current source 50 with the resistor 17 the voltage on node 37 is proportional to the power mosfet drain voltage because of.