address is sent by a controller 133 to a delay unit or queue to be used to address the cache after the updated value has been written into the cache otherwise the address is sent to main memory to obtain the needed value data is selected for the adder 104 by a multiplexer 135 in addition to unique cache design and prefetching the present invention employs novel zero detection logic the zero detection logic unit zdl 114 detects a zero in the k v data stream and serves as the read signal for the p vfu 110 when a zero is detected a new value from p vfu 110 is placed in latch 118 the ieee 754 1985 standard represents a zero value with the exponent and mantissa fields equal to zero therefore the input to the zdl 114 consists of the mantissa and exponent of the double precision floating point value from k vfu 108 the zdl 114 input is 63 bits wide in one clock cycle the zdl must detect when all 63 bits are zero to insure the correct multiplier for the nonzero data fig5 depicts a cmos implementation of the zdl 114 with a nor gate the.