a pressure of 1 u00d7 10 u2212 7 torr at a substrate temperature of 75 u00b0 c and 25 u00b0 c for gold the gold source and drain electrodes are deposited on top of the organic semi conductor through a shadow mask forming a top contact geometry with a channel length of 58 u03bcm and a channel width of 1 u03bcm an electrical wired bonded on the backside of the p doped silicon wafer forms the gate electrode the field effect transistor produces the current voltage characteristics shown in fig1 it is shown that cpc forms a typical p channel transistor operating in two different modes which are the linear regime where the current follows ohm 39 s law at low source drain voltage and the saturation regime as the source drain voltage increase in the conditions described above cpc shows a high mobility of 2 5 u00d7 10 u2212 1 cm 2 v and a high i on i off ratio of 106 in a third embodiment of the invention as shown in fig1 an oled was fabricated consisting of an indium tin oxide transparent conductive anode on a glass substrate a thin pcvdpap layer as emitter and a ca cathode the indium tin oxide coated glass 5 u00d7 5 cm 2 with a sheet resistance of 15 ohm sq is patterned using photolithography techniques to produce ten segments each.