performed on the data outputted by the first read operation memory controller 120 outputs a command code to multi bit flash memory device 110 to perform a pipeline read operation in response to a read request from a host the multi bit flash memory device 110 detects the memory cells selected by read voltage vrd 3 in response to the pipeline read command in step s 110 memory cells with an msb of 1 are selected from among the selected memory cells and the first read operation is performed on the selected memory cells during the first read operation the memory cells are detected according to respective read voltages vrd 0 to vrd 2 and the detected data are stored on latches in a page buffer not shown following the normal read operation the memory cells with an msb of 1 are detected according to over sampling read operation voltages vfrd 0 to vfrd 2 the data detected according to the oversampling read operation and separated from the data detected according to the normal read operation are stored on the latches in step s 120 once the normal and over sampling read operations in the first read operation are completed the latched normal and over sampling read data are outputted in step s 130 the detected data are determined by the soft decision algorithm of memory controller 120 shown in fig2 separated from the soft decision algorithm of memory controller 120 the second read operation proceeds in the multi bit flash memory device 110 to select the memory cells 140 of fig3 b with an msb of 0 among the selected memory cells in step s 140 during the second read operation the memory cells with an msb of.