of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix the decoder is responsive to entries in the matrices for accessing data in parallel from the memories application_number US 29927002 A description the present invention is directed to a decomposer for turbo code decoding which eliminates the need for turbo decoder duplications it employs matrices herein designated t 1 t 2 p 1 p 2 and f which are embodied in memory arrays or the like the premise of the present invention can be generalized by considering two arbitrary permutations of a set of numbers which represents addresses in n memories where data for processing are stored assume that each memory is capable of storing a maximal number m of words the addresses can be represented in two tables matrices one for each processing stage each table has m rows and n columns and each row represents addresses to be accessed simultaneously during a given clock cycle each column represents the addresses in one memory in accordance with the present invention the addresses are partitioned into groups such that.