as also seen in the diagram the frequency of the output signal s out switches from f1 departure phase to f2 and back to f1 correct arrival phase while maintaining a coherent phase in this example f1 may equal e g 3 5 ghz and f2 may equal d u00b7 f1 e g u215b u00b7 3 5 ghz 437 5 mhz fig4 b shows a time phase graph of the slave ds 120 with the accumulator reset each time a new ftw is applied without the disciplining influence of the master ds 110 during the same period as in fig4 a as seen in the diagram the slave ds 120 may experience a u201c pipeline u201d delay after being switched from f1 to f2 at the departure phase the slave ds 120 may experience another pipeline delay when it is switched back from f2 to f1 the accumulator may be reset after the pipeline delay when the slave ds 120 is switched from f2 to f1 fig4 c shows a comparative view of the time phase diagrams of fig4 a and 4b aligned with respect to each other along the time axis fig4 d shows the comparative view time phase diagrams of fig4 c including a graph that illustrates the influence of the master ds 120 accumulator value to the slave ds 120 phase offset to correct the arrival phase as seen in the upper diagram fig4 d shows the effect of adding a phase tuning word from the master accumulator thus achieving a phase coherent output signal fig4 e shows a time phase diagram that illustrates the disciplining of the slave ds 120 by the.