bits 54 for bit synchronization a sixteen bit pattern 34 c 34 52 and 34 inverted c 34 56 are transmitted to allow the selective call receiver to acquire frame synchronization for decoding the subsequent information blocks at 1200 baud the pluralities of bits 50 and 54 comprise eight bits each referring to fig3 a and 3b the operation of the battery saving routine of the microprocessor of the present invention begins when the selective call receiver is energized 60 i e when the user turns the on off switch on next the microprocessor 16 polls the nonvolatile memory 26 to determine whether a value time1 is stored therein 62 time1 is a value indicating at what time as measured by the real time clock 24 fig 1 the selective call receiver last acquired synchronization if no value for time1 is stored in the memory 26 step 62 the receiver demodulator 12 fig1 is activated and the battery saving routine determines whether synchronization has been acquired with the synchronous signal 64 the battery saving routine operates in a loop until synchronization has been acquired 64 the process of acquiring synchronization may have a different battery saving routine when synchronization has been acquired 64 the value time1 is set equal to the value realtime of the real time clock 24 at the time of synchronization acquisition sync acq 66 which corresponds with the center of interval 36 a counter cnt which counts the number of synchronous signal cycles is initialized to one 68 and time1 is stored in nonvolatile memory 70 the eighteen blocks 34 are decoded in step 72 power consersation may be performed while receiving blocks 34 based on a signal included therein additionally blocks 34 may include information.