5 which may occur in the usb interface 11 and the pc clock can accommodate for example the higher frequency clock signal has a period of 117 u03bcsec in other words the clock generation switch 17 switches the period of a frame pulse signal supplied to the usb side codec 14 from 125 u03bcsec to 117 u03bcsec when the pc 1 starts data transmission in the isochronous mode transmission voice data sequentially store into the fifo memories 101 104 as described before when the fifo memories 104 and 103 become full the clock generation switch 17 starts supplying the normal frequency clock signal to the usb side codec 14 under control of the clock controller 21 as described before if the transmission voice data are stored in the fifo memories 104 to 102 the clock controller 21 switches the normal frequency clock signal to the higher frequency clock signal contrarily when the fifo memories 101 103 become empty the clock controller 21 switches the normal frequency clock signal to the lower frequency clock signal referring to fig3 each of the 16 byte fifo memories 201 204 outputs a full status signal to the fifo status monitor 20 when the fifo memory has stored 16 byte reception.