designated 18 the output of the pilot cancellation circuit 10 which is essentially the fm composite with the 19khz pilot component removed provides the other input to the multiplier 18 as well as providing the input to a delay block designated 20 the l r signal is provided at the output of the delay block 20 while the l r signal is provided at the output of the multiplier 18 the magnitude detector 12 and pll 16 are described in greater detail in patent applications g 1784 and g 1804 respectively assigned to the assignee of the present invention and are incorporated herein reference may be had thereto for further details if desired the magnitude detector 12 as well as the pilot cancellation stage 10 are switched capacitor circuits which are controlled by clock signal obtained from the pll 16 the pilot cancellation stage 10 is a switched capacitor summer with a gain of unity as shown in fig2 the stage 10 comprises an amplifier 22 and feedback capacitor 24 with an equivalent resistor formed by capacitor 26 and switches 28 30 the outputs of switched capacitor networks generally designated 32 and 34 are summed at the negative input of amplifier 22 the dc input designated vmag.