first trench 42 and second trench 44 and the surface 32 surface are coplanar this forms a gate dielectric layer 46 in the first trench 42 and a sti 48 in the second trench 44 directly contacting the gate dielectric layer 46 in which the top surfaces of the sti 48 gate dielectric layer 46 and substrate 32 are coplanar if the oxide layer 36 is removed along with the patterned mask 40 during the aforementioned cmp process another oxidation process could be conducted selectively to form another oxide layer 64 atop the substrate 32 sti 48 and gate dielectric layer 46 this oxide layer 64 will be used as gate dielectric layer for other low voltage devices this completes the fabrication of a semiconductor device according to a second embodiment of the present invention referring to fig1 according to an embodiment of the present invention after stis are formed as in fig5 or fig9 fabrication of transistors could be carried out in both high voltage hv region and low voltage lv region for instance a gate structure 52 could be formed on oxide layer 64 of each lv region 50 and hv region 34 in which the top surfaces of the gate structure 52 on lv region 50 and gate structure 52 on hv region 34 are coplanar and the sti 66 on lv region 50 and the sti 66 outside the source drain region 56 of hv region 34 could be formed along with the sti 48 on hv region 34 in this embodiment the fabrication of the metal gates 52 could be accomplished by a gate first process a high.