semiconductor device 100 using the prior art process for forming an air gap in this step a second dielectric layer 210 is deposited onto oxide layer 206 second dielectric layer 210 could be any typical ic chip insulating film deposited by plasma enhanced chemical vapor deposition pecvd or cvd such as for example sio2 siof sicoh sic sicn or porous versions of these as an example of a cu low k dielectrics with k lt 4 0 multilevel wiring technology second dielectric layer 210 could be pecvd sicoh as mentioned previously like numbers indicate similar features and oxide layer 206 of fig2 is similar to oxide layer 106 of fig1 the second dielectric layer 210 forms a sealed air cavity 208 in between interconnects 204 a and 204 b during the process of depositing second dielectric layer 210 some of the second dielectric layer material indicated as 212 is deposited on the interior of cavity 208 this has the adverse effect of increasing capacitance it is therefore desirable to form a sealed air cavity without depositing dielectric material within the air cavity the preferred dimensions of the air cavity 208 depend on the interconnect heights and spacing that is used in modern cmos wiring the dimensions of the depth and the width of the cavity can range anywhere from about 50 nm nanometers up to about 1 um 1000 nm it 39 s most preferable that the depth of cavity 208 exceeds the depth of the interconnect trench bottoms indicated as 205 a and 205 b by an amount approximately 8 to about 12 preferably about 10 of the depth of the trenches 204 a and 204 b so the electric fringing fields are largely contained within the cavity rather.