to 4 is thus completed by the steps described 0178 fig3 is a top plan view showing a memory cell of an sram of the present embodiment fig3 is a section taken along line a a u2032 of fig3 fig3 is a section taken along line b b u2032 of fig3 and fig3 is an equivalent circuit diagram showing the memory cell of the sram of the present embodiment in the sram of the present embodiment as shown the paired local wiring lines l 1 and l 2 cross connecting the input output terminals of the flip flop circuit of the memory cell are formed in different conductive layers as in the sram of the foregoing embodiment 1 in the sram of the present embodiment moreover the upper local wiring line l 2 overlaps with the lower local wiring line l 1 over a wide area and a capacitor element c is composed of the local wiring lines l 1 and l 2 and a thin insulating film a silicon nitride film 42 interposed between the wiring lines specifically the upper local wiring line l 2 is one electrode of the capacitor element c the lower local wiring line l 1 is the other electrode and the insulating film the silicon nitride film 42 is its dielectric film a method for manufacturing the memory cell of the sram of the present embodiment will be described with reference to fig3 38 a and b 39 40 a and b 41 42 a and b 43 44 a and b 45 46 a and b 47 and 48 a and b of the individual figures showing the memory cell manufacturing.