illustrated in fig3 implementation of this multiplexing demultiplexing scheme within existing fpgas 20 and 21 would require the allocation of a portion of the logic arrays 33 and 34 in the creation of the multiplexors 35 and 36 the allocation of logic gates within the logic array for the creation of the multiplexors demultiplexors leaves less of the array available as a computation resource in addition this solution uses the same clock as that of the underlying logic array which limits the communication bandwidth therefore while this solution utilizes fewer input output ports it comes with an associated cost the present invention discloses various hardware fpga pin multiplexing techniques that tradeoff between speed space and complexity of use the invention involves replacing the input output buffers ports on some or all of the fpga pins with special multiplexing input output buffers which synchronously transmit multiple bits of data using a clock which is potentially faster that the clock s used within the logic in the reprogrammable fpga logic array core the virtual pins abstraction of the present invention is a simplified behavioral model for time domain multiplexed fpga pins in this model a multipin is defined as an fpga pin which will be multiplexed l is defined as the level of multiplexing of.