circuit 12 and displayed on the monitor display device 28 processing is slower but the completed image is sharper than in the case of main body display mode fig3 is a block diagram illustrating the first image processing circuit 10 depicted in fig1 in the drawing 32 is a horizontal sampling circuit 34 is a gamma correction circuit 36 is an over sampling circuit 38 is a one pixel delay circuit 40 is a one horizontal period delay circuit 42 is a one pixel delay circuit 44 is a subtracter 46 is an adder 48 is a subtracter 50 52 and 54 are each sample hold circuits 56 is an rgb matrix and 58 is a yuv matrix the horizontal sampling circuit 32 samples the brightness signal y with a 3 mhz clock if pixel signals are being fed at 12 mhz this means that one pixel in four is sampled if there are 640 pixels in one horizontal period 160 pixels are sampled the degree of culling is determined by this horizontal sampling circuit 32 here it is a relatively large cull culled brightness signals pass through the gamma correction device 34 and are converted to 6 mhz in the over sampling circuit 36 the same rate of y output is obtained as with the second processing circuit illustrated in fig4 and described below the sample hold circuits 50 52 and 54 sample and.