u03bcm would be selected if a metal or other highly conductive material is used in the sinker trench a higher ratio e g 3 1 is more desirable other than the relative width of the trenches spacing s 1 between the sinker trench and the active region also impacts the micro loading effect a smaller spacing generally results in reduced micro loading effect in one embodiment the depth of the gate trenches in the epitaxial layer is selected to be close to the interface between substrate 102 and epitaxial layer 104 so that a slightly wider sinker trench would reach through to contact substrate 102 in an alternate embodiment both the gate trenches and the sinker trench terminate within substrate 102 in another embodiment the sinker trench and the gate trenches are formed at different times thought the sinker trench would not be self aligned to the active region spacing s 1 is not a critical dimension advantages of forming the two trenches at different times include elimination of the micro loading effect and the ability to optimize each trench separately in accordance with an embodiment of the present invention a method of forming the power transistor shown in fig1 wherein the sinker trench and gate trenches are formed simultaneously is as follows epitaxial layer 104 is formed over substrate 102 next a masking layer is used to pattern the gate trench and.