the increment signal supplied by clock edge counter 208 is asserted the output signal clk adc 210 of frequency divider 204 may be configured as the sampling clock used by an adc for example adc 124 clk adc 210 may also be fed back to clock edge counter 208 which may be configured to count a specified number of edges of clk adc 210 and output the increment signal to division factor generator 206 at the end of each count clock edge counter 208 may be configured to effectively count one or more than one edge of clk adc 210 at any given frequency of clk adc 210 before issuing the increment signal to division factor generator 206 in one set of embodiments in order to achieve a 50 duty cycle for clk adc 210 frequency divider 204 may be configured to further divide by 2 the signal obtained following the division of f osc by the divide value determined by the m bit address thus f osc may be set to a value that 39 s approximately double the value of fcontrol determined according to the example presented above including equations 3 4 and 5 accordingly the minimum divide value u2018 d u2019 may also be doubled and incremented by 2 at each step for obtaining each subsequent frequency value in alternate embodiments both the rising and falling edges of the f osc signal may be used in conjunction with a half integer divider i e d 2 instead of d and increments of 0 5 instead of 1 providing commensurate results fig3 shows a timing diagram of one example of clk adc 210.