a threshold voltage vtp typically on the order of about u2212 0 2 volts in the present invention to prevent the parasitic pmos fet 150 from turning on the p region 130 of the gate layer 118 is tied a voltage substantially equal to the source voltage vdd a parasitic nmos fet 152 is also formed in the silicon layer 114 with its source sn formed by the n region 124 body bn formed by the p well 128 drain dn formed by the n well 126 and gate gn formed by the p region 130 of the gate layer 118 unlike the parasitic nmos fet 52 described above with regard to fig2 however the threshold voltage vtn of the parasitic nmos fet 152 is not on the order of about 0 2 volts rather because the p region 130 of the gate layer 118 extends a considerable distance over the p well 128 and forms the gate of the parasitic nmos fet 152 the threshold voltage vtn of the parasitic nmos fet 152 is increased by an amount approximately equal to the band gap voltage of silicon which is about 1 0 volts to a value equal to about 1 2 volts now as long as vdd is kept below 1 2 volts the parasitic nmos fet 152 will remain off due to its unusually high threshold voltage vtn of about 1 2 volts the above.