208 210 in the seu hardened latch 200 in fig2 or the seu hardened sram cell 300 in fig3 the pcds are set to low resistance crystalline states as follows first the first and second control modules 212 214 determine the necessary voltage level of set voltage pulses to be applied to the control terminals 410 of the prds prd 1 and prd 2 208 210 based on the logic levels at the state information inputs of the first and second control modules 212 214 for example if the logic level at the latch input terminal vin is at a logic u201c 0 u201d as shown in fig2 and 3 then the set voltage level applied to the control terminal 410 of the first pcd i e prd 1 208 is set to u201c 0 u201d volts plus the required set voltage the voltage pulse shapes e g width time t 2 and amplitude of the set voltage pulses applied to the control terminals 410 are controlled by the first and second control modules 212 214 based on set commands applied to the command terminals of the control modules 212 214 after the set voltage pulses are applied to the control terminals 410 a first set current flows through the first pcd i e prd 1 208 the nmos pull down transistor of the first inverter inv 1 204 and then to ground as shown by the dotted arrow in fig2 and 3 a current sinking device coupled to the vin and vout net may also.