with a processing system 314 that includes one or more processors 304 in various aspects of the disclosure the ms 102 or bs 104 may be implemented with the apparatus 300 examples of the processors 304 include microprocessors microcontrollers digital signal processors dsps field programmable gate arrays fpgas programmable logic devices plds state machines gated logic discrete hardware circuits and other suitable hardware configured to perform the various functionality described throughout this disclosure in this example the processing system 314 may be implemented with a bus architecture represented generally by the bus 302 the bus 302 may include any number of interconnecting buses and bridges depending on the specific application of the processing system 314 and the overall design constraints the bus 302 links together various circuits including one or more processors represented generally by the processor 304 a memory 305 and computer readable media represented generally by the computer readable medium 306 the bus 302 may also link various other circuits such as timing sources peripherals voltage regulators and power management circuits which are well known in the art and therefore will not be described any further a bus interface 308 provides an interface between the bus 302 and a transceiver 310 the transceiver 310 provides a means for communicating with various other apparatus over a transmission medium e g a wireless communication medium in various aspects of the disclosure the transceiver 310 may include rf front ends and one or more rake receivers that will be described in more detail below depending upon the nature of the apparatus a user interface 312 e g keypad touchscreen display speaker microphone joystick mouse touchpad camera may also be provided the processor 304 is responsible for.