bit map contain the byte for the scan line being displayed and also the byte for the scan line located just above it from the opposite field these bytes are subsequently ored to obtain a composite 10 bit byte for display purposes the bit map plane 30 is divided in half on a field basis into an odd half 42 and an even half 44 each half has its own addressing as described above and its own output data register identified as 46 odd and 48 even at circuit level a a single bit map read cycle provides two 10 bit bytes one from each map half as described above the cycle time done using memory page mode is 180 ns at circuit level b consecutive accesses every 90 ns produce bytes from the alternate fields that are operated upon the deflicker and stretch circuitry 50 and 52 respectively under control of a data read control block 54 the data read control block 54 is constructed from fuse programmable logic it controls the operation of the deflicker and stretch circuits 50 and 52 and determines which 10 bit byte is accessed from the data registers 46 and 48 the 34 operation mode 34 can specify normal display mode where the invention does not operate as well as deflicker and stretch mode certain other functions are also performed here such as data blanking and unmasking it will be appreciated that knowledge of the field being displayed and the memory cycle halves 90 ns each are required for operation the deflicker and stretch circuits 50 and 52 also are made from fuse programmable logic these two circuits perform the bit oring that implements the invention the previously mentioned circuit components provide the proper data at the proper time for.