represent specific cells of fig1 and 17 respectively the configuration of each cell of fig1 and 17 somewhat resembles the configuration of this invention according to the configuration of c or fig1 the n layer for vss is arranged around the memory nodes from two directions according to the configuration of d or fig1 the n layer for vss around the memory nodes is continuous around three directions of l shaped driver mos transistors the node capacitance of each memory cell of c and d is 40 pf according to the configuration of c the resistance balance of high resistance elements being formed of polysilicon layers is undesirable according to the configuration of d not only is the resistance balance of high resistance elements undesirable but also the bistable stability of the memory cell is liable to be degraded because the flip flop transistors have l shaped configurations in fig1 the plotted curve e represents a specific cell which is equivalent to a case where the cell of b is provided in a p well of the semiconductor substrate according to the configuration of e where v dh u2267 2 volts the cell is free from a soft error however this cell is subjected to a certain soft error when v dh lt 1 5 volts.