stored in the memories 1202 and 1203 the error detection circuit 1204 outputs error detection data representing that one of max value data d max min value data d min and a division code u03b4 i j in the transmission data input from the input terminal 1201 has an error the error detection data output from the error detection circuit 1204 is stored in an error detection data memory 1206 as described above the transmission data corresponding to one field image data is stored in the memories 1202 and 1203 and the error detection data corresponding to this transmission data is stored in the error detection data memory 1206 the data stored in the respective memories are then read out during read access of each memory new input transmission data and new error detection data are stored in the corresponding memory therefore the memories store the new data in place of the readout data the transmission data stored in the memory 1203 is read out in a fifo order and supplied to the b terminal of a data selector 1207 when the max value data d max or the min value data d min has an error an address generating circuit 1208 outputs to the memory 1202 an address for reading out the data d max or d min in the transmission.