those skilled in the art that the positions of the source 110 and the drain 112 are typically interchangeable fig1 b presents a partial sectional view 114 in accordance with the first embodiment of the present invention a first dielectric layer 116 is deposited onto both the gate poly 108 and the resistor poly 104 the first dielectric layer 116 is a silicide blocking layer that may be made of one or more predetermined oxides fig1 c presents a partial sectional view 118 in accordance with the first embodiment of the present invention the first dielectric layer 116 is partially etched for embodiment using a wet etching process from the gate poly 108 the source 110 and the drain 112 it is however noted that the first dielectric layer 116 remains on the resistor poly 104 fig1 d presents a partial sectional view 120 in accordance with the first embodiment of the present invention a first metal layer 122 is deposited on the gate poly 108 the source 110 and the drain 112 with the first dielectric layer 116 protecting the resistor poly 104 fig1 e presents a partial sectional view 124 in accordance with the first embodiment of the present invention a high temperature process alloys the first metal layer 122 shown in fig1 d into the exposed silicon of the gate poly 108 shown in fig1 d and the exposed silicon of both the source 110 and the drain 112 the result is the formation of a fully silicided thin gate poly 126 a.