devices c f and immediately upon first and second nitride spacers 28 34 as seen in fig1 the depicted polysilicon plugs are separated either by a sequence of nitride spacers and bpsg layer or are separated by a lone nitride spacer due to a misalignment of the aforedescribed first and second masking steps such a lone nitride spacer formed from misalignment is seen upon and vertically rising immediately above first nitride spacer 28 of mos device c and second nitride spacer 34 above mos device f as seen in fig1 an alternative embodiment of the invention process flow taught herein for fabrication of dynamic random access memory structures dram is seen in fig7 through 10 in the alternative embodiment a third mask is required the third mask can be initiated following formation of polysilicon plugs 68 or following the optional step of dry etchbacking n doped polysilicon layer 68 the purpose of the third mask is to open up contacts to p mos devices residing in an n doped silicon well adjacent to a junction with p doped silicon substrate 10 seen in fig1 6 in fig7 a field oxide region 74 is separate from mos devices g and h which reside upon n doped silicon well 72 and have respectively a doped polysilicon gate electrode 76 78 sealed under a fourth nitride spacer 80 82 in contact with n doped silicon well 72 the structure seen in fig6 and 7 has a third photoresist layer 90 applied over bpsg layer 46 n doped polysilicon layer 68 and n doped polysilicon layer 56 third photoresist layer 90 is aligned with a mask exposed to uv light and is developed so as to form.