shows the programmable gain stage 20 of the invention that consists of 2 capacitor arrays that serve as digital to analog converters each capacitor array is composed of a binary weighted section along with a few additional capacitors the binary weighted section is further composed of 2 stages capacitively coupled together by capacitors 34 and 35 to reduce the capacitor ratios referring to fig3 only a portion of the capacitor arrays will be discussed in details as each of the subsequent following portions is substantially the same an upper capacitor 31 and lower capacitor 33 are connected by a switching device 32 the switching device is inputted with an analog signal a high voltage level and a low voltage level also can be a reference ground the switching device is also inputted with a plurality of digital input signals controlling the internal switches the internal switches not shown serve to connect the upper capacitors 31 and lower capacitors 33 with the input signals by using appropriately sized capacitors within the array a proper digital to analog conversion is achieved this allows the control of the gain and offset of the input signal which in a preferred embodiment provides 8 bits or 256 steps of adjustment the size of the least significant bit in offset adjustment is proportional to the full scale output range which is not affected when the gain is adjusted the programmable gain stage also provides good common mode rejection by switching the bottom plates of the corresponding capacitors in the two capacitor arrays together during an integration phase the charges sampled by the capacitor arrays are integrated to capacitors 37 with the help of an amplifier 36 and switching devices 38 that are controlled by a plurality of digital input.