for reading and resetting the pixel using a single nmos n channel metal oxide semiconductor transistor 22 per pixel like reference numbers are used to denote like circuit elements in fig2 a and 2b as shown in fig2 a the drain of the nmos transistor 22 is connected to an output node 24 and the source of the nmos transistor 22 is connected to the source 14 of the pmos transistor 19 the drain 16 of the pmos transistor 19 is connected to a reset node 30 the gate of the nmos transistor 22 is connected to a select node 26 during pixel reset the nmos transistor 22 is turned off and the reset node 30 is raised from ground potential to a potential of v dd to reset the pixel this sets the potential of the pixel to v dd u2013 v pb where v pb is the potential drop across the junction between the drain 16 of the pmos transistor and the n u2212 well the nmos transistor is turned on and off by means of a potential applied to the select node 26 after the reset of the pixel has been completed the reset node 30 is returned to ground potential and the nmos transistor 22 remains turned off while the pixel accumulates signal generated carriers since the source 14 of the pmos transistor 19 is floating and the drain 16 of the pmos transistor 19 is at ground potential during the charge accumulation period the pmos within the n.