the first p channel transistor 42 each read and latch signal line 38 transitions low at time t 2 to gate the first p channel transistors 42 thus gated the first p channel transistor 42 permits the second reference voltage to be coupled to the inverter input 52 this tends to pull the inverter output low which tends to turn on the second p channel transistor 44 setting the default value of the latch e g programming element not to be blown in preparation for receipt of the soft programming signal at t 3 at t 3 the first soft programming signal lines 220 221 222 are set to the desired state for their respective anti fuses devices 140 141 142 for example anti fuse devices 140 and 142 are desired to be blown so the first soft programming signal lines 220 and 222 are set high at t 3 thereby coupling a second soft programming signal line 26 to the input of the anti fuse latch circuits 120 and 122 the second soft programming signal line 26 is set low so as to cause the input 52 of coupled latch circuits 120 and 122 to transition low thus causing the latch output 54 to transition high in contrast anti fuse device 141 is not desired to be blown so the first soft programming signal line 221 is set or remains low at t 3 thereby not applying the second soft programming signal 26 to the input of the.