transistor were to be fabricated the doped layer 40 is preferably composed of thin film containing p type dopants such as borosilicate glass bsg conversely if a nmos transistor were to be fabricated the doped layer 40 is preferably composed of thin film containing n type dopants such as phosphosilicate glass psg next as shown in fig5 an anneal process is conducted to drive dopants within the doped layer 40 into the fin shaped structure 14 for forming a doped region 44 in which the doped region 44 is preferably serving as a lightly doped drain after removing the liner 42 and the doped layer 40 an epitaxial layer 46 is formed to fill the recess 38 with in situ dopants or accompanied by extra ion implantation process to form a source drain region next standard finfet fabrication process could be conducted by first forming a contact etch stop layer cesl on the fin shaped structure 14 and the gate structure 28 and forming an interlayer dielectric ild layer not shown on the cesl next a replacement metal gate rmg process is conducted to planarize part of the ild layer and cesl and transform the gate structure originally composed of polysilicon material into metal gate since the rmg process is well known to those skilled in the art the details of which are not explained herein for the sake of brevity it should be noted that despite two ssd techniques were utilized to adjust threshold voltage and form lightly doped drain in the aforementioned embodiment including using a doped layer or ssd technique to adjust threshold voltage before formation of gate structure and then using ssd technique again to form lightly.