of driver 140 to the gate of transistor q 2 122 as shown the gate drive pins of driver 140 are also strategically positioned assigned to coincide with the gate pin positions of transistors q 1 120 and q 2 122 thus providing ideally short gate drive traces 670 and 680 respectively fig7 a and 7b illustrate top views of the circuit layout 600 of the components and traces in the power stage area 102 of the exemplary power converter 100 of fig1 6 a and 6 b the top views of fig7 a and 7b are essentially reversed images of those of the bottom views of fig6 a and 6b but serve to further illustrate that such mirror image layouts including inverted layouts are also possible in the context of the present fig7 a for example illustrates a top view of the circuit layout 600 of the components 602 overlying the circuit traces 605 of the power stage 102 of the exemplary power converter 100 of fig1 6 a and 6 b fig7 b illustrates the pcb traces 605 of layout 600 without the components 602 to better reveal the layout fig7 b also illustrates the general contact areas of the lead and pin contact surfaces 610 for the components 602 fig8 illustrates top and bottom views respectively of an exemplary package and pin configuration of an exemplary mosfet driver and a pair of mosfet transistors.