the l level selection signal the selection circuit 140 selects and outputs the output signal sync 1 as the output signal sync 3 at this time the output signal sync 3 is outputted at a timing of the rising edge t 1 of the system clock sck the flip flop circuit 130 holds the output signal sync 3 and outputs the signal as the output signal sync 4 at a timing of rising edge t 3 of the system clock in this manner even when the flip flop circuit 120 enters a metastable state at a timing of a falling edge of the system clock sck the input signal async can be transmitted to the flip flop circuit 130 of the subsequent stage at a timing of the next rising edge of the system clock sck subsequently a description is made with reference to fig8 on the case that the output signal sync 2 of the flip flop circuit 120 is converged to the h level after the flip flop circuit 120 enters a metastable state at a timing of the falling edge t 0 of the system clock sck fig8 is a second timing chart for describing the operation of the synchronization circuit 100 a of the second embodiment in this embodiment when the flip flop circuit 120 enters a metastable state and the output signal sync 2 is converged to the l level the output signal sel 2 of the latch circuit 170 remains at the l level.