burst control pulse generating circuit according to the third embodiment is now discussed with reference to fig8 and 9 fig8 is a circuit diagram showing the structure of the burst control pulse generating circuit according to the third embodiment fig9 is a timing chart showing the operation of the burst control pulse generating circuit according to the third embodiment as shown in fig8 the burst control pulse generating circuit 120 includes a timing generating circuit 1230 which maintains a constant bit transmitting speed while varying a modulating pulse width and the pulse generating logic circuit 300 the timing generating circuit 230 has the two input nand 201 as a two input logic circuit the inverters 202 through 205 as not circuits and delay control inverters 231 through 238 as delay control not circuits adapted to control delay time by a delay control signal dctrl the four inverters 202 through 205 n 4 are connected in series with the output pin of the two input nand 201 the output pin of the fourth inverter 205 is connected with one input pin of the two input nand 201 the burst signal burst is inputted to the other input pin of the two input nand 201 the clock signal dclk is outputted from the output pin of the inverter 205 the delay control inverters 231 through 238 are connected in series with the output pin of the.