m the adder 3 adds the runa an runb and 1 cy and outputs resultant data l the adder 4 adds the data 0 and data l and outputs data n the decoder 5 inputs the data m the decoder 6 inputs the data n when the data n does not contain the runb the decoder 6 is disabled the selector 7 selects the data m or n and outputs data q the adder 8 adds the data q and 1 cy the logical circuit 10 comprises and gates a1a to a64a and a1b to a64b or gates g1a to g64a and g1b to g64b and 64 latches l1 to l64 each of the decoders 5 and 6 has an input terminal d and 64 output terminals q0 to q63 each of the decoders 5 and 6 outputs 34 1 34 to an output terminal corresponding to an input data value supplied to the input terminal and outputs 34 0 34 to the other output terminals the suffix a of runa levela represents odd numbered sets the first third fifth and so forth to be processed in parallel the suffix b of runb levelb represents even numbered sets the second fourth sixth and so forth to be processed in parallel next as with the conventional circuit one block is composed of 64 pixel data 8 rows u00d7 8 columns with reference to fig2 the operation.