13 and stored as part of the thread 0 queue or the thread 1 queue one skilled in the art will appreciate that the queues used in processor 10 may be used to store more than two threads instructions from the two threads are supplied to a mulitplexer mux 15 and control logic 17 is used to control whether instructions from thread 0 or thread 1 are supplied to a decode unit 21 decode unit 21 may convert an instruction into two or more microinstructions and supplies the microinstructions to queue 23 in a risc reduced instruction set code processor the instructions may already be in a decoded format and the decode unit 21 converts them into a format for execution the outputs of queue 23 are supplied to a mid 25 which supplies instructions from thread 0 or thread 1 to a rename allocation unit 31 based on operation of control logic 27 the rename allocation unit 31 in turn supplies instructions to queue 33 mux 35 selects between the thread 0 queue and the thread 1 queue based on the operation of schedule control logic 37 which can for example select instructions from thread 0 and thread 1 based on available resources in execution unit 41 the output of mux 35 is supplied to an out of order execution unit 41 in this embodiment which executes the instruction the instruction is then placed in queue 43 the outputs of queue 43 are supplied to a mux 45 which sends instructions from thread 0 and thread 1 to a retire unit 51 based on the operation of control logic 47 in fig2 branch prediction circuitry may be added to assist in the efficiency of.