signal lines 90 the b int addr buf 120 is required to delay the access of memory internal to the mmu 10 as such the b int addr buf 120 receives a latch enable signal during u03c6 2 of the timing scheme thereby delaying the generation at its output of an internal address to occur such that data from both external and internal memory becomes available simultaneously because of the overhead cost of accessing external memory when operands are to be fetched from both internal and external memory concurrently the delay is also needed when external memory is written to internal memory or a register the address generated by b int addr buf 120 is conducted to the second inputs of mux 48 and mux 88 via signal lines 122 data may be written from the external memory to either or both ram a 40 and ram b 80 in either the single or dual access mode using the addressing scheme described above signals representing the data received from external memory are conducted via the a data bus 16 to the single dual access storage device illustrated in fig2 this data may then be written to the a ram 40 and b ram 80 as described above in either a single or dual access mode a multiplexer mux 126 receives the latched addresses from a int addr lch 46 b int addr lch 86.