multiplexer 17 one row latch decoder 21 is provided for each memory array 22 each memory array 22 is comprised of a plurality of memory cells each operable to store one bit of information four memory arrays 22 labeled bank 0 through bank 3 are illustrated in fig6 accordingly there are four row latch decoder circuits 21 one each for controlling bank 0 through bank 3 the column address counter latch circuit 19 is responsive to the control logic 11 and the address register 15 a series of column decoders 23 are responsive to the bank control logic 18 and the column address counter latch 19 one column decoder 23 is provided for each memory array 22 as discussed above sdram 10 includes four memory arrays 22 labeled bank 0 through bank 3 accordingly there are four column decoder circuits 23 one each for controlling bank 0 through bank 3 an i o gating circuit 24 is responsive to the column decoder circuits 23 for controlling sense amplifiers 40 within each of the memory arrays 22 the sdram 10 may be accessed through a plurality of data pads 25 for either a write operation or a read operation for a write operation data on data pads 25 is.