not a limitation in the following the spirit of the invention will be described with reference to a dram package structure but one skilled in the art will easily be able to apply the concepts set out in this disclosure to other memory devices such as logic devices additionally the accompanying drawings illustrate a boc dram package design but one skilled in the art will understand that the following concepts can also be applied to other package designs such as cob and fbga designs as set out in the above the present invention introduces a common ground reference to a semiconductor package such as a dram this is achieved by plating the back side of the die and the back side of the package substrate with metal or any types of conductive plating these back side metal plates back side conductors are then coupled together such that the entire package has one common power supply reference plate this strong common ground reference means that during sso switching between vssq and vddq the voltage drop will be minimized and therefore the inductance at the vssq power supply rail is reduced the packaging means of providing the common ground reference has the added advantage of increasing the amount of space available for wire bonding between the die and the package substrate please refer to fig3 which is a bottom view of a semiconductor package 100 consisting of a package substrate and die wherein both the back side of the package substrate and the back side of the die.