vi representing a command of zero delay are coupled to individual ones of the shift register sections 116 and the stave delay command corresponding to the stave delay of fig4 is coupled to another shift register section 116 as shown in fig1 the u00b1 sign bit and the bearing signal are coupled to individual shift register sections 116 the coupling of the aforementioned input signals to the shift register sections 116 is accomplished via the corresponding steering units 118 which in response to the update signal permit recycling of the stored digital numbers from the back end of the shift register 114 to the front end thereof or replacing the stored digital numbers with new values of the delay commands the u00b1 sign bit and the bearing signal with respect to the steering unit sections 126 each of the and gates 128a b is connected to the update signal the terminal of the and gate 128a connected to the update signal is complemented so that when the update signal is low corresponding to a logic state of zero the and gate 128a couples signals from an output terminal of the shift register 114 to the corresponding input terminal when the update signal is.