represent 0 u00d7 2 10 in this manner a carry from the ten bits of correction memory 70 is not propagated into the base delay memory 44 but is propagated and stored in register 75 as an extra least significant bit of the same power of two as the least significant bit 45 in base delay memory 44 in some embodiments of the invention the significance of the bits may control the vernier in a non binary manner that is a bit may not provide a delay twice that of a next less significant bit the apparatus of fig1 operates in the following manner data from the test system computer is loaded into base delay memory 44 via bus 80 into vernier memory 70 over bus 81 and into vernier memory 72 over bus 82 typically each of these memories is many bits deep with each 34 row 34 of bits representative of the desired delay for a particular test and with the collective memory representative of the desired delays for a sequence of many tests in a well known manner the contents of the base delay memory 44 are loaded into counters 40 and 42 to provide data indicative.