pe to pe switch control u201d the interface to a host processor other peripheral devices and or external memory can be done in many ways a primary presently preferred mechanism shown for completeness is contained in a direct memory access dma control unit 181 that provides a scalable manarray data bus 183 that connects to devices and interface units external to the manarray core the dma control unit 181 provides the data flow and bus arbitration mechanisms needed for these external devices to interface to the manarray core memories via the multiplexed bus interface represented by line 185 a high level view of a manarray control bus mcb 191 is also shown all of the above noted patents and applications are assigned to the assignee of the present invention and incorporated herein by reference in their entirety turning now to specific details of the manarray processor apparatus as adapted by the present invention the inventive approach advantageously provides efficient implementation of more complex instructions and their multi cycle execution units as described further below fig2 a illustrates further details of a pe 201 suitable for use as one or more of the pes of fig1 fig2 b illustrates further aspects of a multi cycle execution unit 216 specifically a divide and square root unit incorporated in the dsu 208 the execution units read source operands from the crf 210 and write results to the crf 210 such reading and writing is illustrated in fig2.