to access its entire memory space the number of bits required by cpu 201 to access its entire memory space is hereinafter referred to as cpu address length e g in the present embodiment cpu address length is 20 bits configuration register 252 for example may be 12 bits long while peripheral devices 111 121 131 141 and 151 may have configuration registers containing more or fewer bits depending upon the memory size of each particular peripheral devices the contents of configuration register 252 indicates to peripheral 101 the memory address es peripheral device 101 has been assigned by cpu 201 a configuration flag 253 is a one bit register which is set when cpu 201 has assigned memory address es to peripheral device 101 i e peripheral device 101 is configured configuration flag 253 is reset when cpu 201 has not yet assigned memory address es or when cpu 201 has explicitly unassigned i e unconfigured memory addresses priorly assigned to peripheral device 101 peripheral device 101 also contains a command register 256 which contains a number of bits equivalent to the number of data lines in data lines 102 e g four bits in the present embodiment command register 256 is used to store a current command sent by cpu 201 see table i each peripheral device 111 121 131 141 and 151 contains a command register peripheral device 101.