20 is provided for varying the band gap at the heterojunction interface smoothly and y increases with position toward the top of the layer thus the composition of layer 20 varies gradually al x ga 1 x as layer 24 is also provided for the same purpose but x decreases with position toward the top of the layer layers 20 22 and 24 serve as an emitter region and layer 26 serve as an emitter cap layer using the thus formed epitaxial wafer first element isolation insulating layers 28 reaching substrate 10 are formed by implantation of h ions and electrode isolation insulating layers 30 reaching n type gaas layer 12 within the transistor are formed by implantation of b ions using a predetermined mask the semiconductor layers are selectively etched up to a depth to reach p type gaas layer 18 thus exposing the base subsequently a cvdsio 2 layer 32 is formed over the entire surface to provide an electrode contact to the collector region selective etching is carried out from the wafer surface up to a depth to reach layer 12 a thin layer of auge is formed in the etched portion and a layer of au is then formed on the auge layer to provide a collector electrode 34 further contact holes are formed for the emitter and base regions to provide emitter and base electrodes 36 and 38 of auge layer using a transistor having the same structure as the thus formed heterojunction bipolar transistor the collector transit time was calculated by means of monte carlo simulation the result was about 0 7 psec this is substantially the same as that of the heterojunction bipolar transistor of.