14 is equivalent to the output signal 99 when a phase of the feedback clock signal 14 is lagging a phase of the reference clock signal 16 a pulse width of the inc pulse 19 is set wider than a pulse width of the dec pulse 20 when a phase of the feedback clock signal 14 is leading a phase of the reference clock signal 16 the pulse width of the dec pulse 20 is set wider than the pulse width of the inc pulse 19 when a phase of the feedback clock signal 14 is about equal to a phase of the reference clock signal 16 the pulse width of the dec pulse 20 is about equal to the pulse width of the inc pulse 19 in this case the pulse width of both inc pulse 19 and dec pulse 20 is defined to be u201c the minimum pulse width u201d generated by a phase frequency detector 4 the generation of the minimum pulse width is described in detail in the description of fig2 the inc pulse 19 and the dec pulse 20 are transmitted to the charge pump 7 the inc pulse 19 and the dec pulse 20 control the charge pump 7 to source or sink a current 33 to from the loop filter 9 based on an amount and the direction i e source or sink of the current flow the loop filter 9 produces a control voltage 10 the control voltage 10 controls the vco 11 to produce an output signal 99 that tracks the reference clock signal 16 i e output signal.