interconnections are extracted box 540 and a timing analysis box 545 is finally performed since this is not the reference design box 550 the designed integrated circuit is verified box 585 if the design does not meet the specification the process is the design is modified box 595 and the process is re executed depending on the modifications done if the design meets the specification the integrated circuit is fabricated box 595 a third embodiment of this invention is commonly referred to in the art as the placed gate level netlist to placed gate level netlist synthesis the placed gate level netlist to placed gate level netlist synthesis begins with the initial procedures of the process of fig1 or fig2 with the creation box 100 of the design specification and coding box 105 of the register transfer logic in the case of fig1 the logic synthesis is performed box 110 to create the listing of the component circuits with the attendant listing of the interconnections of the component circuits in the case of fig2 the physical synthesis is performed box 210 to create the listing of the component circuits with the attendant listing of the interconnections of the component circuits the synthesized box 110 of fig1 or box 210 of fig2 listing of the component circuits with the attendant listing of the interconnections of the component circuits are then placed box 120 of fig1 or box 220 of fig2 to provide a listing of the locations of the component circuit upon the semiconductor substrate rather than completion of the process of fig1 or fig2 the interconnections of the placed component circuits are routed box.