b d is seen through comparator 28 and flip flop 72 which drives switches c and d recall d_drive produces the complementary signal of c_drive this provides a steady state operation for the ccfl panel load considering the removal of the ccfl panel during the normal operation cmp rises to the rail of output of the error amplifier and triggers the protection circuit immediately this function is inhibited during the ignition period referring briefly to fig3 a 3 f the triggering of switches c and d through c drive and d_drive is in this embodiment alternating as a result of the flip flop circuit 72 as is shown in fig3 b the flip flop triggers every other time thereby initiating c_drive and accordingly d_drive the timing otherwise operates in the same way as discussed above with reference to fig2 a 2 f referring now to fig4 a 4 f the output circuit of fig2 or 3 is emulated for example fig4 a shows that at 21v input when the frequency sweeper approaches 75 7 khz 0 5 us overlapping the output is reaching 1 67 kvp p this voltage is insufficient to turn on the ccfl if it requires 3300 vp p to ignite as the frequency decreases to say 68 khz the minimum overlap generates about 3 9 kvp p at the output which is sufficient to ignite the ccfl this is illustrated in fig4 b at this frequency the overlap increases to 1 5 us gives output about 1 9.