the divider 12 reaches it maximum count of 128 whereby a reset signal resets the sr flip flop 14 this in turn disables the prescaler flip flops and other circuitry of fig8 by shutting off the current source that feeds the cml ecl and ecl to cmos circuits until the next div_r pulse occurs and so on the power savings achieved by this dynamic technique whose functionality is illustrated by the timing diagram of fig9 can be estimate as follows then for the worst case scenario the fractional timing block 20 will be u201c on u201d for a time t on determined by 1 the t cxo pulse width t cxo 1 f txo 1 20 ue89e ue89e mhz 50 ue89e ue89e ns ue89e ue89e and eq 12 as shown in fig9 so in the worst case the average current is then i avg t on t ue89e u2211 i ecl_ff i ecl_cmos u2211 i cmos eq 15 the average current is estimated to be i avg 114 4160 u00b7 1 4 ue89e ue89e ma 0 2 ue89e ue89e ma 1 0 ue89e ue89e ma 40 ue89e ue89e u03bc ue89e ue89e a eq 19 in addition since the fractional timing block is biased from a continuous current source of 50 u03bca the net total current is therefore thus the power for the compensation circuitry is reduced by more than one order of magnitude fig1 shows a block diagram for a typical wireless transceiver celluar phone which uses the low power fractional n synthesizer of this patent the system is comprised of the receiver r x and transmitter t x rf if.