adding an extra layer of insulation to ensure that current through the device flows only through its central area thereby minimizing its edge reading sensitivity application_number US 70683803 A description the present invention discloses a cpp design with bias cancellation whose signal current has been constrained to flow through only the area where bias cancellation is taking place this is accomplished through the introduction of two novel modifications to the prior art design that was shown in fig4 as illustrated in fig5 these are a reduction in the width of the bias cancellation layer now seen as afm layer 52 and the introduction of additional insulating layer 51 which serves to limit current flow to be through only the area that has bias cancellation continuing our reference to fig5 in the top half of that figure we have plotted the bias field as a function of position relative to the center of the read track curve 55 shows the hard bias field curve 56 the hard bias cancellation field and curve 57 the total field referring now to fig6 using data obtained through micro magnetic simulation we have plotted the normalized signal amplitude as a function of the hard bias cancellation field this shows that the signal amplitude of this new structure increases almost linearly with the hard bias cancellation field strength referring next to fig7 we now begin a description of the process for manufacturing the new device the process begins with the provision of a substrate not shown on which lower lead layer 41 is formed the requisite layers to form a gmr stack are then laid down followed by an exchange dilution layer of but not limited to cu ru cr rh ta or laminates of two or more of these elements which is deposited.