cutting off the third transistor 121 by the third logic control 221 by cutting off the second transistor 112 by the second logic control 212 by conducting the fourth transistor 122 by the fourth logic control 222 and by conducting the first transistor 111 by the first logic control 211 respectively recirculation current flows from the first transistor 111 to the fourth transistor 122 via out 1 the load 14 and out 2 voltage at out 2 increases continuously until it reaches the value of a kickback voltage the second positive input 63 p 2 of the comparator 63 then senses the kickback voltage at out 2 as such a polarity of either output signal of the comparator 63 inverts that is the second output 63 p 5 of the comparator 63 generates an output control signal which is fed to the second logic control 212 to combine with other control signals fed thereto for generating a kickback voltage reduction control signal which is adapted to conduct the second transistor 112 by feeding to the gate terminal thereof i e connected to output 212 p 3 of the second logic control 212 eventually current flows from out 2 to the ground gnd via the conducted second transistor 112 voltage at out 2 remains at the level of kickback.