design is tested if it is determined that this fpga can be used to implement design b a performance testing is performed step 144 if the fpga fails the performance testing it is again rejected if it passes the performance testing the fpga is placed in another specially designated bin step 146 the fpgas in this bin can only be used to implement this specific customer design the above described procedure is used until the last design shown in fig3 as design m is tested the application of the above described procedure in a wafer is now described a wafer typically contains a number of dies such as the dies marked u201c 1 u201d u201c 2 u201d u201c 32 u201d in a wafer 212 of fig4 all some or none of the dies may contain localized defects in one embodiment each die is tested using the procedures described in fig1 or 3 the result of the testing is stored in an electronic file 214 each record in the file contains the identification of the corresponding die i e wafer number in column 1 of file 214 and location of the die on the wafer in column 2 of file 214 and the design number assigned to this die in fig4 a non defective die has a design number of u201c gd u201d or other symbols.