air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device thus being applicable to a high performance logic circuit application_number US 201113384215 A description hereinafter the present invention will be further described with reference to accompany drawings and specific embodiments embodiment 1 a process flow for fabricating a surrounding gate silicon nanowire device with air sidewalls are as follows starting from a soi substrate a thickness of a si layer over a buried oxide layer is 2500 u00e5 2 a sio 2 layer is deposited with a thickness of 300 u00e5 by using a low pressure chemical vapor deposition lpcvd 3 a sin layer is deposited with a thickness of 1500 u00e5 by using a low pressure chemical vapor deposition lpcvd as shown in fig3 4 a photolithography process is performed to define a channel region and a large source drain region 5 as shown in fig4 the sin layer is etched by 1500 u00e5 and the sio 2 layer is etched by 300 u00e5 by using a reactive ion etching rie technology so as to form a hard mask for the large source drain region and then the photoresist is removed 6 a sin layer is deposited with a thickness of 300 u00e5 as shown in fig5 7 a photolithography process is performed to define a hard mark for a fin bar 8 as shown in fig6 the sin layer.