ensure a stable voltage of the peak holding capacitor c 4 which is then relayed to the adc the fast discharge unit 105 is composed of a first resistor r 3 a second resistor r 4 a bipolar junction transistor q 4 and an inverter u 6 a wherein the control pulse signal 30 is applied to the input end of the inverter u 6 a one end of the second resistor r 4 is coupled to the output end of the inverter u 6 a one end of the first resistor r 3 is connected to the other end of the second resistor r 4 and the base of the bipolar junction transistor q 4 the collector of the bipolar junction transistor q 4 is coupled with one end of the potential following capacitor c 3 and the emitter of the bipolar junction transistor q 4 is connected with the other end of the first resistor r 3 the fast discharge unit 105 enables the potential following capacitor c 3 and the peak holding capacitor c 4 to discharge fast through a transistor switching path the detailed operation process is described below basing on abovesaid architecture when the control pulse signal 30 provided by a microprocessor is positive both the first and the second transmission gates u 4 a u 4 b are turned on and in the negative half cycle of the analog voltage signal 40 the voltage comparison signal 10 of the feedback comparator buffer unit 101 is negatively saturated at this moment because a negative output is given by the inverter usa to keep the mosfet q 3 u201c off.