3 and case 5 or conformed step 5 u2032 in the test of the dram unit the decision manner in the step 5 u2032 is shown in the second embodiment to the fourth embodiment as described later in this case decision is effected electrically regarding whether the defective chip recognition fuse 33 is blown out or not if the chip is conformed in the step 5 u2032 process is advanced to the test to confirm the operation of the logic unit step 5 and the test is continued if the chip is defective the test of the object chip is finished at that time and the test of next chip is started in the step 5 in order to confirm the operation of the logic unit the function test and the dc test are executed the step 5 u2032 and the step 5 are incorporated into one test program to test the logic unit fig1 shows such an example as a flow chart as shown in fig1 to fig1 the step 5 and the step 5 u2032 are repeated in all chips on one wafer and when the test is finished the ink mark is applied to the defective chip as above described according to the first embodiment the semiconductor integrated circuit device of eram type must be tested using two testers for test of the dram unit and test of the logic unit when the test flow in the first embodiment is not used that is if the step 4 u2032 and the step 5 u2032 do not exist in fig1 since the chip judged defective in the test of the dram unit is deemed to.