the auxiliary word line drive circuits 103 are converted in level by the main row decoder 101 and the auxiliary row decoder 102 and then applied to the auxiliary word line drive circuits 103 fig1 a and 14b show a first example of each of the auxiliary word line drive circuits 103 as shown in fig1 a the auxiliary word line drive circuit 103 comprises three nmos transistors n1 n2 n3 the transistor n1 is connected between an auxiliary word selecting line ra and an auxiliary word line swl and has a gate to which a potential from a main word line mwl is applied the transistor n2 is connected between a negative potential supply line and the auxiliary word line swl and has a gate to which a complementary main word line mwlb is connected the transistor n3 is connected between the main word line mwl and the gate of the transistor n1 and has a gate to which the power supply potential vcc or the increased potential vpp is applied in an unselected state the main word line mwl is held at the negative potential vnb the complementary main word line mwlb at the power supply potential vcc and the auxiliary word selecting line ra at the negative potential vnb the transistor n2 is rendered conductive keeping the auxiliary word line swl at the negative potential vnb the main word line mwl which is selected in response to the application of an address signal changes from the negative potential vnb to the increased potential vpp the complementary main word line mwlb changes from the power supply potential vcc to the.