units 51 are typically placed on the smaller arrays 31 or on the insulating layer separating the interconnect pads from the array with the addition of interconnect pads 40 as shown in fig3 and a die 30 composed of a 7 u00d7 7 array of superblocks 31 a pair of die 30 mounted on a substrate would gain a total of 784 16 u00d7 49 possible interconnects in addition to the 108 presently available this would allow more cells to be used for active logic functions since fewer would be needed to function as interconnect wires thereby increasing the degree of gate utilization in addition since fewer of the existing buses will be needed for interconnections cells won 39 t be disabled by the need to use their close by buses for interconnections it is important to note that this added connectivity is achieved with little if any increase in die size the only increase would be that needed for the placement of the added switching units 51 shown in fig4 the interconnect network embedded on or within the substrate determines how the individual arrays 31 are interconnected and how the resulting device operates in terms of functionality and capacity fig5 shows a possible interconnect network for an array 60 formed from multiple smaller programmable gate arrays or chips 30 which are placed on a mcm substrate where the substrate interconnect lines interconnect corresponding points interconnect pads on each of the smaller arrays or chips the result is a three.