q 54 q 64 fig8 a shows a variable capacitance circuit comprising a single transistor and fig8 b shows a variable capacitance circuit comprising subdivided transistors wherein w denotes a gate width and l small ell denotes a channel length fig8 c graphically shows the capacitance characteristics of both transistors in fig8 a and 8b as described above the change point of the mos capacitance value toward decrease is determined by the potential difference between the gate and the source so that if mutually different dc bias voltages are applied previously to the respective gates of the subdivided transistors in fig8 b then the capacitance change start voltages depending on the control voltage vtune for the four subdivided transistors are rendered mutually different for example if the dc potentials to be applied previously are raised stepwise like a staircase the change characteristics of the capacitances cv due to the individual transistors are offset to the control voltage vtune as shown in fig9 a when these transistors are connected in parallel there is obtained cv u2032 cv 1 cv 2 cv 3 cv 4 hence widening the variable voltage range as graphically represented by cv u2032 in fig9 b also the change characteristics of the resistances rp due to the individual transistors are offset to the control voltage vtune as shown in fig9 a the equivalent parallel resistance rp is expressed as therefore in comparison with the resistance rp obtained without any gate bias offset the equivalent parallel resistance rp u2032 obtained through the gate bias offset by using a multiplicity of transistors is advantageous in the point that as shown in fig9 b its minimum value can be increased from rpmin to.