much of the bus traffic presented by microprocessor 110 is accomplished via level 2 cache 114 of course microprocessor 110 may also effect bus traffic around level 2 cache 114 by treating certain bus reads and writes as 34 not cacheable 34 level 2 cache 114 as shown in fig5 is connected to two level 1 caches 116 level 1 data cache 116 d is dedicated to data while level 1 instruction cache 116 i is dedicated to instructions power consumption by microprocessor 110 is minimized by accessing level 2 cache 114 only in the event of cache misses of the appropriate one of the level 1 caches 116 furthermore on the data side microcache 118 is provided as a level 0 cache which in this example is a fully dual ported cache as shown in fig5 and as noted hereinabove microprocessor 110 is of the superscalar type in this example multiple execution units are provided within microprocessor 110 allowing up to four instructions to be simultaneously executed in parallel for a single instruction pointer entry these execution units include two alus 142 0 142 2 for processing conditional branch integer and logical operations floating point unit fpu 130 two load store units 140 0 140 1 and microsequencer 148 the two load store units 140 utilize the two ports to microcache 118 for true parallel access thereto and also perform load and store operations to registers in register file 139 data microtranslation lookaside buffer u03bctlb 138 is provided to translate logical data addresses into physical addresses in the conventional manner these multiple execution units are controlled by way of multiple pipelines with seven stages each with write back the pipeline stages are as follows ______________________________________f fetch this stage generates the instruction address and reads the instruction from the.