level vdd to low voltage level vss the reasons are as follows a the first tft t 11 is turned on because the second clock signal cl 2 is at high voltage level vdd b the second tft t 12 is turned off because the second note n 2 is at low voltage level vss c the third tft t 13 is turned off because the first note n 1 is at low voltage level vss d the fourth tft t 14 is turned off because the first clock signal cl 1 is at low voltage level vss e the fifth tft t 15 is turned off because the signal of the output terminal out is at low voltage level vss f the first supplementary tft ma is turned off because the second note n 2 is at low voltage level vss g the second supplementary tft mb is turned on because the second clock signal cl 2 is at high voltage level vdd h the third supplementary tft mc is turned on because the second clock signal cl 2 is at high voltage level vdd i the voltage of the first node n 1 is at low voltage level vss because the first tft t 11 is turned on whereby the voltage of the first node n 1 is changed from vdd u2212 vth t11 u03b4vp to low voltage level vss j the second node n 2 is at low voltage level vss because the third supplementary tft mc is turned on whereby the voltage of the second node n 2 is pulled to be at low voltage level vss and k the output terminal out is at low voltage level vss because the second supplementary tft mb is turned on whereby.