as an external input portion 57 moreover the cpu 51 causes a display portion 58 to display design data design drawings and etc fig2 is a flowchart illustrating steps of the pattern design according to the present embodiment in the present embodiment after an operation is started s 10 deign data obtained when element layout design in the integrated circuit is ended is input into a storing portion such as the disk 60 in the aforementioned pattern design apparatus s 11 sequentially under control of the cpu 51 the data input into the pattern design apparatus is read from the memory portion and displayed on the display portion 58 and a mask layer to which the dummy pattern is inserted is selected through the input portion 57 s 12 in the present embodiment the gate electrode layer in the mos transistor is selected fig4 is a schematic plan view of a semiconductor device 10 illustrating a part of a pattern in which the mos transistor as an element is laid out after the element layout design in the integrated circuit is ended a pattern of a mos transistor region 12 is formed in such a manner that gate electrodes 11.