pulse of pci_exp_wake the judging module of the logic circuit judges the system as network waking state according to the low pulse signal of pci_exp_wake 2 the controlling unit of the logic circuit pulls the ich_wake signal to low notifying the south bridge or the io 3 the south bridge pulls the slp_s 3 signal to high and notifies the controlling unit of the logic circuit 4 the controlling unit of the logic circuit pulls the ps_on signal to low the atx power supply is turned on 5 the enable writing signal writing unit of the controlling module writes a switch on enable signal i e writes the enable signal es_en 0 set by bios when wol_en 1 the sw 2 is switched off and the system does not support the network waking function with reference to fig7 fig7 is a timing schematic diagram of the turn off of the invention as follows 1 the signal receiving module of the logic circuit receives a low pulse signal of power_bt_l the low pulse signal of power_bt_l is received by the signal receiving pin 2 2 the controlling unit of the logic circuit pulls the power_bt_r signal to low notifying the south bridge or the io of the turn off 3 the judging module of the logic circuit judges the current mode of the system according to bios mode signal the bios will generate the mode signal of the current system according to the power_bt_r signal the judging module judges the mode of the current system according to the content of the mode signal when it is determined that the system is in the s 3.