933 composed of an adder and code value switching circuits 934 to 938 composed of a selector circuit respectively each of the code value switching circuits 934 to 938 can switch output code values between the back diffusion code string c4c3c2c1c0 for the digital signal i and the back diffusion code string c04c03c02c01c00 for the digital signal q those code value switching circuits 934 to 938 are combined to compose a digital code string switching circuit to the input terminals 901 and 902 are entered digital signals i and q generated by sampling analog signals for example spectrum diffusion signals with a 8 192 mhz sampling frequency double the sampling frequency in the first embodiment the digital signals i and q are synchronized with the 8 192 mhz clock clk entered to the clock signal input terminal 903 and if digital signals i and q are entered to the input terminals 901 and 902 respectively the signal multiplexing circuit 933 multiplexes the signals then the multiplexed signal is entered to the first delay circuit 904 of the shift register 914 after this the multiplexed signal is shifted from the first delay circuit 904 to the tenth delay circuit 913 sequentially in synchronization with the clock signal clk the code value switching circuit 934 then switches the code value between c0 of the digital signal i and c00 of the digital signal q in a time dividing manner in the same way each of the code value switching circuits 935 to 938 switches the code value between c1 to c4 and c01 to c04 respectively.