vb is stabilized in its constant value when pd changes from 34 l 34 to 34 h 34 and pdb from 34 h 34 to 34 l 34 which causes the source of the transistor mn3 and the substrate to change to 34 h 34 and the gate to change from 34 l 34 to 34 h 34 after the delay time then mn3 is turned off in this period therefore the circuit is immediately changed to the power down status as explained above this embodiment makes it possible to start the circuit with no capacitance connected between v ss and vb any noise in v ss does not affect vb and no deterioration occurs in psrr characteristics moreover since transistors lower the bias node the circuit does not require a large capacitance as used conventionally and can decrease the area as well fig2 shows the construction of a start device of a self biasing constant current circuit taken as the second embodiment of the invention this embodiment uses a p channel mos transistor mp6 connecting its drain to the gate of the transistor mn1 applying the power down signal pdb to its source and the substrate and applying to the gate a signal derived from pdb introduced through the delay circuit dl in the power down status where pd 34 h 34 and pdb 34 l 34 the transistor mp3 is turned off and mp4 is turned on in this status vb 34 h 34 and no current flows.