package base 21 so that the production of the package base is still further facilitated and the production cost thereof lowered fig3 a and 3b show a third embodiment of this invention in which two semiconductor chips 8 are mounted on a package base 21 in this case a substrate cracking prevention plate 35 equipped with two openings 35a as shown in fig3 c is fixed onto the flat surface 21c of the package base 21 the semiconductor chips 8 and respective chip carriers 18 being disposed in the respective openings 35a three dielectric substrates 6 are provided on the substrate cracking prevention plate 35 with the openings 35a being positioned between them the respective electrodes of the semiconductor chips 8 are electrically connected to the peripheral circuits 6a of the adjacent dielectric substrates 6 thus a plurality of semiconductor chips 8 can be easily mounted solely by changing the shape of the substrate cracking prevention plate 35 similarly three or more semiconductor chips 8 can be mounted fig4 a and 4b show a fourth embodiment of this invention in this embodiment a panel like substrate cracking prevention plate 45 with no opening as shown in fig4 c is fixed to the flat surface 21c of the package base 21 two semiconductor chips 48 are arranged at appropriate positions on the substrate cracking prevention plate 45 three dielectric substrates 6 being arranged with the semiconductor chips 48 situated between them the semiconductor chips 48 are small signal semiconductor chips or power saving semiconductor chips so that they will not develop much heat when driven in the case of semiconductor chips 48 whose thermal resistance is.