6 may remain on the end surface 31 of the outer lead 30 fig4 e is a cross sectional view of the semiconductor package finally completed through the process of the present invention the feature of this structure resides in that the plated layer 6 and the plated layer 26 each formed of the material with good solder wettability are formed on the end surface 31 and the bottom surface 32 of the outer lead 30 respectively fig5 a to 5d and fig6 e to 6g are top views for facilitating the understanding of a part of the process of fig3 a to 3j fig5 a is a top view of fig3 a the plated layer 1 is formed in accordance with the shape of the patterned photo resist 2 the plated layer 1 serves as the island portion for mounting the semiconductor chip thereon and the outer lead when the semiconductor package is completed fig5 b is a top view of fig3 c in order to expose the end surface 31 of the outer lead 30 the photo resist and the encapsulation resin layer are removed to form the air gap 5 it is desired that the air gap 5 be formed only in a region in contact with the end surface 31 of the outer lead 30 but it is not desired that the end surfaces of adjacent outer leads be connected to each other via the air.