would not be short circuited to ground vcm when g 1 is not active instead it would be floating further in addition a series connection of a switch s 121 2 a capacitor c 1 2 and a switch s 122 2 is arranged between terminals a and b in parallel with a series connection of a switch s 123 2 a capacitor c 2 2 and a switch s 124 2 the connection between switch s 123 2 and capacitor c 2 2 is connected via a switch s 125 2 to ground vcm and the connection between capacitor c 2 2 and switch s 124 2 is connected via a switch s 126 2 to ground vcm switches s 121 2 and s 122 2 are closed in case of a gain setting signal g 2 switches s 123 2 and s 124 2 are closed in case of a gain setting signal g 2 during clock phases u03c6 1 and switches s 125 2 and s 126 2 are closed in case of a gain setting signal xg 2 or during clock phases u03c6 2 further similar arrangements of capacitors c 1 n and c 2 n with n 3 to n are added in parallel between terminals a and b these capacitors c 1 n and c 2 n are switched based on gain setting signals gn and xgn with n 3 to n just like capacitors c 1 1 c 2 1 c 1 2 and c 2 2 are switched based.