25 while writing a zero involves writing a 0 to node 15 and a 1 to node 25 the memory cell 5 forms a bi stable circuit that is stable either in a state where it stores a 1 and a 0 on the two devices or in a state where it stores a 0 and a 1 however with shrinking geometries it is known that the cell stability can be challenged and even corrupted by external voltage noise disturbances which are quantified as snm or rnm snm being signal noise margin when the wordline is open while rnm is retention noise margin when the wordline is closed on power up if the same voltage level is applied to vdd 1 and vdd 2 at the same time then the state that the memory cell will initialise in is uncertain and in an array of memory cells a percentage will probably initialise in one state and the rest in the other state it may be desirable to initialise a memory in a known state by providing separately controllable power inputs to the memory cell vdd 1 and vdd 2 embodiments of the present invention are able to power up one side of the cell before the.