address generator for the dual port memory showed in fig4 d containing n segments and its structure is chosen to optimize the number of reads and writes the memory has two ports for reading and writing in the same time to a different address the subdivision block is composed by three couples of x and y adders divide by two plus a delay element the sequence illustrated by the flow chart 4 b can be described as 0 write the first element three sets of x y coordinates representing two anchor points and one control point that is the b u00e9zier curve to be processed in the first memory address location addr 0 1 subdivide the points as shown in the formula and write the lower subcurve in the memory addr location 1 and the upper subcurve in the memory addr location 0 this is presented as the best sequence due to the fact that every result is calculated from the first read and the subsequent writes are determinated only by this particular and its intermediate results 2 the subcurve of addr 1 is divided again and stored as described before the lower part in memory addr location 3 and upper part in the addr location 2 same scheme for subcurve 0 divided and stored in 1 and 0 memory addr locations 3 the process is repeated again for each subdivision and in the example the last writes is showed in.