minute and two hours in air or n2 o2 wherein the o2 content is between 1 and 100 if there is a reaction between the feo encapsulation material and m1 system or undesired interface between feo encapsulation material and m1 system a layer of dielectric can be deposited on top of the encapsulation layer to separate the encapsulation and m1 the examples of suitable materials for the separation layer are cvd alox ald alox pvd alox cvd sinx pvd sinx cvd sionx pzt and feo referring now to fig1 a planarized transistor in conventionally formed on top of the planarized surface of the transistor 20 is a ferroelectric capacitor including a bottom electrode be 1 a ferroelectric layer 2 a top electrode te 3 the ferroelectric capacitor is encapsulated using layers 4 as is known in the art after the ferroelectric capacitor is formed a ferroelectric oxide feo is formed over the encapsulated ferroelectric capacitor and planarized pc referred to in the drawing figures is poly silicide gate contact or simply poly contact referring now to fig2 an feo encapsulation layer 6 is formed and a separation layer 7 is also formed the separation layer is used to prevent the reaction between the feo encapsulation and metal 1 m1.