clock edge modulated signals to the channel where the clock edge modulated signals include direct current balancing control signals a signal receiver is connected to the channel the signal receiver is configured to recover the direct current balancing control signals application_number US 26430305 A description the invention includes a single channel serial link using clock edge modulation cem this scheme also known as pulse width modulation pwm encodes data information onto a periodic clock by varying the position of a selected edge i e the rising edge or falling edge thus the pulse width of the clock is altered or modulated the invention provides techniques to transfer a clock signal data and control signals over a single channel by way of example the invention may be implemented by varying the falling edge of the clock signal as shown in fig2 a data are encoded as a variation of the clock falling edge position while the position of the rising edge is fixed the periodic occurrence of the rising edges enables easy extraction of the clock signal from which the receiver can generate the u201c dot clock u201d simply by dividing down the incoming signal e g by 18 with no further clock recovery mechanism the modulation of the falling edge position or the.