the tag array 38 and the data array 34 are simultaneously written the tag array 38 is written with the saved tag address and the valid bit is set the data array 34 is written with the incoming instruction from the external memory during a flush the tag valid bit for all sets and lines is reset all data in the instruction cache 14 is now invalid whenever any given set is first accessed after flush a cache miss is guaranteed to occur a flush cycle can occur during a fetch or replace cycle in case of a fetch an instruction hit is forced high whether or not a hit truly resulted in case of a replace cycle the valid bit for the set being replaced would be simultaneously written and reset the reset wins out invalidating the newly loaded data during a null cycle the tag array 38 and the data array 34 are not accessed a fetch requested by the bus control unit 20 may be cancelled by the integer execution unit 10 with an abort cycle in that case the cycle proceeds as normal except that the data output latches are never reset and loaded with new data replace.