t ch u2014 as shown in fig2 u2014 can be generated by frequency division with a frequency step down means 35 being generated from the synchronization clock sequence t syn alternatively the chopper clock sequence t ch can also be derived from the engraving clock sequence t g with the engraving frequency on the basis of a frequency multiplication with a phase locked loop circuit pll circuit the chopper frequency advantageously is a multiple of the engraving frequency and is optimized in view of the properties of the switched power amplifier 16 for example in view of the filter properties of the filter element 26 fig3 shows a second exemplary embodiment of the inventive signal processing unit 1 which differs from the first exemplary embodiment in that the d a converter 15 is eliminated and the pulse width modulator 25 in the switched power amplifier 16 is replaced by a timer 36 the timer 36 is directly driven by engraving control data gsd at the output of the signal processor 13 and converts the engraving control data gsd into the pulse width modulated control signals s 1 s 2 for the two electronic switches 23 24 in this case the timer 36 is synchronized by a chopper clock sequence t ch on the line 34 whereby the chopper clock sequence t ch can be generated in the same way as in the exemplary embodiment in fig2 given employment of a timer the chopper clock sequence t ch can also be additionally noise infested by a random signal acquired in a numeric random generator fig4 shows a first exemplary embodiment of a signal processor 13 the signal processor 13 comprises two table memories 35 36.