delay signal loss etc as a consequence the overall synchronization of the system is not normal for instance in case of voice data the voice is distorted if control data are exchanged a deadly error occurs to the system that 39 s why a circuit for eliminating the skew i e phase difference between clock signals is introduced to prevent the foregoing phenomenon transition varying buffer 800 controls an overall relationship between registers 400 500 and 600 by controlling the phase and delay of each clock signal while interworking with register 500 meaning each register 400 500 and 600 determines the slope of an edge at which the clock signal changes from low to high the time delay of the clock signal depends on the slope transition varying buffer 800 can be controlled by connecting transition controller 900 to register 500 as is apparent from the above description in accordance with embodiments since the transition varying buffer and the transition controller are added to control the clock input transition of flip flops emi and ir drop of the digital synchronous circuit caused by a change in the clock input transition of the flip flops can be further mitigated as far as the operation of the digital synchronous circuit allows although embodiments have been described herein it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the.