performance enhancements provided by the present invention 39 s enabling back to back data transfers of data received from a communications link to system processor memory over shared i o system bus 40 second and subsequent bus arbitrations occur even though data previously placed on bus 40 has not been completely transferred at time t1 the first bus request is issued in response bus grant comes up at time t2 an address and data are placed on the bus at time t3 by time t4 dma control logic 20 has determined it necessary to again issue a bus request though the previous data transfer is incomplete the bus request is overlapped with data transfer at time t5 the second bus grant is received coincident with completion of the data transfer following the last data transfer an address and data associated with the next cache line data transfer is placed on the bus fig4 is a timing chart illustrating how bus arbitration occurs in the midst of data transmission from bus 40 to the communications link at time t1 the first bus arbitration cycle completes and dma control logic places the address addr from tag table 22 on the bus there follows some idle time on the bus between t2 when dma control logic 20 accessed main memory and t3 the point in time at which data from that address in main memory is placed on the bus advantageously in the present invention there is some compensation for that idle period because at time t4 while data is being transferred dma control logic 20 raises a bus request coincident with the grant being given is the completion of the previous data transfer cycle at time t5 dma control logic 20 immediately places the.