spacers 108 and the etch mask pattern 101 are removed to expose the first pattern 106 the step portion 112 and the second pattern 110 additional layers of material may then be formed on the substrate including for example a relatively thin 50 300 u00e5 oxide layer not illustrated and a thicker nitride layer 124 as illustrated in fig5 b c an insulating layer 114 may then be formed on the nitride layer 124 and upper portions of one or more of the insulating and nitride layers may be removed to expose the nitride layer 124 or the nitride layer and the semiconductor fin structure 113 a portion of the nitride layer 124 and if present any buffer layer s adjacent the sidewalls of the first pattern 106 of the semiconductor fin structure 113 may then be removed to form openings 128 between the substantially vertical sidewalls of the semiconductor fin structure and the remaining portion of the insulating layer 126 as illustrated in fig5 d the exposed portion of the first pattern 106 may then be subjected to an ion implantation process during which a predetermined dose of one or more dopant species 116 are implanted to establish the electrical characteristics of the channel region 118 as illustrated in fig5 e following the ion implant process a.