one of the upstream tristate buffers 40 42 is enabled an output of or gate 96 is automatically a logical 1 this will cause the output of or gate 112 to necessarily be a logical 1 the logical 1 signal on line 50 applied to an input of or gate 120 causes or gate 120 to apply a logical 1 to an input of nand gate 114 nand gate 114 now has two logical 1 inputs and consequently applies a logical 0 to the enable terminal of tristate buffer 43 disabling tristate buffer 43 in this case during an active test mode tristate buffer 43 is disabled regardless of the state of the enable in4 signal due to one of the upstream tristate buffers 40 42 being enabled atg test mode signal low enablement of buffer 43 in fig4 if the atg test mode signal on line 50 is a logical 0 indicating that the test mode is inactive invertor 110 inverts this logical 0 signal on line 50 and applies a logical 1 to the first input of or gate 112 hence the output of or gate 112 will necessarily be a logical 1 a logical 1 or logical 0 enable in4 signal applied to line 94 is inverted by invertor 118 so as to apply a logical 0.