input d a data output q an address input a an active low write enable input we active low is a well understood concept meaning that the described function is activated when the corresponding active low signal is set to a logic 0 and an active low device enable ce in the current embodiment this memory size is 32 768 bytes data memory extension 10 is a generic sram cell with a data input d a data output q an address input a an active low write enable input we and an active low device enable ce in the current embodiment this memory size is 512 bytes address mux 8 is an address multiplexer and data mux 11 is a data multiplexer both multiplexers 11 and 8 have a function consistent with that of any generic multiplexer this is most easily described using the verilog 2 description y lt sel b a see ieee standard 1364 1995 u2014 ieee standard description language based on the verilog hardware description language the memory cells 9 and 10 have functions consistent with that of generic synchronous memories an examination of fig3 shows that if the buf_sel signal is low then the write_address is applied to the upper main data memory 9 and the write enable of this memory we is active low in this state the 8 bit data appearing at the data inputs d 2 will be written into this memory at the same time the lower main data memory 9 receives the read_address and the write enable of this memory we is inactive high in this state the memory is read and the data passes.