pole of the source of supply of electric current the terminal q of the flip flop 41 is connected to one control input 35a of the alarm device 35 to one input of a nand gate 47 and also to one input of an or gate 48 the output s 1 of the counter 45 is connected to another input of the nand gate 47 while the output s 2 of this counter is connected to another inverting input of the or gate 48 the output of the nand gate 47 and the or gate 48 are each connected to a respective input of an and gate 49 having two inputs and the output of which constitutes the output terminal s43 of the circuit 43 and on which is collected the above mentioned signal b the output of the and gate 49 is connected on the one hand to an input of the and gate 42 and on the other hand to an input of a nor gate 50 which has two inputs and the output of which is connected to the reset to zero terminal r of the flip flop 40 the second input of the nor gate 50 is connected to the output contact 37 of the switch 28 finally the reset to zero terminal r of the downstream flip flop 39 is connected to the output terminal 37 of the switch 28 via an inverter 51 the flip flops 39 40 and 41 are flip flops which respond to trailing edges of the signal applied to their respective clock inputs the clock pulse signal h is applied to the clock inputs of the flip flops 39 and 40 which form the anti surge circuit while.