in fig2 but is different therefrom in that it includes leak blocking circuit 5 inserted between power supply voltage providing circuit 3 and target circuit 4 and control circuit 6 which detects an operating state of target circuit 4 to sends a control signal to leak blocking circuit 5 minimum energy point monitor circuit 2 and power supply voltage providing circuit 3 are of circuit arrangements which are identical to those in the first exemplary embodiment control circuit 6 sends control signal active to leak blocking circuit 5 when target circuit 4 starts operating and sends control signal sleep to leak blocking circuit 5 when target circuit 4 stops operating fig1 shows the circuit arrangement of leak blocking circuit 5 leak blocking circuit 5 includes a power switch p mosfet p channel mos field effect transistor 501 and rs set reset flip flop 502 rs flip flop 502 has an r reset input terminal for being fed with control signal active for controlling the timing to start operating target circuit 4 and an s set input terminal for being fed with control signal sleep for controlling the end of operation of target circuit 4 output terminal q of rs flip flop 502 is connected to the gate of p mosfet 501 with leak blocking circuit 5 thus arranged when target circuit 4 is to operate output terminal q of rs flip flop.