respective section of external state cache 15 in other words the processor adopts a state written by the other processor others instructions can be used to enable or disable automatic state dumps and set their frequency in the absence of an explicit instruction state dumps are controlled by hardware by default state dumps occur at regular intervals the regular interval can be increased or decreased based on a determination in this case by cec 13 of a likelihood of failure e g based on a number of detected correctable and uncorrectable errors detected voltage rail droops etc the regular interval can be cut short upon prediction of an imminent failure a state dump can also be omitted or delayed based on other demands on the processor for example a state dump can be omitted or delayed to avoid synchronization issues the need for omitting or delaying state dumps is minimized by the use of dedicated state dump ports 31 and 32 dedicated to external state cache 15 since external state ports 31 and 32 are separate from the normal system interface ports 41 and 42 they allow state dumping to proceed without significant performance issues because normal system bandwidth is not consumed the frequency of state dumps can be set for example as a function of factors relating generally to a tradeoff of need for high availability and performance or power while using a dedicated state dump port alleviates most of the performance overhead there can still be some overhead associated with specific state dump instructions so fewer state dumps can be called for when.