integration time constant r 2 c 2 the q output of the flip flop 305 is connected to the integrator 308 via an inverter 318 to control the time for starting the integration the q output of the flip flop 305 is also provided via a buffer 316 to the hold switch 307 to control the hold timing of the integrator 306 both outputs of the integrators 306 and 308 are supplied to a voltage comparator 309 whereby coincidence in the voltages of both outputs is detected the output of the voltage comparator 309 is provided to the reset terminal of the flip flops 302 and 305 and the divider 304 through an or gate 324 the control circuit 313 is comprised for example of a d type flip flop with the d terminal provided with a high level signal and the t terminal connected to a q terminal of the gate signal generator 103 the q output of the control circuit 313 is provided to the d terminal of the flip flop 302 the reset signal 202 from the terminal 221 is provided to the gate signal generator 103 and the control circuit 313 and through the or gate 324 to the flip flops 302 305 and the divider 304 at the beginning of the operation by the reset signal 202 from the terminal 221 the control circuit 313 is changed to high level to yield a start signal 401 shown in fig4 i which is provided to the terminal of the flip flop.