first embodiment of the present invention it is possible to use one system of substantially vblh alone as the power supply for imparting the overdrive potential to the bit line making it possible to decrease the chip size compared with the conventional semiconductor memory device also it is unnecessary to switch the supply path of the bit line charge potential during activation of the sense amplifier which is required in the prior art and it suffices to redistribute the charge pre charged to the vblh power supply line to the bit line capacitor and the cell capacitor as a result the generation of the power supply noise can be markedly suppressed a second embodiment of the present invention will now be described with reference to fig6 the second embodiment is directed to the circuit for adjusting the value of the charge adjusting capacitance c added to the vblh power supply line described previously in conjunction with the first embodiment if the final potential of the bit line is made as close to vblh as possible in the bit line potential overdrive circuit described previously in conjunction with the first embodiment it is possible to suppress the power consumption of the vblh potential generation circuit also it is possible to eliminate the vblh potential generation circuit if the final potential of the bit line is allowed to coincide with vblh with a high accuracy such being the situation it is desirable to adjust the value of the charge adjusting capacitance c added to the vblh power supply line as.