of or gate 133 controls synchronous flipflop 122 a retriggerable monoflop 129 comprising two comparators receives the write clock signal from clock input 127 and generates the signal 34 x 34 on read write select line 123 select line 123 is also connected to read logic 135 read logic 135 substantially consists of a d flipflop 141 for read request a d flipflop 143 for read confirmation and gates 145 and 147 and a gate 149 providing a predetermined delay read logic 135 controls a synchronous flipflop 137 through which the read data are transferred in the circuit according to fig2 a write operation is performed as follows the leading edge of a write clock signal at clock input 127 causes synchronous flipflop 132 to accept data after a time delay determined by delay line 128 and gates 130 and 133 synchronous flipflop 131 accepts the data and synchronous flipflop 122 accepts the corresponding address so that data and address are simultaneously present at ram 111 at the same time pulse shaper 125 delivers a write pulse to ram 111 write address counter 124 continues counting by 1 and its new state is transmitted via multiplexer 121 to synchronous flipflop 122 where it is present for the next write operation retriggerable monoflop 129 then applies signal x 0 on read write select line 123 upon the write clock pulse at clock input 127 the delay of monoflop 129 is chosen so that the signal x 0 is maintained for at least 20 nanoseconds after the last write clock pulse has elapsed if the period duration of the write clock is shorter than its pulse width plus the hold time of monoflop 129 34 x.