the embodiments of the present invention referring to fig8 the esd protection apparatus includes a resistor 810 a capacitor 820 a first transistor 830 a second transistor 840 diodes d 1 dn and a main transistor 850 wherein n is an integer greater than 0 in the embodiment the transistors 830 and 840 are a pmos transistor and an nmos transistor respectively and the main transistor 850 is an n type field oxide device in general the substrate of the main transistor 850 has a substrate internal resistor indicated as a resistor rsub in fig8 wherein the substrate of the main transistor 850 is coupled to the second power rail gnd as the ground line here via the substrate internal resistor rsub the capacitor 820 and the resistor 810 are connected with each other in series between the first power rail vdd as the system voltage line and the second power rail gnd the gates of the transistors 830 and 840 are coupled to the common contact cp between the capacitor 820 and the resistor 810 the source and the drain of the transistor 830 are respectively coupled to the first power rail vdd and the substrate of the main transistor 850 the drain of the transistor 840 is coupled to the drain of the transistor 830 while the source of the transistor 840 is coupled to the.