versatile and compact circuit architecture involves dividing a bus into sections separated by switches actuated in phase opposition certain sections are coupled to computing operators whereas others are coupled to memories serving for reorganizing the order in which the data is presented to the following operators application_number US 77432291 A description the architecture of the circuit of the present invention is shown in fig4 it includes essentially a data transmission bus divided into sections separated from each other by switches which prevent or allow the passage of data from one section to the other the switches surrounding a given section are actuated in phase opposition so that one section may communicate with one or other of its two neighbors but not with both at the same time the switches are designated by i1 i2 etc in the order of their succession along the bus the closure phases for the switches are designated by phi and phib respectively phib being the logic complement of phi to each section are connected either one or more computation operators or a buffer memory the computation operators receive data arriving over a bus section to which they are connected and they deliver a result over this same section the buffer memories record data arriving over the section.