numbers in fig2 in which different levels of the drive signals are in each case present at the transistors t 1 to t 5 the prp signal is applied to a control input of the fourth transistor t 4 the prn signal is applied to a control input of the fifth transistor t 5 and the boost signal is applied to a control input of the second transistor t 2 the clock signal clk provided is present at the control inputs gate terminals of the first and third transistors t 1 t 3 in the case of which clock signal a level corresponding to the state of the clock signal clk is put at the potential of the output node a the first time window is characterized by a low level of the prp signal a high level of the prn signal a high level of the boost signal and a high level of the clock signal clk the first time window begins with a change in level of the prp signal and of the prn signal as a result the fourth and fifth transistors t 4 and t 5 are turned on closed and on account of the high level of the clock signal clk the third transistor t 3 is likewise turned on so that the first node k is connected to the second low supply potential.