100 to 200 u00b0 c may be used in step 680 for each polysilicon bounded test diode 100 n well 115 substrate 105 and polysilicon gate 125 see fig1 are held at ground potential in one example ground potential is about 0 volts in step 685 for each polysilicon bounded test diode 100 a pre determined voltage is applied to p diffusion region 110 see fig1 for at least a pre determined time in one example the predetermined voltage is about u2212 6 3 volts or less and the pre determined time is about 0 5 hours or more in step 690 for each polysilicon bounded test diode 100 the current through polysilicon gate 125 see fig1 is monitored for u201c soft u201d breakdown u201c soft u201d breakdown is defined as an increase in gate current of about 10 to 50 times the breakdown current of an unstressed gate u201c hard u201d breakdown is defined as an increase in gate current greater than about 50 times the breakdown current of an unstressed gate in the present example u2212 6 3 volts for 0 5 hours are the stress conditions referring to fig1 b in step 700 one or more test dram devices 300 is selected in step 705 each test dram device 300 is maintained at a pre selected temperature in one example the pre selected temperature is 160 u00b0 c however any temperature in the range of about 100 to 200 u00b0 c may be used in step 710 for each test dram device 300 n well contact 385 and bit line contact 390 see fig5 are held at ground potential in one example ground potential is about 0 volts in step 715 for each test dram device 300 word line contact 395.