through 70 are controlled by the system arbiter 62 at time t 1 the transfer originator a issues two transfer information items to the transfer destination 1 the transfer originator b issues two transfer information items to the transfer destination 1 and the transfer originator c issues two exclusive transfer information items to the transfer destination 1 and one transfer information item to the transfer destination 2 since the system arbiter 62 gives the highest priority to the transfer originator c in accordance with the sequential table 58 one of the two transfer information items of the transfer originator c is sent to the transfer destination 1 with no contention latency in a period between the times t 1 and t 2 the system arbiter 62 executes the transfer in the order of the transfer originator a the transfer originator b and the transfer originator c in accordance with the sequential table 58 and transfer complete notices are also sent in accordance with the sequential table 58 with no contention latency also in a period between the times t 2 and t 5 the command arbiters 13 and 14 the write data control circuits 30 and 31 and the transfer complete notice arbiters 68 through 70 are controlled in a similar manner in accordance with the sequential table 58 selected by each transfer originator so that the transfer can be controlled without grasping the states of the buses included.