an enabling signal on line 96 is high the signal having a relatively high voltage representing a logic state of 1 clock pulses from the clock 72 are passed by the and gate 74 in response to a high signal from the comparator 70 the term 34 high 34 utilized in describing the signals refers to a relatively high voltage representing a logic state of 1 while the term 34 low 34 utilized in describing these signals refers to a relatively low voltage representing a logic state of 0 the clock pulses passed by the and gate 74 are counted by the counter 76 the digital number appearing at the output of the counter 76 representing the count thereof being coupled via the switch 86 to the dac 88 the dac 88 converts this digital number to an analog voltage which is coupled via line 92 back to the comparator 70 when the amplitude of the signal on line 92 is less than the amplitude of the signal on line 90 the output of the comparator 70 is high as the count of the counter 76 rises the amplitude of the signal on line 92 increases to a point at which it equals the amplitude of the signal on line 90 when the point of equality is reached the output of the comparator 70 goes low thereby inhibiting the coupling of further clock pulses from the clock 72 to the counter 76 the count of the counter 76 is retained during such times as the signal on line 90 maintains its amplitude or reduces its amplitude however in the event that the signal on line 90 should again increase in amplitude then clock pulses from the clock 72 are.