layers and specifically changes to locations within programmable cells 42a 42d are reflected on the integrated circuit of wafer 44 at specific locations within programmable circuits 12 embodied therein the programmed circuits 12 are shown on wafer 44 as having an 34 x 34 placed at specific locations indicative of specific mask layer changes programmed programmable circuit 12 is shown to produce unique wafer 44 designated as 34 rev a 34 wherein the wafer modification program is at a location specific to bit 0 locations within device 10a bit 0 indicates a programmed logic level representative of the specific revision to mask layers 1 3 and n shown in fig5 the remaining devices 10b 10d are not changed and are reserved for subsequent revisions such as those shown in fig6 and 7 referring now to fig6 a second revision denoted as 34 rev b 34 possibly subsequent to rev a is shown specifically fig6 illustrates revisions to the first mask layer at locations 40a revisions to the third mask layer at locations 40c and revisions to the nth layer at locations 40n the revisions are also reflected in the programmable cell locations to 42a 42c and 42d it is appreciated from the drawings of fig5 and 6 that while the same mask layers can be changed a different revision code will result since the revisions are reflected at different binary locations i e bit 0 versus bit.