a resistor as shown in fig1 each column of the array has a blc line 40 41 4 n connected to one terminal of each magnetic memory element 7 x 0 7 x 1 7 xm in that column x takes on values from 0 to n and a blt line 50 51 5 n connected to the drains of the cell transistors 8 x 0 8 x 1 8 xm in that column x takes on values from 0 to n the drains of the cell transistors in each cell are connected to the other terminal of the magnetic memory element in that cell as shown in fig1 a first voltage source vd 1 is connected through a blt transistor 60 61 6 n to each blt line 50 51 5 n a second voltage vd 2 is connected through a blc transistor 70 71 7 n to each blc line 40 41 4 n as shown in fig1 the gates of the blt and blc transistors for each column are connected together and connected to a gate signal source as shown in fig1 the gates to transistors 60 and 70 are connected to gate signal y 0 the gates of transistors 61 and 71 are connected to gate signal y 1 and the gates of transistors 6 n and 7 n are connected to gate signal y n so that the first voltage source v d1 and the second voltage source v d2 can be applied to the blt and blc lines for each column of the array separately and individually the gates of the cell transistors in each.