voltage on the node 10 with the values of the resistive load 12 and the send logic high resistor 40 chosen appropriately the voltage on the electrical interconnect 18 will be slightly positive with respect to the low voltage on the node 10 this positive voltage will be received by the differential amplifier 34 resulting in the first received signal 14 the combination of the first received signal 14 and the first transmission signal 8 uniquely identifies the second transmission signal 24 allowing it to be reconstructed case 2 for the case in which both the first transmission signal 8 and the second transmission signal 24 are high representing logic 1 39 s the circuit operates as follows as in case 1 the high signal at 8 is inverted by the first inverter 36 supplying a low voltage to the node 10 the application of the second transmission signal 24 being high in this case to the gates of the cmos transistors 38 44 will cause the pmos transistor 38 to be turned off and the nmos transistor 44 to be turned on with the nmos transistor conducting the voltage in the electrical interconnect 18 will be low and no voltage drop will be detected across load resistance 12 by the differential amplifier 34 this results in a first received signal 14 being a zero voltage.