5 film an al 2 o 3 film or a stack of these films and have found the fact that the present invention is particularly effective for the insulators having a thickness of smaller than 6 nm in terms of silicon dioxide equivalent the thickness of the insulator in terms of silicon dioxide equivalent should preferably be greater than 2 nm when the thickness is smaller than 2 nm the insulator allows a large leakage current in this embodiment a voltage applied to the second capacitor electrode 7 is set to be higher than an ordinarily employed voltage of 0 5 vcc here the voltage vcc is the one which is higher than the other voltage that are applied to the bit lines 16 when the capacitor is to be electrically charged the lower voltage is in many cases 0 v therefore when the voltage of 0 v or vcc gt 0 is applied to the first polycrystalline silicon electrode 5 to store the charge in the capacitor the absolute value of negative voltage applied to the capacitor insulator 6 becomes smaller than that of the ordinary 0 5 vcc system in which the voltage 0 5 vcc is applied to the capacitor electrode 7 and the positive voltage increases on the other hand here the voltage applied to the capacitor insulator 6 is determined with the first polycrystalline silicon electrode 5 as a reference in the structure and the system of this embodiment the gate current is suppressed for the positive voltage applied to the capacitor insulator 6 just like in the aforementioned second embodiment although the voltage is larger than the one in the prior art therefore despite the thickness of the insulator being.