26 stores the contents of register 24 when the latter contains the final result of the operation i e the result ec nt which may then be read out either by another computer or by a digital analog converter not shown a circuit 28 forming a time base and containing a program memory makes it possible to control the computing operations by activating the circuits 10 12 22 24 and 26 according to a proper sequence the sum equ19 is available after n computing cycles in the following way after 24 and 26 have been cleared by the time base addition of the output of the multiplier and of the contents of register 24 namely g 0 qe n last after the nth cycle the time base causes transfer of the result from register 24 to output register 26 referring to fig2 a device of the invention fulfils the same function as that of fig1 without increasing the volume of the memory required for computing ec nt with the same number n of computing cycles for each value however without a multiplier in fig2 the time base and the program memory have not been shown for simplicity the elements corresponding to those in fig1 bear the same reference number in addition to illustrate the arrangement of the echo canceller in a station fig2 shows schematically a transmitter 30 delivering successive data qe nt to a transmission line 32 a sampler 34 provides successive.