lines 79 the gate electrodes 73 74 75 76 of the nmos transistor n 1 are connected to a power supply voltage node vdd and the gate electrodes 73 u2032 74 u2032 75 u2032 76 u2032 of the nmos transistor n 2 are connected to an input signal node ng the gates of the nmos transistors n 1 n 2 may be formed for example by a salicidation process the source regions s 1 s 2 s 3 of the first nmos transistor n 1 are connected to the drain regions d 3 d 4 d 5 of the second nmos transistor 72 through conductive layers 81 82 83 avoiding connection of these regions through a common diffusion region can help improve esd protection for the illustrated embodiments smaller narrower faces of the source regions s 1 s 2 s 3 of the first nmos transistor n 1 and the drain regions d 3 d 4 d 5 of the second nmos transistor n 2 face one another which can also reduce the effect of a parasitic npn transistor associated with these structures as shown a p type p guard ring gd may surround the insulation regions fox and may be connected the power supply ground node vss such a p type guard ring gd can further reduce the effect of the parasitic bipolar transistor as the guard ring gd can decrease base modulation of the parasitic bipolar transistor as shown in fig9 parasitic npn bipolar transistors q 1 q 2 q 3 q 4 are associated with the transistors n 1 n 2.