u00bd chip u00be chip to generate at least one delayed version of the signal then the signal and the delayed version s thereof are down sampled to lower the sampling rate the down sampled signals are latched by respective latches to be aligned with each other then the aligned signals are correlated with a local code replica by the respective correlators alternatively the aligned signals are respectively correlated with a local code replica and at least one delayed version thereof by the respective correlators the delayed version of the local code replica is delayed by the delay unit with u00bc chip for example it is noted that the chipping space such as u00bc chip or u00bd chip described in the above embodiments are described as examples rather than limitations to the present invention by using at least one delayed version of the incoming signal and correlating the incoming signal per se and the delayed version s thereof with the local code replica alternatively with the local code replica and at least one delayed version thereof the operation speed of the correlators of the fractional correlation device can be significantly lowered that is the calculation load for each correlator is decreased as compared to the prior art therefore the power consumption can be reduced which is very desirable to the spread spectrum receiver such as a cdma receiver for example while the preferred embodiments of the present invention have been illustrated and described in detail various modifications and alterations can be made by persons skilled in this art the embodiment of the present invention is therefore described in an illustrative.