beginning of the period which represents non busy status on the bus therefore both sio and sck lines remain high in the u201c b u201d portion is represented the start condition for transfer data a high to low transition of the sio line while the clock sck is high determines a start condition all commands must be preceded by a start condition in the u201c c u201d portion is represented the period for memory selection in which i 2 c code has been set in the u201c d u201d portion is represented the period for expandable memory selection with the suspend resume code set as for the traditional control byte there is a partial timing overlapped with above said 8 bit codes at portions u201c c u201d and u201c d u201d in the u201c e u201d portion is represented that the write command has been set in the u201c f u201d portion is represented the stop condition without transferring data a low to high transition of the sio line while the clock sck is high determines a stop condition then the write operation proceeds to activate in other words all the program erase operations will automatically start step by step which is controlled by the internal state machine in the u201c g u201d potion the read operation that follows is activated by a start condition with a read command code note that the read operation cannot be applied to the memory portion which is undergoing a write operation except the sram owing to the fast speed alterability.