an extreme example the later stages coalesce to a single route application_number US 5355298 A description the present invention provides pipelined analog to digital converter architectures which accurately and rapidly digitize analog outputs for arrays of detectors such as cmos photodiode arrays the invention accomplishes this by employing a 34 tree 34 architecture in which the converter employs more instances of earlier stages than of later stages in the pipeline in the following description various specific details are set forth in order to fully illustrate preferred embodiments for accomplishing the analysis of this invention for example certain specific applications of the invention e g providing the architecture on a cmos photodiode array chip will be described it should be understood however that the invention may be practiced without limitation to the specified details and applications presented herein the time constant required for the interstage amplifier 34 and the adder 24 see fig1 and that together determine the speed of the stage relaxes from the earlier stages to the later stages of the pipeline this can be understood by considering the mathematical approximation for an interstage amplifier 39 s time constant u03c4 assuming a single pole amplifier and assumming that it is not slew rate limited tsettle is the settling time requirement for the pipeline stage components under consideration in the stage design depicted in fig1 these components are adder 24 and multiplier 34 the settling time represents the time required to process one datum from all the channels handled by the stage instance it is generally one half the sampling frequency obviously as a stage handles more channels pixels the allowed settling time decreases.