early and the bit leveling process therefore determines that a delay of ta u2212 tb 2 quote is to be added to dq to align the center of a dq data bit u201c 0 u201d value as close as possible with the rising edge of dqs in general by determining the size of these delay measurement windows the bit leveling process determines if dq is being sampled too early or too late and therefore adjusts the delay on dq to sample it correctly an exemplary flowchart 300 for this process is shown in fig3 in step 302 a 0 1 0 1 pattern is installed such that it can be received by a data interface according to the invention during a calibration operation in this example such a pattern is installed in a dram according to step 304 while continuously receiving the 0 1 0 1 pattern a programmably delayed version of a dq data bit is sampled on the rising edge of dqs u2014 where dqs has been delayed by 90 u00b0 plus a suitable programmable delay as described previously it is expected that given the data pattern received for this scenario that when first sampled a value of u201c 0 u201d will be sampled given the initial setting of the dq programmable delay line in an alternate embodiment a value of u201c 1 u201d might instead be the expected value per step 306 from the initial delay line setting for dq dq is subsequently delayed in time by some number of delay line increments until a u201c 1 u201d is sampled and the total number of delay line increments required to achieve this point is recorded relative to the initial setting as ta per step 308 dq is advanced.