and the overflow signal are inactive 0 the next count output 460 of the next count selector 545 is also the binary u2018 1 u2019 fig7 is a plot showing the structure of a virtual counter and physical counter placed within the virtual counter for increasing the time base of the virtual counter as implemented within a configurable debounce circuit 135 of fig5 illustrating an adjustment to increase a time base the virtual counter 600 is defined as having a number n bits ranging from the least significant bit 0 to the most significant bit n u2212 1 in this example the physical counter 605 is initialized to have its origin at the least significant bit of the virtual counter 600 the current window 610 is defined as the present location of the physical counter 605 in this example the physical counter 605 has been incremented to contain the count 11101010101 referring additionally to fig5 the time base change is defined by the source debounce time 125 and generated by the time base generator 415 for transfer to the n bit virtual count controller 450 the new window 615 is defined to place the least significant bit of the physical counter 605 the k bit count register 455 at the location j the contents of the physical counter 605 are now 000 1110 with the remainder of the previous physical counter 605 is 1010101 620 and is to be masked out to be reset to be.