conventional process flow and how it is minimized according to one aspect of the present invention the process starts in step s 100 when the specification for the asic is defined the design architecture is built in step s 101 and the register transfer logic u201c rtl u201d design is completed in step s 102 thereafter the physical design is completed in step s 103 and the masks for actual fabrication is performed in step s 104 wafer fabrication occurs in step s 105 and the chip assembly is tested in step s 106 a functional laboratory test is performed in step s 107 if the functional test is successful then the chip is released for production in step s 110 in the conventional processes if the functional test fails and any changes have to be made in the asic or state machines the design process for the change is repeated from step s 102 this iterative process continues until the chip is acceptable this is expensive and tedious the present invention solves this problem by using a processor inside the asic to control the state machine thereby reaching the final goal of production quickly and inexpensively in step s 109 after the functional laboratory test control is passed to a processor and the processor can be programmed to perform a function typically the function that failed in the functional test efficiently once the processor solves the functional problems the chip is sent for production in step s 110 details regarding steps s 109 are provided below with respect to fig2 and 3 fig2 shows a system diagram of an asic 210 that includes a general purpose state machine 200 operationally coupled to a.