the substrate surface 18 is removed as well also in block 120 the dielectric layer 48 is deposited over the region in which the digital device 14 will be formed process 110 proceeds to block 122 where barrier layers 52 and 54 and dummy gate layers 96 and 98 are deposited on the dielectric layers 44 and 48 respectively the multiple layers are then patterned to form the temporary gate structures 92 and 94 also the ild layer 72 is formed over the substrate and the temporary gate structures a gate replacement process is then performed over the course of blocks 124 and 126 specifically in block 124 the dummy gate layers 96 and 98 are removed from the temporary gate structures 92 and 94 which creates the openings 100 and 102 above the barrier layers 52 and 54 next in block 126 the openings 100 and 102 are respectively filled with the work function layers 56 and 58 and the metal fill layers 60 and 63 to form the gate structures 68 and 70 also ild layer 72 is enlarged in a vertical dimension finally process 110 proceeds to block 128 where the gate contact 82 is formed to engage the gate structure 68 at a location over the recess 26 in the isolation structure 20 also the gate contact 84 is formed to engage the gate structure 70 at a location over the isolation structure 30 the semiconductor device 10 is not limited to the aspects of the integrated circuit described above moreover altering the order of.