hole 171 a method of fabricating a ferroelectric memory device according to some embodiments of the present invention will now be described more fully hereinafter with reference to fig8 through fig1 referring now to fig8 a device isolation layer 53 is formed in a predetermined area of a semiconductor substrate 51 to define a plurality of active regions 53 a a gate insulating layer a gate conductive layer and a capping insulating layer are sequentially formed on the semiconductor substrate 51 the capping insulating layer the gate conductive layer and the gate insulating layer are successively patterned to form a plurality of gate patterns 60 crossing over the active regions 53 a and the device isolation layer 53 each of the gate patterns 60 includes a gate insulating layer pattern 55 a gate electrode 57 and a capping insulating layer pattern 59 preferably the gate patterns 60 are formed along the row direction y axis of fig4 using the gate patterns 60 and the device isolation layer 53 as ion implantation masks impurities are implanted into the active regions to form three impurity regions in each of the active regions a central impurity region corresponds to a common drain region 61 d and the other regions correspond to source regions 61 s therefore a couple of cell transistors are formed in each of the active regions the cell transistors are arrayed on the semiconductor substrate 51 along row and column directions then a spacer 63 is formed on a sidewall of the gate pattern 60 using for example conventional processes referring now to fig9 a first.