generating circuit 15 based on the maximum value or on the integrated value of the electrical energy and processing is performed such that values of the threshold value or above are unchanged and values lower than the threshold value are discarded replaced by zero reducing the influence of noise and the processing result is sent to the fft circuit 16 the fft circuit 16 performs fft processing based on the electrical energy supplied from the delay profile threshold value generating circuit 15 converting into values equivalent to the transfer function of the frequency region generated by the channel and supplies the conversion result to the equalizer 17 the equalizer 17 multiplies the output signal of the fft circuit 12 by the complex conjugate in the conversion result of the fft circuit 16 removing the transfer function component generated in the channel and converting into a signal that can be ofdm demodulated and the output signal thereof is sent to the combining circuit 30 in the arithmetic circuit 20 too substantially the same arithmetical processing as performed as in the arithmetic circuit 10 namely the fft window extraction circuit 21 extracts the fft window 21 a from the output signal s 3 of the thinning circuit 3 and passes the.