preferred access to the memory 10 furthermore there is a possibility of using the bridge 15 as a small cache memory so that fewer memory accesses from the side of the system microcontroller to the memory 10 are necessary in this manner also any possible waiting cycles with respect to the system microcontroller accessing the memory are shortened to the system microcontroller 13 is further assigned a further data memory 16 in the form of a dram or sram integrated on the chip this data memory may have a capacity of 32 k with a transmission width of 32 bits on the data bus 14 the system microcontroller 13 has immediate access to the further data memory 16 in order to also enable the digital signal processor 2 to have access to the further data memory in which volatile short term data are stored a dma controller 17 is provided which is also connected to the data bus 14 and a further bridge 18 which is connected to the sub system internal bus 6 c it is true the further data memory 16 works very slowly compared to the high clock frequency of the digital signal processor 2 as a result of which it will rarely be accessed this access however is possible by means of the dma controller 17 and the bridge 18 which bridge is again arranged for the synchronization between the different data buses and the clock frequencies to the data bus 14 is further connected a boot rom 19 via which the original configuration of the memory.