conversion is to be started next in a respective adc 3 a 3 b 3 c 3 d for synchronizing purposes the arbiters 9 a 9 b of adcs of the same synchronization group have to run have to be started in parallel or more exactly the state machines of the respective arbiters 9 a 9 b the same e g applies to the analog parts 8 a 8 b e g to internal dividers comprised in the analog parts 8 a 8 b of adcs of the same synchronization group to adc kernel clocks controlled by respective kernel clock controls 10 a 10 b of the respective adcs etc see fig3 for carrying out a synchronized start of the arbiters 9 a 9 b analog parts 8 a 8 b etc a variable anon analog on stored in a register 11 a 11 b of a respective adc is set to a first predefined value e g to u201c 00 b u201d see fig3 as will be described in further detail below if a respective adc is a u201c master u201d adc or an u201c autonomous u201d adc the value stored in the register 11 a 11 b e g the above first predefined value u201c 00 b u201d is supplied via a multiplexer 12 a 12 b to a further register 13 a 13 b stored therein and supplied to the respective.