as long as the integrator ota gain is high enough to avoid a dead zone of calibration u03b4 u03c3 adc in reality the calibration resolution is usually limited by circuit thermal noise and calibration time a higher order u03b4 u03c3 adc can generally relax the gain requirement of the ota and thus shorten the calibration time the conventional algorithm of a sar adc uses the u201c test keep or discard u201d strategy for every bit to encode analog input as described above for example after the input is sampled the msb is tested first by connecting the bottom plate of the msb to v ref and those of all lsbs are connected to ground if the test result comparator decision is positive the msb needs to be discarded or the bottom plate of the msb needs to be grounded if the test result is negative the msb needs to be kept or the bottom plate of msb needs to stay connected to v ref for the rest of conversion cycles then the same procedure is repeated from the second msb to the lsb sequentially such an algorithm has two disadvantages the first one is related to the asymmetry of the redundancy range and the second one is related to the accumulated calibration error introduced noise floor under small signal conditions fig4 illustrates the asymmetry of the redundancy range the redundancy range of the msb is between r 3 lsb and r 2 r 2 lsb in other words if the analog input v.