to 500 nm and impurities are introduced by predeposition or an ion implantation method whereby the gate electrode 8 is obtained here the first conductivity type or the second conductivity type may be adopted the gate electrode 8 is patterned with the use of a resist film 9 whereby a transistor structure having the trench 6 as illustrated in fig2 e is completed continuously as illustrated in fig2 e impurities are implanted so as to form a source region and a drain region by a self alignment method in this case a self alignment method is irrelevant to the essence of the present invention as the impurity implantation to the source region and the drain region in a case where the conductivity type is n type ion implantation in which arsenic or phosphorus is implanted preferably at a dose ranging from 1 u00d7 10 15 atoms cm 2 to 1 u00d7 10 16 atoms cm 2 is performed on the other hand in a case where the conductivity type is p type ion implantation in which boron or boron difluoride is implanted preferably at a dose ranging from 1 u00d7 10 15 atoms cm 2 to 1 u00d7 10 16 atoms cm 2 is performed here the impurity implantation to the source region and the drain region can be performed simultaneously under the same conditions when another mos transistor having no trench 6 within the same chip is manufactured after that as illustrated in fig2 f the resultant is subjected to heat treatment at a temperature ranging from 800 u00b0.