period fig3 shows the association of some of the act timing parameters to the hardware detailed in the dashed box of fig2 as can be seen in fig3 an input pedistal delay of tau1 exists from the time an electron packet sample is taken at terminal a1t1 to the time it enters the storage region of fet channel f1 the storage length of the fet channel is defined as deltat which corresponds to the saw s1 tap spacing it is within this fet channel that the interrupt field cause the act to store charge packets an output pedistal delay tau2 exists from the time a packet exits the fet channel storage region to the time the act output signal appears on act output tap a1t2 the total propagation delay of the act is equal to the sum of tau1 deltat and tau2 tau1 and tau2 can be made relatively small on the order of nanoseconds and they need not necessarily be made equal the interrupt field voltage supplied to fet channel f1 to store act input int1 is generated by hold and release circuit hr1 shown in fig3 only located outside the dashed box of fig2 the point in time when hold and release circuit hr1 asserts and releases the interrupt field is determined by radar system timing parameters such as the radar system clock and interpulse period time marks fig4 is a timing diagram of clutter cancellation of two interpulse periods time moves from left to right in the diagram two interpulse periods are shown the first interpulse period follows the first transmit pulse interval 400 the second interpulse.