in the case of the passthrough mode where bsi is the same as the input data the signals one is at a logical u201c 1 u201d oneb lt 0 gt at u201c 0 u201d and oneb lt 1 gt at u201c 0 u201d this will disable the pull up or pull down but enable the transfer gate 522 to pass the data on the pbus 505 to the output 523 in the case of the inverted mode where bsi is the invert of the input data the signals one is at u201c 0 u201d oneb lt 0 gt at u201c 1 u201d and one lt 1 gt at u201c 1 u201d this will disable the transfer gate 522 also when pbus is at u201c 0 u201d the pull down circuit will be disabled while the pull up circuit is enabled resulting in bsi being at u201c 1 u201d similarly when pbus is at u201c 1 u201d the pull up circuit is disabled while the pull down circuit is enabled resulting in bsi being at u201c 0 u201d finally in the case of the floated mode the output bsi can be floated by having the signals one at u201c 1 u201d oneb lt 0 gt at u201c 1 u201d and oneb lt 1 gt at u201c 0 u201d the floated mode is listed for completeness although in practice it is not used fig1 a illustrates a preferred embodiment of the output logic of the common processor shown in fig1 the signal at the bsi node from the input logic 520 is latched in the processor latch platch 510 the output logic 530 receives the data mtch and mtch from the output of platch 510 and depending.