metallization layer m x u2212 1 a via layer v x u2212 1 and a second metallization layer m x an interlevel dielectric layer 502 is used to contain the various metallization and via layers in embodiments the interlevel dielectric layer 502 may be comprised of an oxide such as silicon oxide sio2 tetraethoxysilane teos oxide or other suitable material such as a low k dielectric material e g k lt 4 while two metallization layers are shown in fig1 in practice there can be many more metallization and via layers disposed between the two metallization layers m x u2212 1 and m x is a mim capacitor 508 the mim capacitor 508 comprises a first plate 512 and a second plate 514 disposed between first plate 512 and second plate 514 is capacitor dielectric layer 516 in embodiments the first plate 512 and second plate 514 may be comprised of titanium nitride tin boron doped titanium nitride tibn or of tantalum nitride tan other materials may also be used in embodiments dielectric layer 516 may comprise hafnium oxide and or aluminum oxide in embodiments the second bottom plate 514 may extend at a distance d 5 beyond the first top plate 512 in embodiments distance d 5 may range from about 500 nanometers to about 2 micrometers a barrier layer 506 is disposed above the metallization region 507 which belongs to.