block diagram of scheduling engine 522 according to some embodiments of the invention as shown in fig1 scheduling engine 522 may include a data processing system 1302 which may include one or more microprocessors and or one or more circuits such as an application specific integrated circuit asic field programmable gate arrays fpgas etc a network interface 1304 and a data storage system 1306 which may include one or more non volatile storage devices and or one or more volatile storage devices e g random access memory ram as shown data storage system 1306 may be used to store scheduling tree state information in embodiments where data processing system 1302 includes a microprocessor computer readable program code 1343 may be stored in a computer readable medium 1342 such as but not limited to magnetic media e g a hard disk optical media e g a dvd memory devices e g random access memory etc in some embodiments computer readable program code 1343 is configured such that when executed by a processor code 1343 causes scheduling engine 522 to perform steps described above e g steps describe above with reference to the flow chart shown in fig8 in other embodiments scheduling engine 522 is configured to perform steps described above without the need for code 1343 that is for example data processing system 1302 may consist merely of one or more asics hence the features of the present invention described above may be implemented in hardware and or software for example in particular embodiments the functional components of scheduling engine 522 described above may be implemented by data processing system 1302 executing computer instructions 1343.