box upper silicon layer 115 is doped p type and will serve as the p well of the vertical nfet formed in an upper portion of silicon layer 105 adjacent to box layer 110 is a p type silicon layer 120 formed on top of upper silicon layer 115 is a pad oxide layer 125 comprising silicon dioxide and formed on top of the pad oxide layer is a pad nitride layer 130 in one example p type silicon layer 120 is formed by ion implantation in one example pad oxide layer 125 is formed by thermal oxidation of a top surface of upper silicon layer 115 and pad nitride layer 130 is formed by low pressure chemical vapor deposition lpcvd of silicon nitride in one example upper silicon layer 115 has a thickness between about 25 nm and about 1000 nm box layer 110 has a thickness between about 10 nm and about 500 nm p type silicon layer 120 has a thickness between about 25 nm to about 100 nm pad oxide layer has a thickness of between about 2 nm to about 10 nm and pad nitride layer 130 has a thickness between about 100 nm and about 2000 nm in fig2 trenches 135 are etched from a top surface of pad nitride 130 through pad oxide layer 125 upper silicon layer 115 through box layer 110 and through p type layer 120 and an optional conformal diffusion barrier 140 formed on the sidewalls and bottom of the trenches in one example trenches 135 are formed by a photolithographic process using an optional hard mask and a reaction ion etch.