acl applied thereto if ac1 is equal to a logical 1 circuit 10 senses a positive edge of input ca1 applied to conductor 12 if ac1 is a logical 0 sensing circuit 10 senses a negative edge of ca1 ac7 is in one embodiment of the invention the output of the register bit labeled 40 having a q output connected to conductor 16 and a set input connected to output node 40 the signal on output node 40 sets a logical 1 in register bit 40 and the resulting signal on ac7 34 acknowledges 34 that the edge positive or negative depending on the level of ac1 has been sensed briefly the operation of the circuit of fig1 is that if e is at a logical 1 at the time that an edge of ca1 occurs that edge will be sensed however if e is equal to a logical 0 at the time that the edge of ca1 occurs then the level rather than the edge ca1 is sensed referring to fig3 it is seen that input ca1 undergoes negative transition a after e has already risen to a logical 1 level in response to this node 14 which is ca1 goes to a logical 1 ac1 during this time is at a logical.