domain 12 is sensed at the fourth power supply node 110 sensing the reference voltage at the fourth power supply node 110 indicates that a logical one is stored in the memory cell 46 conversely if a logical zero is stored in the memory cell 46 the voltage level at the second node of the memory cell 46 will be the reference voltage vcell of the memory cell 46 accordingly the second read transistor 56 of the read port 52 will be switched on and the rbl 84 starts discharging and will continue to discharges to ground under current scenario accordingly when the voltage level of the third power supply node 108 is set to reference voltage of the second domain 12 the pre charge transistor 44 is switched off and a lower voltage level at rbl 84 is sensed at the fourth power supply node 110 sensing the reduced using conventional sense amplifier or zero voltage using a conventional inverter stage at the fourth power supply node 110 indicates that a logical zero is stored in the memory cell 46 the power supply configuration of fig3 ensures that the first domain 10 read domain and the second domain 12 write domain are isolated and domain cross over is prevented the first domain 10 writes data to the memory cell 46 by driving the first power supply node 100 and the second power supply.