if the information stored in the mnos capacitance 2 is to be erased then a positive voltage pulse of a magnitude of approximately 30 v and a duration of approximately 10 u03bc sec is applied to the write line 20 this corresponds to the instant t 3 in fig3 in the case of a second functional mode of the memory element in accordance with this invention the element is written in and read out at the write line 20 as a common single transistor memory element with an inversion layer capacitor for the operation with given voltages in particular 15 v if the data contained in the memory is to be stored for a very long time prior to the switching off of the current supply the information containedin the element is written into the mnos capacitor by way of corresponding voltage pulse at the write line 20 herefore as described hereinabove a 30 v is applied to drive line 20 the surface potential of the inversion layer will be 0 v in the elements wherein a 34 0 34 has been written thus a reloading of the states in the dielectric of the memory capacitor will be effected causing a prospective shift in the flat band voltage in the elements wherein a 34 1 34 has been written the surface potential has a negative value for instance 15v the voltage of approximately 30 v applied at the write line does not cause a shifting of the flat band voltage this writing in into the more permanent memory state may be effected element by element line by line or matrix by matrix two versions of.