601 to so 803 via multiplexer 806 in the data scan mode the 3 bit ir 805 is disabled and the lir simply forms a bypass connection between the so 605 of test architecture 601 and the so 803 of the lir thus during data scan operations the lir is included in the data scan path between si 604 and so 803 but it does not add to the bit length of the data scan path also since the control bus 109 is gated off during data scan operations the data contained in the lir 39 s ir 805 cannot be changed during data scan operations it should be noted that while the lir 801 has been shown inserted in the serial output path from the test architecture 601 i e lir input 802 connected to test architecture so output 605 it could be have been similarly inserted in the serial input path to the test architecture 601 as well i e lir output 803 connected to test architecture si input 604 thus the position of the lir 801 with respect to it being positioned at the beginning or ending of the serial path through the test architecture does not impact its ability to provide control of the link 606 and enable 607 bus inputs to the test architecture 601 fig8 b illustrates that the circuitry of the 3 bit ir 805 consists of a 3.