of decoded address lines 16 identifying a particular memory word 34 of memory 14 to be read from or written to the particular device the processor subsystem 12 also communicates with the memory via data lines 18 passed through from the processor transmitting the data from the data bytes 36 of the particular memory word 34 in a case of a reading of the memory 14 and to the data bytes 36 of the particular memory word 34 in case of a writing of the memory 14 parity lines 20 passing through control circuitry 22 as will be described below connect with the memory 14 by lines 20 39 and allow writing to or reading from the parity byte 38 addressed by the processor subsystem 12 the parity lines 20 39 are four bits wide in this example and the data lines 18 are 32 bits wide with each of the data bytes 36 providing a successive eight bits of the 32 bit word control lines 24 also pass between the processor subsystem 12 and the memory 14 via the control circuit 22 on lines 24 from the processor subsystem 12 to the control circuit 22 then on lines 24 39 to the memory 14 including for example read and write lines to be described a clock 26 provides a clock signal on line 27 through control circuit 22 to line 27 39 to processor subsystem 12 for the timing of its internal operations according to well known techniques processor subsystem 12 also provides decoded 34 byte write 34 signals 25 to the control circuit 22 which include.