28 form a resistive capacitive u201c rc u201d configuration the divider stage 12 via the rc configuration generates a divided voltage signal div_vdd where div_vdd vdd z 2 z 1 z 2 and where z 1 r 1 c 1 and z 2 r 2 c 2 those skilled in the art will appreciate that the rc configuration within the divider stage 12 allows for filtration of certain frequencies by selecting and or adjusting values for one or more of the resistors or capacitors in other words the resistors 26 28 in the divider stage 12 may be tunable so as to allow voltage division to be cut off above a specific frequency effectively eliminating performance inhibiting high frequency noise from the voltage division those skilled in the art will appreciate that the elimination of high frequency noise in voltage monitoring may allow for more accurate voltage measurement div_vdd serves as an input to the buffer stage 14 the buffer stage 14 has an operational amplifier 30 that is configured in a unity gain voltage follower arrangement a biasing circuit 32 is used to bias the operational amplifier 30 the output of the operational amplifier 30 buf_div_vdd serves as both negative feedback to the operational amplifier 30 and an input to the output stage 16 the output stage 16 has a transmission gate 34 which is formed by a pmos transistor 36 and nmos transistor 38 depending on signals from the voltage sensor 39 s computer chip the transmission gate 34 switches u2018 on u2019 causing buf_div_vdd to pass to an output out of the on chip voltage sensor 10 those skilled in the art will appreciate that the signal on out may be sent off chip to indicate the voltage measurment one purpose of the buffer stage 14.