
{"publication_number": "US-8276120-B2", "abstract": "the exemplary embodiment is for an architecture integrated in a generic system on chip and consisting of reconfigurable coprocessors for executing nested program loops performed in a functional unit array in parallel . the data arrays are accessed from one or more system inputs and from an embedded memory array in parallel . the processed data arrays are sent back to the memory array or to system outputs and enable the acceleration of nested loops . the coprocessors are connected either synchronously or using asynchronous first in first out memories , forming a globally asynchronous locally synchronous system and each coprocessor can be programmed by tagging and rewriting the nested loops in the original program and produces a coprocessor configuration per each nested loop group , which is replaced in the original code with coprocessor input / output operations and control .", "application_number": "US-24763808-A", "description": "the coprocessors derived from the proposed architecture template are capable of manipulating n - bit data words . we distinguish between constants : single data words read from a configuration register file variables : single data words read from functional unit outputs arrays : collection of data words read from memories the architectures are capable of executing one or more consecutive nested loop groups according to the following meta - language definitions : { nested_loop_group 