schematic diagram of a connection relationship and an eye diagram of control signals between a memory controller and two memory modules according to an embodiment of the present invention respectively a memory controller 400 includes an address translating unit 402 a control signal translating unit 404 and a clock generating unit 406 the clock generating unit 406 generates the first clock signal clk 1 and the second clock signal clk 2 the control signal translating unit 404 generates the command signal cmd and the address translating unit 402 generates the bank control signals bank 2 0 and the address signals a 15 0 depending on the number of ddr memory modules the clock generating unit 406 may generate individual clock signals to the ddr memory modules respectively as shown in fig3 a the first clock signal clk 1 connects to a first ddr memory module 410 and the second clock signal clk 2 connects to a second ddr memory module 420 further the first ddr memory module 410 and the second ddr memory module 420 share the address signals a 15 0 the command signal cmd and the bank control signals bank 2 0 that is the first ddr memory module 210 latches the data in the address signals a 15 0 the command signal cmd and the bank control signals bank 2 0 according to the first clock.