voltage drop along the data lines and provides more energy to switch bit lines or the corresponding memory columns it also produces less drop on the bit lines as a result of doing a mask during the block write operation application_number US 80826897 A description in fig1 is shown the prior art connection of address circuitry 10 to bit switch bs 12 by means of control line 11 through 17 s0 through s255 each bit switch 12 having a connection to the same data line dl 13 and the same data line bar dlb 14 shown only in the expanded view of the bit switch bs0 12 each bit switch 12 is connected to a different differential pair of bit lines represented by bit line zero bl0 15 and bit line bar zero blb0 16 these bit lines 15 16 connect to a memory column where each bit switch 12 connects to a different memory column there are two hundred and fifty six bit switches bs0 through bs255 12 23 corresponding to the same number of different memory columns and bit lines 15 16 fig2 shows the data connections for the prior art of fig1 the bit switches 12 in fig2 are connected to the dl 13 and the dlb 14 of the output of the data.