and 66 are incorporated in a circuit for transferring an operation switching signal poll to the gate of a transistor 68 for switching polling data and read data an inverter 69 is interposed between the gates of the transistors 68 and 70 the gate of the switching transistor 63 is connected to an inverter 62 and the inverter 62 is connected to a nor circuit 61 one input terminal of the nor circuit 61 receives an address change detection signal atd via an inverter 60 whereas the other input terminal receives a signal pollb which is output from the inverter 69 and input to the transistor 70 the above inverter 60 to latch circuit 67 constitute delay unit 600 in the output signal control circuit of the fourth embodiment having this arrangement before a predetermined time elapses after an address ad changes for the switching signal poll for polling data and read data in a suspend read by automatic algorithm operation of a write erase in a flash memory i e during sense operation of read data in the sense amplifier 1 u201c h u201d level period of the address change detection signal atd the signal pollb can be delayed until the address change detection signal atd changes to u201c l u201d level even if the operation switching signal poll changes to u201c l u201d level as shown in the timing chart of fig1 switching.