an input 140 that may receive the signals pn_wd_ 0 n an input 142 that may receive the signal iwdc_ref and an input 144 that may receive the signals sw_vee_ 0 n the driver circuit 104 may have an output 150 that may present a signal e g hwp and an output 152 that may present a signal e g hwn the driver circuit may be implemented as a number of sub driver circuits to be described in more detail in connection with fig2 in one example the particular number of driver circuits may be a 1 to 1 ratio to the particular number of write heads implemented in a particular drive system however other ratios such as 1 driver for a number of write heads may be implemented to meet the design criteria of a particular implementation in general each write head receives a differential signal hwp and hwn the write head block may have an input 156 that may receive the signals hwpa n an input 158 that may receive the signal hwna n and an input 160 that may receive the signal gnd in one example the writer circuit 100 may be implemented as an all npn transistor design therefore data rates may be extended beyond what is currently available the costs associated with an all npn design may be lower than a design implemented with a complementary npn pnp process the circuit 100 may also reduce power consumption compared with conventional approaches for example the writer circuit 100.