pattern width an antireflection film may additionally be stacked thereon to promote consistency referring to fig6 using a photoresist pattern not shown the hard mask layer 245 is etched to form a mask pattern exposing a trench area using the mask pattern the etch protection layer 240 is etched thereafter the etch protection layer 240 is etched again by means of an etchant to the polysilicon layer 230 and gate insulating layers 220 and 221 until the relatively thinner gate insulating layer 221 in the cell area is completely removed as a result the lower portion of the gate insulating layer 220 remains in the high voltage area to a thickness of 100 u00e5 300 u00e5 referring to fig7 the remaining gate insulating layer 220 is removed by means of an etchant wherein an etching selectivity of a silicon substrate to the gate insulating layer is in the range of approximately 1 1 to 3 1 when the substrate 210 in the high voltage area becomes exposed the p well 207 in the cell area has become partially etched as shown by means of the etchant thus a trench is formed to a thickness of 100 u00e5 900 u00e5 referring to fig8 the substrate 210 in the cell area and the high voltage area is continuously etched an etchant capable of etching silicon and silicon oxide may continuously be used alternatively an etchant having a greater etching selectivity with respective to the silicon may be used a trench depth difference in both areas is maintained or alternatively may be reduced because an etching rate of the high voltage area is somewhat higher for example assume an initial trench depth difference between the high voltage area and the cell area of 600 u00e5 since the high voltage area is quickly etched.