one processing unit an interconnect means is provided for connecting the memory means and the cache memory means the cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means application_number US 81576406 A description fig1 shows a block diagram of a basic architecture of a system on chip according to the invention such a system on chip may be implemented as or on an electronic device or a data processing system the system on chip comprises at least one processing unit 10 only one processing unit is depicted a cache means 20 associated to the processing unit 10 the cache means 20 is connected to a memory 40 via a bus 30 the cache 20 serves to cache data from the memory i e those data items which will be needed during upcoming processing cycles are fetched from the memory before their actual processing the cache means 20 comprises m cache lines 25 or cache blocks as well as cache controller cc the m cache line 25 may comprise the data d 1 d 2 dm the last data d 0 which has been read from or has been written to the cache lines 25 is stored in the cache controller cc or in the cache means 20 once a cache miss has occurred a cache controller cc has to select the data item or the block currently stored in the cache which is to be replaced with the desired data item or data block to be fetched the actual cache replacement can be performed on a randomly basis a least recently used lru basis.