and forming a low dielectric constant insulating layer having a specific dielectric constant lower than the specific dielectric constant of silicon oxide on the first hydrophobic insulating layer having a bydrophilized surface a semiconductor device manufacturing method which can suppress peel off of a low dielectric constant insulating layer from an underlying hydrophobic layer is provided application_number US 41024703 A description an embodiment of the invention will be described with reference to the accompanying drawing as shown in fig1 a an element isolation trench or trenches are formed in the surface layer of a silicon substrate 10 and insulating material such as silicon oxide is filled in this trench to form a shallow trench isolation sti 11 if necessary before or after sti is formed ions are implanted to form a desired well or wells in the surface layer of the silicon substrate 10 a number of active regions are defined being surrounded by sti 11 on the surface of each active region of the silicon substrate 10 an insulated gate electrode is formed which is made of a lamination of a gate insulating film 14 a polysilicon gate electrode 15 and a silicide electrode 16 side wall spacers 17 are formed on both side walls of the insulated gate electrode the insulated gate electrode structure is collectively represented by g before and after the side wall spacers 17 are formed desired ions are implanted to form source drain regions with extensions a cmos transistor structure can be formed by forming n and p channel transistors after semiconductor elements such as mos transistors are formed a phosphosilicate glass psg layer 18 is deposited to a thickness of about 1 5 u221e m by chemical vapor deposition cvd at a substrate temperature of 600.