the upper insulating layer 126 a cell poly or plate electrode 136 is disposed over the capacitor or cell dielectric 134 to form the capacitor 138 of each memory cell the formation of the recesses 144 in the storage poly nodes 132 results in an increase in the surface area of the capacitor 138 this results in lower refresh rates easier sensing of the contents of the cell due to a greater potential difference between bitlines and a reduction in the pitch constraints on the layout of the memory cells due to smaller capacitors fabricated by the method of the present invention being able to achieve a predetermined capacitance fig5 and 6 illustrate oblique views of two embodiments of the mask 130 as shown in fig2 fig5 illustrates an embodiment where the apertures 140 are holes through the mask 130 and the boundary openings 142 are avenues wherein the diameter of the holes of the apertures 140 is smaller than the width of the avenues of the boundary openings 142 fig6 illustrates an embodiment where both the apertures 140 and the boundary openings 142 in the mask 130 are avenues wherein the avenues of the boundary openings 142 are wider than the avenues of the apertures 140 this invention.