of the instruction pipeline stages also wake up to permit the instruction to flow from stage to stage progressing through fetch decode read execute and write fig5 depicts an exemplary power saving methodology and program sequence for the present invention as an initial step after having completed any previous communication tasks the processor 100 specifies the wake up conditions that will be used to wake up the processor along with a time out period at step 502 for example the conditions to observe and the wake up interval may be specified by registers which are loaded by a power saving program the processor may then deactivate certain nonessential modules at step 503 in a selected embodiment these modules are those whose deactivation is controlled by the processor 39 s instructions with step 503 the psm 39 s instructions power down some modules generally by writing appropriate values into the modules 39 control registers prior to the psm 39 s execution of the sleep instruction the processor detects and executes a sleep instruction at step 504 this sleep instruction detection functionality may be implemented by control logic in the processor 100 in one implementation the instruction decode logic in the processor 100 may be extended to detect the sleep instruction step 504 upon receipt of a sleep instruction the processor logic determines that preceding instructions in the pipeline 140 have completed step 506 prior to deactivation upon completion of the.