being input into the delay circuit 330 the signal cmo rather than the setdrn signal is delayed the input terminal of the pmos gate signal connection terminal logic circuit 335 into which the delay signal dly is input is set to have a function of inverting and inputting the delay signal dly while the output terminal that outputs the set gen signal has a function of inverting the logical product of the comparison signal cmo and the inverted delay signal dly and outputting the set gen signal that is the comparison signal cmo and delay signal dly are input into the pmos gate signal connection terminal logic circuit 335 the pmos gate signal connection terminal logic circuit 335 sets the set gen signal at an l level only when the comparison signal cmo is at an h level and the delay signal dly is at an l level sets the set gen signal at an h level at all other times and inputs the set gen signal into the gate terminal of the pm 11 in the same way the second rise detector circuit 322 too going through the same operation as in the case of the first rise detector circuit 321 but with the resdrn signal as an input inputs the reset gen signal into the gate terminal of the pm 21 fig1 shows an operation time chart of the rise detector circuit shown in fig1 as shown in fig1 on the setdrn signal or resdrn signal being switched from an h level to an l level at a time t 7 the comparison signal cmo is also switched from an h level to an l.