a selective semiconductor growth ssg process without producing surface topography or degrading device surface planarity this simple process ensures uniform and repeatable nmos and pmos gate patterning due to flat surface topography the n to p well placement and spacing is self aligned due to the use of a disposable ssg hard mask application_number US 81454791 A description the invention provides a single mask self aligned twin well formation process for advanced cmos and bicmos technologies the process is based on the use of a selectively grown semiconductor or metal hard mask the process flow for the preferred embodiment of the process flow is as follows 1 with reference to fig1 which illustrates a portion of the resulting structure formed from process steps of the invention fabricate a stack of oxide 2 polysilicon 4 oxide 6 over for instance a p epitaxial layer lying on a p highly doped p type substrate using thermal oxidation low pressure chemical vapor deposition lpcvd of polysilicon and lpcvd or plasma enhanced chemical vapor deposition pecvd of oxide note that the p epitaxial layer and the p substrate may be collectively called the substrate lower oxide layer 2 may be 100 to 1000 u00e5 e g 200 u00e5 polysilicon layer 4 which acts as a buffer layer may be 200 1000 u00e5 e g 500 u00e5 top oxide layer 6 is chosen to be 5000 15000 u00e5 e g 1 u03bcm 2 with reference to fig2 which illustrates a cross sectional drawing of the resulting structure from the following processing steps use a well.