and a processor 11 are connected to the shared memory 21 fig5 is a block diagram showing a configuration of an embodiment in which the processor 1 and the processor 3 support virtual processors 15 and 16 and virtual processors 35 and 36 respectively the description will hereinbelow be given as to the operation when the processor 1 intends to communicate with the processor 3 through the i o ports 4 and 5 in the shared memory device 2 first the description will be given to the operation of setting the processor connection information to the registers 110 and 120 in the shared memory 2 on referring to the flow chart of fig6 immediately after the power supply is turned on in the shared memory device 2 the values of the processor numbers and the i o port numbers of the registers 110 and 120 prepared in the shared memory device 2 are not certain and the corresponding tags are reset in the initial program load ipl just after turning the power supply on the os which operates the processor 1 issues an instruction for storing the processor connection information the processor number 34 1 34 the tag is available and the i o port number 34 4 34 to the register 110 in the shared memory device 2 through the interface 7 and the i o port 4 step 601 in the shared memory device 2 it is confirmed that the processor number 34 1 34 is not set to any of the registers 110 and 120 step 602 then the specified processor connection information.