Manufacturing process used to create integrated circuits
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as microprocessors, microcontrollers, and memories (such as RAM and flash memory). It is a multiple-step photolithographic and physico-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs", with the central part being the "clean room". In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average. Production in advanced fabrication facilities is completely automated, with automated material handling systems taking care of the transport of wafers from machine to machine.
A wafer often has several integrated circuits which are called dies as they are pieces diced from a single wafer. Individual dies are separated from a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging.
Within fabrication plants, the wafers are transported inside special sealed plastic boxes called FOUPs. FOUPs in many fabs contain an internal nitrogen atmosphere which helps prevent copper from oxidizing on the wafers. Copper is used in modern semiconductors for wiring. The insides of the processing equipment and FOUPs is kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment and helps improve yield which is the amount of working devices on a wafer. This mini environment is within an EFEM (equipment front end module) which allows a machine to receive FOUPs, and introduces wafers from the FOUPs into the machine. Additionally many machines also handle wafers in clean nitrogen or vacuum environments to reduce contamination and improve process control. Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which are constantly purged with nitrogen. There can also be an air curtain or a mesh between the FOUP and the EFEM which helps reduce the amount of humidity that enters the FOUP and improves yield. 
Companies that manufacture machines used in the industrial semiconductor fabrication process include ASML, Applied Materials, Tokyo Electron and Lam Research.
Feature size.
Feature size is determined by the width of the smallest lines that can be patterned in a semiconductor fabrication process, this measurement is known as the linewidth. Patterning often refers to photolithography which allows a device design or pattern to be defined on the device during fabrication. F2 is used as a measurement of area for different parts of a semiconductor device, based on the feature size of a semiconductor manufacturing process. Many semiconductor devices are designed in sections called cells, and each cell represents a small part of the device such as a memory cell to store data. Thus F2 is used to measure the area taken up by these cells or sections.
A specific semiconductor process has specific rules on the minimum size (width or CD/Critical Dimension) and spacing for features on each layer of the chip.
Normally a new semiconductor process has smaller minimum sizes and tighter spacing. In some cases, this allows a simple die shrink of a currently produced chip design to reduce costs, improve performance, and increase transistor density (number of transistors per unit area) without the expense of a new design.
Early semiconductor processes had arbitrary names for generations (viz., HMOS I/II/III/IV and CHMOS III/III-E/IV/V). Later each new generation process became known as a technology node or process node, designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994, and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per unit area).
Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009. Feature sizes can have no connection to the nanometers (nm) used in marketing.
For example, Intel's former 10 nm process actually has features (the tips of FinFET fins) with a width of 7 nm, so the Intel 10 nm process is similar in transistor density to TSMC's 7 nm process. As another example, GlobalFoundries' 12 and 14 nm processes have similar feature sizes.
History.
20th century.
In 1955, Carl Frosch and Lincoln Derick, working at Bell Telephone Laboratories, accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects. By 1957 Frosch and Derick, using masking and predeposition, were able to manufacture silicon dioxide transistors; the first planar field effect transistors, in which drain and source were adjacent at the same surface. At Bell Labs, the importance of their discoveries was immediately realized. Memos describing the results of their work circulated around Bell Labs before being formally published in 1957. At Shockley Semiconductor, Shockley had circulated the preprint of their article in December 1956 to all his senior staff, including Jean Hoerni, who would later invent the planar process in 1959 while at Fairchild Semiconductor.
In 1948, Bardeen patented an insulated-gate transistor (IGFET) with an inversion layer; Bardeen's concept forms the basis of MOSFET technology today. An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963. CMOS was commercialised by RCA in the late 1960s. RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20μm process before gradually scaling to a 10 μm process over the next several years. Many early semiconductor device manufacturers developed and built their own equipment such as ion implanters.
In 1963, Harold M. Manasevit was the first to document epitaxial growth of silicon on sapphire while working at the Autonetics division of North American Aviation (now Boeing). In 1964, he published his findings with colleague William Simpson in the "Journal of Applied Physics". In 1965, C.W. Mueller and P.H. Robinson fabricated a MOSFET (metal–oxide–semiconductor field-effect transistor) using the silicon-on-sapphire process at RCA Laboratories.
Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East. 
Wafer size has grown over time, from 25 mm (1 inch) in 1960, to 50 mm (2 inches) in 1969, 100 mm (4 inches) in 1976, 125 mm (5 inches) in 1981, 150 mm (6 inches) in 1983 and 200 mm in 1992.
In the era of 2-inch wafers, these were handled manually using tweezers and held manually for the time required for a given process. Tweezers were replaced by vacuum wands as they generate fewer particles which can contaminate the wafers. Wafer carriers or cassettes, which can hold several wafers at once, were developed to carry several wafers between process steps, but wafers had to be individually removed from the carrier, processed and returned to the carrier, so acid-resistant carriers were developed to eliminate this time consuming process, so the entire cassette with wafers was dipped into wet etching and wet cleaning tanks. When wafer sizes increased to 100 mm, the entire cassette would often not be dipped as uniformly, and the quality of the results across the wafer became hard to control. By the time 150 mm wafers arrived, the cassettes were not dipped and were only used as wafer carriers and holders to store wafers, and robotics became prevalent for handling wafers. With 200 mm wafers manual handling of wafer cassettes becomes risky as they are heavier.
In the 1970s, several companies migrated their semiconductor manufacturing technology from bipolar to MOSFET technology. Semiconductor manufacturing equipment has been considered costly since 1978.
In 1984, KLA developed the first automatic reticle and photomask inspection tool. In 1985, KLA developed an automatic inspection tool for silicon wafers, which replaced manual microscope inspection.
In 1985, SGS (now STmicroelectronics) invented BCD, also called BCDMOS, a semiconductor manufacturing process using bipolar, CMOS and DMOS devices. Applied Materials developed the first practical multi chamber, or cluster wafer processing tool, the Precision 5000.
Until the 1980s, physical vapor deposition was the primary technique used for depositing materials onto wafers, until the advent of chemical vapor deposition. Equipment with diffusion pumps was replaced with those using turbomolecular pumps as the latter do not use oil which often contaminated wafers during processing in vacuum.
200 mm diameter wafers were first used in 1990 and became the standard until the introduction of 300 mm diameter wafers in 2000. Bridge tools were used in the transition from 150 mm wafers to 200 mm wafers and in the transition from 200 mm to 300 mm wafers. The semiconductor industry has adopted larger wafers to cope with the increased demand for chips as larger wafers provide more surface area per wafer. Over time, the industry shifted to 300 mm wafers which brought along the adoption of FOUPs, but many products that are not advanced are still produced in 200 mm wafers such as analog ICs, RF chips, power ICs, BCDMOS and MEMS devices. 
Some processes such as cleaning, ion implantation, etching, annealing and oxidation started to adopt single wafer processing instead of batch wafer processing in order to improve the reproducibility of results. A similar trend existed in MEMS manufacturing. In 1998, Applied Materials introduced the Producer, a cluster tool that had chambers grouped in pairs for processing wafers, which shared common vacuum and supply lines but were otherwise isolated, which was revolutionary at the time as it offered higher productivity than other cluster tools without sacrificing quality, due to the isolated chamber design.
21st century.
The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second-largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC. They also have facilities spread in different countries. As the average utilization of semiconductor devices increased, durability became an issue and manufacturers started to design their devices to ensure they last for enough time, and this depends on the market the device is designed for. This especially became a problem at the 10 nm node.
Silicon on insulator (SOI) technology has been used in AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors made since 2001. During the transition from 200 mm to 300 mm wafers in 2001, many bridge tools were used which could process both 200 mm and 300 mm wafers. At the time, 18 companies could manufacture chips in the leading edge 130nm process.
In 2006, 450 mm wafers were expected to be adopted in 2012, and 675 mm wafers were expected to be used by 2021.
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm process was similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm). Intel has changed the name of its 10 nm process to position it as a 7 nm process. As transistors become smaller, new effects start to influence design decisions such as self-heating of the transistors, and other effects such as electromigration have become more evident since the 16nm node.
In 2011, Intel demonstrated Fin field-effect transistors (FinFETs), where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors at the 22nm node, because planar transistors which only have one surface acting as a channel, started to suffer from short channel effects. A startup called SuVolta created a technology called Deeply Depleted Channel (DDC) to compete with