To understand the technical aspects which survive (as @WanderingLogic said marketting aspect dominated quite quickly), of the RISC/CISC dichotomy you need to consider four points:
* it is not really a dichotomy but more a continuum
* history is important: RISC came as a reaction to tentative to close the so called semantic gap. Don't look at how simple arithmetic is done, that will give you about no information, look for instructions like polynomial evaluation or function entry with automatic display setting and register savings. Those are the complex instructions which are absent in RISC and present in CISC. They introduced complications in the processor and their function could often be implemented more rapidly with a sequence simpler instructions, especially when not needed in their full generality. RISC is somewhat the result of a quantitative approach(1) to ISA design, trying to make the cost of the inclusion of an instruction justified by its benefit and its frequency of execution.
* history is important: RISC became popular at a time when implementing a 32-bit RISC on a single chip was just possible while for implementing a 32-bit CISC you either had to use several chips or space saving techniques which had an impact on performance. 705
You can nearly define RISC as the answer to the question "how to get an high performance 32-bit CPU on that area?" When the space available on a chip increased, the RISC cpus became more CISCy.
Now, how to get an high performance 32-bit CPU on a small area?
* You can't rely on having cache on chip, so lot of registers to benefit from the locality of data access. Thus not an accumulator nor stack architecture. (Aspect carried over with the register windowing).
* Pipelining. That means overlappable instructions, thus again 2 or 3 operands or you'll have trouble to have independent instructions.
* Simplify decoding. Fixed width instruction. Thus wide enough to have 3 operands and as the cost of implementing 3 operands is mostly instruction width, you get that most RISC are 3 operands ISA.
Delayed jump is more or less the result of pipelining with decoding simplified to the extreme.
1) See <PERSON> and <PERSON>. 705