If I am correct about your query then there are some of the links which I mentioned below that may help you to understand the procedure. But to make better understanding approach should not be how it is working the approach should be how it could possibly work.
Lets check with the first approach.
If you read some open documents of MCH you will see the PCI works on separate clock and FSB works on separate clock. Think of all the components working in the system works on different clock rate, the word synchronized doesnt mean that "If I say yes, at the same time you also say Yes", indeed it means things happenning at the rising edge of the clock. Now all the components such as circuits deal with busses like PCI, circuits deal with interrupt system and control unit itself has different clocks. One approach is in order to intercommunicate between the components the approach should be based on the handshaking signals. 7
Lets suppose components X1 is the main component that deal with internal processing and component X2 is the component that deals with only ISA or I2C bus. Now data recieved by X2 should go to processing through X1, what handshaking signals required. The hypothetical approach is:-
1 X2 notification that he has the data to X1 2 X1 acknowledge and ask to share the data 3 X2 start sending the data by keeping another signal ON to tell the X1 that data is on the bus (Just like in RAM we have the concept of RAS and CAS signals) 4 Once the data is completed by X2 it sends complete signal 5. And X1 acknowledge
Second approach I read on the MP book for x86, based on my understanding.
There is separate clock generated circuit in the computer that sends the clock to the processor and to the system, This circuit is tunned by a variable for example 2Y is the clock frequency on which the computer processor work and processor and clock generator is designed in such a way that 2Y gives to the processor and processor is made aware that it receives the multiple of Y clock frequency like "2" in this case and the board designer (An important person) should know that Y is enough frequency for the operation of every component mentioned on the board, thats why when he send the board for selling in the Market he mentioned the list of specifications for the compatibility.
Third approach is my own idea where the system components have one controller and each controller has two clocks one that is running its part and the other for which it is communicating upstream with the single reference clock
Moreover if we study pentium structure there is one pin which is known as cache miss and also if you study X86 you will see one pin known as Data ready, such kind of implementation is done that if an environment comes where sync-synchronized (The idea of perfect matching) not be the option (Board designer person decision) then create the wait states until the data is reliably received.
Below are some links that might help you. Also search clock domain crossing protocols
https://en.wikipedia.org/wiki/Clock_synchronization http://paginas.fe.up.pt/~ee12248/Dissertation/wp-content/uploads/2015/03/PDI_ee12248.pdf 552