b'Resume and Cover Letter Tips @ MS of Electrical Engineering\n\n2013-2014 Academic Year\n\nResources from the Columbia Center for Career Education (CCE) You Should Review:\n\xe2\x80\xa2 Planning Guide for Resumes/CVs and Cover Letters\no For Resumes/CVs (pages 14-31)\no For Cover Letters (pages 40-45)\n\xe2\x80\xa2 Tip Sheets for Resumes and Cover Letters\no Resume Tip Sheet\no Cover Letter Tip Sheet\nEE Recommended Resume Format\n\xe2\x80\xa2 One (1) page document\n\xe2\x80\xa2 Page Size: 8.5\xe2\x80\x9d x 11\xe2\x80\x9d\n\xe2\x80\xa2 Sections: Each section clearly outlined\n\xe2\x80\xa2 Font Style: Times New Roman, Arial, Calibri, or Tahoma\n\xe2\x80\xa2 Font Size: Dependent on Style, but no less than size 10\n\xe2\x80\xa2 Margins: No less than 0.5\xe2\x80\x9d on each side\n\xe2\x80\xa2 Consistency: Use one Font throughout\n\xe2\x80\xa2 Microsoft Word Format\n\nResume Sections\n\xe2\x80\xa2 Header\no Name: Legal First Name followed by Legal Last Name\n\xef\x82\xa7 If using a Preferred Name, the recommended format is:\nPreferred Name (Legal First Name in Parentheses) Legal Last Name\no Address: Where to mail physical offer letter\no Phone Number in the US\no Email: If using a Preferred Name, change your email \xe2\x80\x98Display Name\xe2\x80\x99 to reflect this format. It\nis also suggested you use your Columbia email.\no Webpage (LinkedIn Profile or other professional site such as a blog)\n\xe2\x80\xa2 Education: School and Degrees- in order of attendance starting with the most recent\no No high school\no Clearly indicate name of undergraduate institution, the location, degree program and month\nand year of graduation (required)\no Include any additional graduate degrees in the same format as undergraduate institution\no Performance indicator (i.e. GPA, honors, awards)\no List titles of relevant courses (no course numbers) if applicable\no Briefly summarize projects or thesis, if applicable\n\xe2\x80\xa2 Professional, Research, Academic Experience- in order of experience starting with the most recent\no Name of organization\no Location of organization\no Title of position\no Duration of experience (month and year began and month and year completed)\no Description of experience\n\xef\x82\xa7 Use action verb to start all bullet points (examples of verbs)\n\xef\x82\xa7 Verb tense: Past experiences should begin with a word in the past tense and Current\nexperiences should begin with a word in in present or active voice.\n\xef\x82\xa7 Tailor the resume to the job or purpose\n\xef\x82\xa7 Quantify your skills and highlight accomplishments- For example, include cost\nsavings in dollars or number of people you managed\n\xef\x82\xa7 All bullet points should be in the third person (no I, Me, Us, We\xe2\x80\xa6)\n\xe2\x80\xa2 Skills and Certifications\no Skills: Language(s), Computer, Programing, Other (i.e. hardware)\no Certifications\n\xe2\x80\xa2 Interests and Activities\no Interests: Select interesting ones and try to be specific\n\n\x0cResume and Cover Letter Tips @ MS of Electrical Engineering\n\n2013-2014 Academic Year\n\no Activities: Describe transferable skills and leadership\nThe Cover Letter Defined:\nIt is a business letter that\xe2\x80\xa6\n\xe2\x80\xa2 Introduces you as an applicant and highlights your qualifications\n\xe2\x80\xa2 Markets your creativity, writing style, and personality\n\xe2\x80\xa2 Informs the employer that you understand the requirements of the job\n\xe2\x80\xa2 Demonstrates that you possess the skills necessary for the job\n\nEE Recommended Cover Letter Format\n\xe2\x80\xa2 One (1) page document\n\xe2\x80\xa2 Page Size: 8.5\xe2\x80\x9d x 11\xe2\x80\x9d\n\xe2\x80\xa2 Font Style: Times New Roman, Arial, Calibri, or Tahoma\n\xe2\x80\xa2 Length: 4 or 5 brief paragraphs\n\xe2\x80\xa2 Font Size: Dependent on Style, but no less than size 10 and no more than size 12\n\xe2\x80\xa2 Consistency: Use one Font throughout, no bold or italics\n\xe2\x80\xa2 Microsoft Word Format\nCover Letter Sections:\nHeader: Your Name, Address, phone number and email\nGreeting: \xe2\x80\x98To Human Resources and Hiring Manager:\xe2\x80\x99 or \xe2\x80\x98Dear Mr. Riley:\xe2\x80\x99\n\xe2\x80\xa2\n\nWhenever possible, write to a specific person\n\nParagraph 1- Introduction- What position you are applying for, how you heard about the position, why\nthis position is exciting to you and a statement about what you bring to the table \xe2\x80\x9cbased on my\ngraduate education and previous internship/full time experience I will add value to this role in X way."\nParagraph 2- Specific Example(s) drawing on competencies/responsibilities listed in the job description\nthat you can speak to. "In my current role/graduate program I manage/take classes (in) Z where I\nstrengthened my BLANK skills.\xe2\x80\x9d\n\xe2\x80\xa2\n\nNote: If you are a career changer, you should provide a statement about how your previous\ncareer led you to transition back to school and seek a job opportunity in a new field or industry.\n\nParagraph 3- Specific Example(s) drawing on competencies/responsibilities listed in the job description\nthat you can speak to "In my current/previous role I create(d) Z where I develop(ed) BLANK skills.\xe2\x80\x9d\nParagraph 4- If Necessary: Specific Example(s) drawing on competencies/responsibilities listed in the\njob description that you can speak to. "In my current/past role I manage(d) X, Y, Z where I have\napplied BLANK skills.\xe2\x80\x9d\n\xe2\x80\xa2\n\nNote: If you have limited work or internship experience, this paragraph is likely not necessary.\n\nPara 5(or 4) Summation- What experience you are bringing to the table, why you will succeed and why\nyou are enthusiastic about this potential opportunity.\nClosing: Sincerely, Kind Regards, Best, Respectfully followed by exact name on your resume\n\nand time(s) and method to best reach you.\n\n\x0cResume and Cover Letter Tips @ MS of Electrical Engineering\n\n2013-2014 Academic Year\n\nAlways avoid clich\xc3\xa9s ( \xe2\x80\x98 I am a hard worker \xe2\x80\x99) . Highlight your strengths, but always follow up statements ab\nout your competencies ( \xe2\x80\x98 I have advanced technical skills\xe2\x80\x99) with a specific example.\n\nQuestions to ask yourself\n1. Does this resume stand up to the brand I wish to convey to employers?\nYour resume is a marketing presentation of you. It is a document with a purpose and summarizes\nyour education, experience, and skills in short, concrete, result-oriented phrases that puts together\nthe right picture of you.\n2. Which three people can I show this to for a variety of responses and constructive criticism?\nYou need a resume that can appeal to different pairs of eyes and people are subjective so be sure\nto gather various opinions during your editing process.\n3. What should I put in the cover letter rather than in the resume?\nThe cover letter is an opportunity to introduce yourself in full sentences and should explain how\nyou learned about the position and why you are interested and qualified for the role in comparison\nto a resume which highlights the tasks and responsibilities of your work and educational experience\nin bullet points. Also note, there is a difference between a formal 3-4 paragraph cover letter and an\nemail introduction to the prospective employer. The email form should be a brief 1 paragraph note\nthat pulls from the first and last paragraph of your formal cover letter and should be edited and\nreviewed thoroughly for errors before hitting send!\n\nIngredients for a Knock-out Resume\n\xe2\x80\xa2\n\nKeep your resume to one page.\n\n\xe2\x80\xa2\n\nUse an attractive and professional layout.\n\n\xe2\x80\xa2\n\nCatch the reader\xe2\x80\x99s attention in 15 seconds.\n\n\xe2\x80\xa2\n\nStart each bullet point with an active verb\n\n\xe2\x80\xa2\n\nMake everything positive on your resume. Your resume should convey a sense of vitality and an\nimage of you progressing smoothly and confidently through your career rather than having bumps.\n\n\xe2\x80\xa2\n\nTailor your resume to a job description whenever possible. Identify the five main qualities in the\ndescription and make sure those five qualities or as many as you can describe that are clearly\ndemonstrated in your resume.\n\n\xe2\x80\xa2\n\nHighlight achievements, rather than listing everything you have done.\n\n\xe2\x80\xa2\n\nAvoid raising unanswered questions and don\xe2\x80\x99t leaving gaps in your resume. Whether you served in\nthe military or did some traveling while unemployed or took a sabbatical, include a brief description\nto set the tone of a continued career progression\n\n\xe2\x80\xa2\n\nProofread \xe2\x80\x93 not just spell/grammar check! Check for tenses! Make sure to set your computer\nlanguage to U.S. English.\n\n\xe2\x80\xa2\n\nDO NOT Include:\no Personal Information (too personal)\n\xef\x82\xa7 Age, gender, marital status, number of children\no Repetitious use of words \xe2\x80\x9cResponsible for\xe2\x80\xa6Duties include\xe2\x80\x9d\n\n\x0cResume and Cover Letter Tips @ MS of Electrical Engineering\no\no\no\no\n\nYour GPA, if less than 3.0\nLong narrations\nList of references or \xe2\x80\x9cReference Available Upon Request\xe2\x80\x9d\nJPEGS, TIFFs, Animation\n\n2013-2014 Academic Year\n\n\x0cFIRST LAST\n425 Riverside Ave # 9A Manhattan NY 10027\n\n123-456-7139\xc2\xb7ab1234@columbia.edu\n\nEDUCATION\nColumbia University, School of Engineering and Applied Science\n\nNew York, NY\n\nMS in Electrical Engineering, GPA 3.79/4\nExpected Dec 2012\nCourses: Digital VLSI Circuits, Analog Electronic Circuits, Communication Circuits, Analog System in VLSI, Millimeter Wave Circuits,\nAdvanced Analog Integrated Circuits, Advanced Digital Electronic Circuits.\n\nTongji University, School of Electronics and Information\n\nShanghai, China\n\nBS in Electrical Engineering, GPA 3.8/4\nJul 2011\nCourses: Computer Architecture, Analog Electronic Technique, Digital Electronic Technology, Principles of Microcomputers and Interface\nTechnology, Automatic Control Theory, Programmable devices, Embedded systems.\n\nWORK EXPERIENCE\n\nHardware Design Team, Qualcomm Reference Design\n\nShanghai, China\nJun 2012 \xe2\x80\x93 Aug 2012\n\xe2\x80\xa2\nUsed Agilent 8960 to test WCDMA performance of Mobile Phone, such as Spectrum Emission Mask, Frequency\nError, Occupied bandwidth\n\xe2\x80\xa2\nMeasured GSM index of Mobile Phone, like output power, Output RF Spectrum, Frequency Error, Receive Sensitivity\n\xe2\x80\xa2\nModified the schematic of RF part to improve cell phone\xe2\x80\x99s RF performance\nSummer Intern\n\nPROJECT EXPERIENCE\nColumbia University\n\nDesigned and Physical Implementation of an AM radio receiver\n\nNew York, NY\nJan 2012 \xe2\x80\x93 Apr 2012\n\xe2\x80\xa2\nDesigned a TRF (tuned radio frequency) receiver for the AM band. Verified the circuit by simulation using LTspice.\n\xe2\x80\xa2\nBreadboard designed to make sure the circuit works with practical components.\n\xe2\x80\xa2\nBuilt the design in permanent form, by soldering the components to a regular-pattern PCBs. Achieved the frequency\nranges from 520kHz to 1710 kHz with a 50mW audio power into a 8-Ohm loudspeaker\nDesigned a fully differential switched capacitor amplifier used for pipelined ADC\nNew York, NY\nClass: Communication Circuits\n\nClass: Advanced Analog Circuits\nJan 2012 \xe2\x80\x93 Apr 2012\n\xe2\x80\xa2\nMade a system-level design for 5MHz, 7-bit ADC. Chose a full-scale voltage 1.4V with power supply 1.8V. Chose the\nswitch-MOSFET sizes. Determined the OTA specifications using the ideal OTA model.\n\xe2\x80\xa2\nDesigned an OTA satisfies the requirements, choose the topology, size transistors.\n\xe2\x80\xa2\nPlug in the OTA in the fully differential switched capacitor sample-and-hold amplifier with MOSFET switches and\nrun through the clock phases. Made sure it got a settling error of less than 1/2Vlsb with full-scale input.\nDesigned a CMOS Operational Amplifier with the demand specifications\nNew York, NY\n\nOct 2011 \xe2\x80\x93 Dec 2011\n\xe2\x80\xa2\nCame up with a preliminary design, taking into account relevant specifications given, calculating transistors\xe2\x80\x99 sizes.\n\xe2\x80\xa2\nVerified with LTSpice. Tuned the circuits Simulated DC operating point, DC transfer curve and DC small-signal gain,\nCommon-mode small-signal gain at DC, AC analysis.\n\xe2\x80\xa2\nAchieved Low Frequent Gain of 88.31dB, CMRR of 95dB, Unity-gain Frequency of 70.91MHz and Power\nconsumption of 99uW.\nDesigned a 8_bit Micro Processor using IBM 90-nm technology\nNew York, NY\nClass: Analog Electronic Circuits\n\nClass: Digital VLSI Circuits\nOct 2011 \xe2\x80\x93 Dec 2011\n\xe2\x80\xa2\nCreated a proposal to determine the topology of the circuits.\n\xe2\x80\xa2\nConstructed schematics for each part of the circuits with Cadence, analyzed key parameters including the delay, the\nfrequency and the sizing with preliminary W and L values. Made simulation to tune a considerable sizing. Finished the\nlayout of each part of the processor.\n\xe2\x80\xa2\nImplemented the whole layout in Virtuoso with DRC, LVS clean.\n\nAWARDS\n\nNational Scholarship\nFirst-Level People\'s Scholarship, Tongji University\nExcellent Student Award, Tongji University\n\nSKILLS\n\n\xe2\x80\xa2 Verilog HDL, Matlab, C, tcl, Cadence Virtuoso, LTSpice\n\nSep 2009\nJun 2009\nOct 2009\n\n\x0cFIRST LAST\n123-456-7890\n\nab1234@columbia.edu\n\nCURRENT POSITION\nHardware Development Engineer at LSI\n\nSan Jose, CA\n\nEDUCATION\nColumbia University, Fu Foundation School of Engineering and Applied Science\n\nNew York, NY\n\nMS in Electrical Engineering\n\nFeb 2013\n\nCoursework: Digital VLSI Circuits, Advanced Logic Design, Computer Architecture, CAD of Digital Systems, Embedded\nSystems, Advanced Digital Electronics Circuits, Formal SW & HW Verification, Computer Hardware Design\nHarbin Institute of Technology, School of Electronics and Information Technology\n\nHarbin, China\n\nBS in Communication Engineering (Microwave Technology)\n\nJuly 2011\n\nWORK EXPERIENCE\nALTOBEAM\n\nBeijing, China\n\nASIC Design Engineer\n\nSummer 2012\n\n\xe2\x80\xa2\n\nParticipated in the Merlin project designing high-performance receiver for digital television.\n\n\xe2\x80\xa2\n\nDesigned RTL modules in Verilog HDL to develop algorithms in Matlab, and verified them by writing testbenches in Verilog\nand Matlab and did large numbers of tests randomly by script files wrote in Perl and Makefile.\n\n\xe2\x80\xa2\n\nSet up the FPGA test environment, including collecting all related design modules and check for syntax errors, PIN\nassignment, running the simulations and synthesis, and report the timing and LUT utilization results.\n\nPROJECT EXPERIENCE\nColumbia University\n\nNew York, NY\n\nDesign of a Low Power Digital Signal Processor\n\xe2\x80\xa2\n\nSpring 2012\n\nDesigned a 32-bit microprocessor for DFT, IDFT and convolution operations, applying several low-power technologies, such\nas clock gating and multiple supply voltages, to minimize its power. The designed processor is capable of dealing with\ndifferent data lengths (2n, n varies from 1 to 16), and has specially designed hardware part for SRAM address calculation.\n\n\xe2\x80\xa2\n\nImplemented the design in System Verilog and wrote testbenches to verify its performance.\n\nDesign of a Small CAD Tool for Logic Miniaturization\n\xe2\x80\xa2\n\nSpring 2012\n\nDesigned a CAD tool in C based on unate recursive paradigm for generation of prime implicants from the input set of covers\nand identification of the essential ones. Functions built in the tool include: Termination Rule Checking, Tautology Checking,\nConsensus Generation, Single-Cube Containment, and Split variable picking.\n\n\xe2\x80\xa2\n\nVerified the tool with designed input PLA files covering all different kinds of initial covers.\n\nDesign and Verification of CAM\n\nFall 2012\n\n\xe2\x80\xa2\n\nDesigned a 32-bit content accessible memory (CAM) in System Verilog, realized its reset, read, write and search function.\n\n\xe2\x80\xa2\n\nVerified the design with testbench wrote in System Verilog, including manual-set tests, random tests, code coverage and\nfunction coverage.\n\nRTL Design of a Hybrid Floating-Point Integer Adder\n\xe2\x80\xa2\n\nFall 2011\n\nDetailed design of a special adder with an integer and a floating number as operands, including its Pseudo code, Algorithmic\nState Machine (ASM), architecture and microarchitecture, state diagram and Finite State Machine (FSM).\n\n\xe2\x80\xa2\n\nImplemented the design in VHDL and write testbenches to verify its performances with Quartus tool.\n\nOptimization of the Longest Common Subsequence (LCS) Microprocessor\n\nFall 2011\n\n\xe2\x80\xa2\n\nApplied a more efficient algorithm and rewrote the software part in C.\n\n\xe2\x80\xa2\n\nAdjusted the hardware configurations of the processor, such as core type, memory hierarchy, cache configuration and clock\nfrequency, to minimize the execution time within the cost and RAM size limitations.\n\nTECHINICAL SKILLS\n\xe2\x80\xa2\n\nApplications:\n\nOrigin, Excel, MS Word, PowerPoint, MS Visio, Endnote\n\n\xe2\x80\xa2\n\nResearch & Development:\n\nMatlab, Quartus, Cadence, Advanced Design System, CST Microwave Studio\xc2\xae\n\n\xe2\x80\xa2\n\nProgramming Languages:\n\nC, C++, Verilog HDL, System Verilog, VHDL, Perl, Tcl\n\n\x0cFirst Last\nab1234@columbia.edu \xc2\xb7 (+1) 123-456-7890\n122 West 126th Street, Apt.2E \xc2\xb7 New York, NY 10031\nEDUCATION\nExpected Dec.2012\nColumbia University, Fu Foundation School of Engineering and Applied Science\nM.S. in Electrical Engineering, Majoring in Analog IC Design\nRelevant Coursework:Advanced Analog Integrated Circuits, Analog Systems in VLSI, Electrical Power Networks\nBeijing JiaoTong University, School of Electrical Engineering\nSept.2007-Jun.2011\nB.S. in Electrical Engineering, Majoring in Power Systems and Power Electronics\nRelevant Coursework:Power Electronics, Power Electronics Device & Application, Photovoltaic Power Generation\nTechnology, Relay Protection of Power Systems\nOutstanding Graduates Award & Excellent Individual in Social Practice & Tri-A Student Scholarship\nEXPERIENCE\nElectrical Engineer at Urban Green Energy Inc., New York Headquarters\nMay.2012-Present\n\xe2\x80\xa2 Leading the Patent-Pending Project of Auto Relay Protection System for Wind Turbines from ideas to\nprofitable product, broadening the global market and reducing over $150 potential cost per unit\n\xe2\x80\xa2 Independently designed and developed a Solar Radiation Sensor for next generation 1st Step Weather Station,\ncreating an extra $15 profit for each device\n\xe2\x80\xa2 Effectively communicating with groups of people from over 15 different countries and regions\nGraduate Research Assistant at Columbia Laboratory for Unconventional Electronics\nSept.2011-May.2012\n-The EnHANTs (Energy Harvesting Active Networked Tags) Project\n\xe2\x80\xa2 Designed and simulated a Pulse-Width Modulation driver circuit to control LED lights for EnHANTs project\n\xe2\x80\xa2 Designed, improved and implemented an Energy Harvesting Module for EnHANTs project, cutting down\npower consumption by 15%, while increasing the accuracy of current measurement\n\xe2\x80\xa2 Won Best Student Demo Award at ACM Conference on Embedded Networked Sensor Systems(SenSys 2011)\nUndergraduate Research Assistant of Electric Power Engineering Laboratory at BJTU\nJuly.2010-Jan.2011\n-The Control and Protection Strategy of Micro-Grid with Charging Station involved\n\xe2\x80\xa2 Investigated and designed fundamental units and protection strategies of Micro-Grid\n\xe2\x80\xa2 Employed MATLAB and Simulink to build Micro-Grid model and verify protection strategies\nSELECTIVE PROJECTS\nApril.2009-April.2011\nProject Leader of Creative Experimental Project of National Undergraduate Students\n-Micro-Grid Power Quality Monitoring Network\n\xe2\x80\xa2 Designed, simulated and implemented a power quality data acquisition module, utilizing Proteus to simulate\nand Altium Designer to develop Printed circuit board\n\xe2\x80\xa2 Developed and implemented Modbus-TCP/IP Protocol and Ethernet Protocols to achieve full duplex data\ntransmission based on Microchip TCP/IP Stack\n\xe2\x80\xa2 Proficient in MPLAB IDE for micro-controller firmware development and lab equipments for debugging and\ntesting PCB\n\xe2\x80\xa2 Gained valuable experience in working cooperatively in a leadership role to accomplish goals\nMar.2012-May.2012\nAdvanced Analog Integrated Circuits Course Project\n-Design of a Fully Differential Switched Capacitor Amplifier for a 7-bit/5MHz Pipelined ADC\n\xe2\x80\xa2 Utilized Cadence to Design, simulate and test a two-stage fully differential telescopic Op-Amp in 0.18um\nCMOS technology\n\xe2\x80\xa2 Achieved desired functionality with a distinguished Figure of Merit by elaborate sizing and persevering effort\nDigital VLSI Circuits Course Project\nOct.2011-Dec.2011\n-Design of an 8-bit Microprocessor core in 90nm CMOS technology\n\xe2\x80\xa2 Utilized Cadence suits to design and simulate the schematics of each component within microprocessor core\n\xe2\x80\xa2 Accomplished layout of the completed microprocessor and obtained a DRC, LVS clean verification\n\xe2\x80\xa2 Achieved nearly 50% less area and power consumption because of ingenious design and sizing\nTECHNICAL SKILLS\nProficient in Cadence, ADS, SPICE Tools, MATLAB/Simulink, PCB Design/Layout, MPLAB, Microprocessor\nApplication Development, Modbus-TCP/IP Protocol Development\nACTIVITIES\nJun.2012-Aug.2012\nElectronics Tutor for selective high school students at BlueStamp Engineering\nMay.2008\nOrganizer of Soliciting Contributions Collecting over $2,300 for 2008.5.12 Sichuan Earthquake\n\n\x0cFirst Last\nab123@columbia.edu\n\n1962 1st Ave., APT 1K, New York, NY, 10029\n\n1-234-567-8901\n\nEDUCATION\nColumbia University, Fu Foundation School of Engineering and Applied Science\nMS in Electrical Engineering, GPA 3.5/4.0\nShanghai Jiao Tong University, School of Microelectronics\nBS in Electrical Engineering, GPA 3.5/4.0\n\nNew York, NY\nExpected December 2013\nShanghai, China\nJune 2012\n\nSELECTED COURSE DESIGNS\nColumbia University\n\nNew York, NY\n\nDesign: A Processor Employing Accelerator\n\xef\x82\x9f\nModified MIPS instruction set to enable accelerators for high performance calculation\n\xef\x82\x9f\nBuilt from Verilog RTL code to Place&Route, using 130nm technology\n\xef\x82\x9f\nWrote scripts to do simulation and timing & power analysis in Perl/bash\n\nFeb. 2013 - May. 2013\n\nDesigned a Hardware Firewall: \xe2\x80\x9cKillswitch\xe2\x80\x9d\n\xef\x82\x9f\nTargeted at filtering and capture of 10Gb/s Ethernet network\n\xef\x82\x9f\nBuilt Avalon ST interfaces of killswitch module for connection to Solarflare Board Service\n\xef\x82\x9f\nFiltering with CAM based structure to meet timing requirements\n\nFeb. 2013 - May. 2013\n\nDesigned a Network-On-Chip System\n\xef\x82\x9f\nBuilt a 4x4 mesh network in SystemVerilog\n\xef\x82\x9f\nAchieved Y-X dimension-ordered and credit based wormhole routing\n\xef\x82\x9f\nApplied golden brick to do random test to guarantee the correctness\n\xef\x82\x9f\nSynthesized with Design Compiler. Adjusted the design to meet the timing and area constraints.\n\nAug. 2012 - Dec. 2012\n\nShanghai Jiao Tong University\n\nShanghai, China\n\nProgrammed an Internet Information Server\nMar. 2011 - Jun. 2011\n\xef\x82\x9f\nCoded in C providing network function with TCP/IP socket, multithread using pthread and setup file configuration\n\xef\x82\x9f\nFunctions including several Linux commands (pwd, ls) via telnet provided to multiple client access.\n\xef\x82\x9f\nAvoided multithread data hazard using locks (mutex).\nDesigned a Pipeline Mips CPU\n\xef\x82\x9f\nImplemented optimizations including FORWARD to achieve better CPI\n\xef\x82\x9f\nCoded in Verilog, verified with several testbenches and synthesized in ISE\n\nMar. 2010 - Jun. 2010\n\nRESEARCH EXPERIENCE\nProject: Modeling and calibration of high speed, high resolution ADC\n\xef\x82\x9f\nEstablished the ideal model using Modelsim/Matlab , added harmonic distortion\n\xef\x82\x9f\nImplemented HDC algorithm and verified it.\n\nAug. 2010 \xe2\x80\x93 Nov.2011\n\nProject: Embedded System Design for the Portable Bio-Electrochemistry Sensor\n\xef\x82\x9f\nProgrammed the control software in C# for the device running on PC\n\xef\x82\x9f\nDesigned multi-channel mode with data verification\n\nApril. 2010-April.2011\n\nSKILLS\n\xef\x82\x9f\nProgramming Languages: asm, C, C++, C#,Verilog, SystemVerilog, VHDL, Java,Perl\n\xef\x82\x9f\nEngineering Tool: Modelsim, Xilinx ISE, Hspice, Multisim, Quartus, Matlab\n\xef\x82\x9f\nOperating Systems: Windows, Linux\n\xef\x82\x9f\nDocuments: Word, PowerPoint, Excel\n\xef\x82\x9f\nLanguages: Chinese(Native speaker), Japanese(N2)\nACTIVITIES\nAug. 2009 \xe2\x80\x93Jul. 2012\nForum Moderator, software board in online forum for SJTU\n\xef\x82\x9f\nHeld several themed parties offline\n\xef\x82\x9f\nDaily management\n\n\x0cFirst Last\n40 18st STR, Jackson Heights, Queens, NY, U.S\n\n\xe2\x80\xa2 ab123@columbia.edu \xe2\x80\xa2 123-456-7890\n\nEDUCATION\nColumbia University, New York, USA\nMS in Electrical Engineering, GPA 3.6/4.0\nBeijing University of Posts and Telecommunications (BUPT), Beijing, China\nBS in Telecommunication Engineering with Management, GPA 3.7/4.0\n\nDEC 2012\nJUL 2011\n\nPROFESSIONAL EXPERIENCE\nSoftware Developer, JPMorgan Chase & Co., New York, USA\nWINTER 2012 (till present)\n\xc2\xb7 Implemented the Proof Of Concept for website of Vedere to be like the business pattern of Vayable include the\nhtmls and database reconstructions.\n\xc2\xb7 Developed iOS mobile apps using Objective-C and Cocoa Touch SDK.\n\xc2\xb7 Developed Android mobile apps using JAVA and android SDK.\nSoftware Developer, HuaWei Technologies, Inc. Santa Clara, USA\nSUMMER 2012\n\xc2\xb7 Designed and implemented an online demonstration for the VXLAN project in Cloud Computing & Networks\ngroup, using JavaScript and Canvas in HTML5/CSS3\n\xc2\xb7 Designed an algorithm using HashTables to realize the connections between User Interface and actual virtual\nmachines with different combinations allowed.\n\xc2\xb7 Installed the virtual machine manager KVM and Openvswitch hypervisor under the Linux Ubuntu system to\nachieve the communications between the virtual machines by openvswitch.\n\xc2\xb7 Implemented the packet send and receive mechanisms under Layer 3 network of the VXLAN module using C++\n\xc2\xb7 Improved the performance of VLAN by using the featured updates from VXLAN\nInvestment Assistant, Shaanxi Hi-tech Industry Investment Ltd Co. Xi\xe2\x80\x99an, China\nSUMMER 2011\n\xc2\xb7 Accomplished the entire process of high risk investment of the Western Superconducting Technologies (WST)\n\xc2\xb7 Calculated the allowance of the depreciation, the capital and dividends of WST in financial year 2011.\n\xc2\xb7 Calculated the present value of the company by analyzing the investment value for future 3-5 years including\nprediction of gain and cash flow, evaluation of technology, management and intellectual property with the\ndiscount rate.\nPROJECT EXPERIENCE\nJava/PHP Developer, "Online Movie Rental DBMS" on Oracle 10g, Columbia University\nFALL 2012\n\xc2\xb7 Simulated the famous online movie rental website Netflix and designed our own Online Movie Rental Database\nManagement System Model by using E/R Diagrams and SQL Schema.\n\xc2\xb7 Implemented functions like Searching, Borrowing, Returning, Rating and Movies Management\n\xc2\xb7 Implemented web front-end application of the Library DBMS using Java, PHP, HTML and CSS\n\xc2\xb7 Won the best DBMS project in the class.\nJava (J2EE) Developer, \xe2\x80\x9cStocksBox\xe2\x80\x9d Web Application on AWS Cloud, Columbia University\nSPRING 2012\n\xc2\xb7 Designed a web application using Java, JSP, JavaScript and HTML/CSS to help clients\nsearch, store and display their selected stocks exchanges on our website from MySQL database\n\xc2\xb7 Utilized AWS EC2 with Linux, Apache/Tomcat, MySQL, PHP (LAMP) to support the web server\n\xc2\xb7 Designed elastic support with auto-scale processing units and storage when the number of clients\nor the amount of data exceeds their thresholds\nJava (J2EE) Developer, \xe2\x80\x9cTwitterBlog\xe2\x80\x9d Web Application on GoogleAppEngine, Columbia University\nSPRING 2012\n\xc2\xb7 Designed a blog website and deployed on Google App Engine\n\xc2\xb7 Designed a search engine using Get Search Service to create a request for Twitter API\n\xc2\xb7 Created a DataStore to store every Twitter request into an object instance for each given tweet Id\n\xc2\xb7 Fetched the 10 most popular tweets using Memcache service and used Java Mail Service to deliver them\nJava Developer, Vending Machine System, BUPT\nSPRING 2010\n\xc2\xb7 Designed vending machine model by using UML, which required conceptual diagrams, sequence diagrams\n\xc2\xb7 Implemented functions, including Transaction Management, Stock Management and Security Management\nTECHNICAL SKILLS\nProgramming:\nJAVA, JavaScript, PHP, JSP/Servlet, HTML5/CSS3, SQL, C++, Matlab and Assemly language Tools:\nEclipse, MySQL, Xcode,Oracle 10g Database, Tomcat, Matlab, OpenGl, Flash\nOperation System: Linux/Unix, Mac OS, Windows\nLanguage skills:\nChinese Mandarin\n\n\x0cFirst Last\nTEL : (123)-456-7890\nEmail: ab1234@columbia.edu\n\nEducation\nColumbia University, The Fu Foundation School of Engineering and Applied Science\n\nNew York, NY\n\nMS in Electrical Engineering, GPA 3.42/4.0\n\nExpected December 2013\n\nOhio University, Russ College of Engineering and Technology\n\nAthens, OH\n\nBS in Electrical Engineering, GPA 3.7/4.0\nJune 2012\nMinor in Math\nRelevant Coursework:\nAnalog System in VLSI, Advance Digital Circuits, Advance Analog Integrated Circuits, Digital VLSI Circuit, Electronic\nCircuits, Computer Architecture, Micro Device Fabrication, Energy Conversion Microcontroller, Electric Machine\n\nProject Experience\nColumbia University\n\nNew York, NY [January 2013-Current]\n\nFFT/FIR Accelerators design for General CPU\n\xef\x81\xac\n\xef\x81\xac\n\xef\x81\xac\n\xef\x81\xac\n\nDesigned algorithms for FFT/FIR accelerators in order to improve the speed of DSP.\nDesigned custom instructions, data paths and communication system between CPU and accelerators.\nWrote algorithms in Verilog HDL at RTL for accelerators.\nAnalyze static time for the design. Did Synthesis and convert verilog code to circuit net list using design compiler provide\nby Synopsys. Using Synopsys Primetime tool to produce timing and power information.\n\xef\x81\xac Wrote Verilog test bench and Perl scripts to automatically check functionality of the accelerators in Modelsim.\n\xef\x81\xac Designed Golden brick verification to compare results between Modelsim simulation and Matlab simulation.\n\xef\x81\xac Automatically produced layout of the whole design using Cadence Encounter and minimized the area. Hand adjusted the\nlayout to clean all DRC and LVS errors.\nColumbia University\nNew York, NY [September 2012-December 2012]\n\n8- Bit CPU Design\n\xef\x81\xac\n\nDesigned transistor level schematic circuit for an eight bit CPU in submicron (90nm) technology. The CPU contains\nmemory (SRAM), adder, shifter, flip-flop, tri-state bus controller, Mux and PLA in Cadence Virtuoso.\n\xef\x81\xac Designed Custom Layout for the eight bit CPU in order to use minimum area and fully understand design rules and layout\nissues.\n\xef\x81\xac Simulation in Cadence with layout parasitic extraction to fully prove the functionality and detect delay, power consumption\nof the CPU.\nColumbia University\nNew York, NY [September 2012-December 2012]\n\nTransimpedance Amplifier Design\n\xef\x81\xac\n\nDesigned a Transimpedance Amplifier used for the receiver in optic communication systems, which can convert current\nfrom a photodiode to large output voltage.\n\xef\x81\xac Analyzed and constructed the circuits in Pspice using CMOS technology. Technology tradeoffs between gain, bandwidth\nand power consumption to meet low power and large bandwidth requirements for the Amplifier.\n\xef\x81\xac Simulated the amplifier in different temperatures to prove the stability and wrote specification report.\nOhio University\nAthens, OH [September 2011- June 2012]\n\nSenior Design Project Wire Leach\n\xef\x81\xac Hardware design for the power harvest system for small UAV (Unmanned Aerial Vehicle).\n\xef\x81\xac Write codes using C++ in ROS allowed the UAV to detect a power line and land on the power line.\n\nTechnical Skills\nApplications: MATLAB, Cadence Virtuoso ,Modelsim, Pspice, Quartus, Modelsim, Cadabra,Synopsys design compiler\n& Primetime,Multisim, MS Excel, Word and Power point, ROS, BlueJ.\nProgramming Languages: C/C++, Java, VHDL/Verilog HDL, Perl, Python\nOperating System: Linux, Windows and Mac\n\n\x0cFirst Last\n250 W 106th St., Apt. 4J, New York, NY 10025 \xc2\xb7 1(234)567---8901 \xc2\xb7 ab123@columbia.edu\n\nEDUCATION\nColumbia University, The Fu Foundation School of Engineering and Applied Science\nMS in Electrical Engineering, GPA 3.8/4.0\n\nNew York, NY\nExpected December 2013\n\nRelevant Coursework: Analog Electronic Circuits, Digital VLSI Design, Computer Architecture, Advanced Logic Design, Advanced\nAnalog Integrated Circuits, Analog Systems in VLSI, Communication Circuits\nTsinghua University\n\nBeijing, China\n\nBS in Microelectronics, GPA 87/100\n\nJuly 2012\n\nRelevant Coursework: C++ Programming, JAVA Programming, Data Structure, Digital Logic Design, Principles of Microcomputer,\nDigital Integrated Circuit Analysis and Design, Analog Integrated Circuits Analysis and Design, Semiconductor Devices\n\nCURRICULUM PROJECTS\n\xe2\x80\x9cA Low---Power 2.8GHz 70dB\xce\xa9 TIA\xe2\x80\x9d\nFall 2012\n\xc2\xb7 Perfectly met all requirements in bandwidth, gain, and group delay with only 800uW power consumption (required less than\n30mW) due to the optimized design of structure and progressively optimizing transistor parameters under 130nm technology.\n\xc2\xb7 Used HSPICE to simulate and MATLAB to analyze the simulation result.\n\xe2\x80\x9cA 8---bit Microcontroller Core\xe2\x80\x9d\n\nFall 2012\n\n\xc2\xb7 Designed an 8-- bit core that can operate fundamental instructions, such as add/sub, shift, load, and store.\n\xc2\xb7\n\nDesigned all schematics on Cadence Composer. Carefully sizing of transistors and the insertion of buffer stages significantly\n\nimproved the circuit\xe2\x80\x99s speed, which is two times faster than the second of the class.\n\xc2\xb7 Completed manually layout on Cadence Virtuoso and passed DRC and LVS. High density and uniform height for the data path\nelements were achieved by using bit slice style while power and clock distribution were discreetly designed.\n\xe2\x80\x9cI2C (Inter---IC) Bus Protocol Implementation\xe2\x80\x9d\nFall 2012\n\xc2\xb7 Developed and simulated a Moore FSM controller specification for a slave device on the I2C bus protocol, where the slave can\nbe either a receiver or a transmitter. Described in VHDL.\n\xc2\xb7 Designed simple fault tolerance. Even parity code is used as the error detection.\n\xe2\x80\x9cA Custom Trigonometric FP Function Unit\xe2\x80\x9d\nFall 2012\n\xc2\xb7 Adopted RTL design flows and methodologies to implement a FP unit that operates on IEEE 754 SPFP numbers to compute both\nsine and cosine functions with user specified precision.\n\xc2\xb7 Derived a Moore controller ASM specification, on which a pipeline is designed to achieve high---speed.\n\xc2\xb7 Developed VHDL code and testbenches to verify the function.\n\xe2\x80\x9cFly Ball\xe2\x80\x9d\n\xc2\xb7 Implemented an Arkanoid game described in VHDL on FPGA, displayed on a monitor via the VGA interface.\n\xc2\xb7 Designed algorithms for logic module; developed VGA module that shows pictures loaded from ROM.\n\nFall 2009\n\nRESEARCH EXPERIENCE\n\xe2\x80\x9cRFID---2.4GHz OQPSK Digital Transmission and Reception System\xe2\x80\x9d\nSummer 2011\n\xc2\xb7 Implemented a communication protocol used on wireless sensor networks.\n\xc2\xb7 Developed and debugged the codes on IAR Embedded Workbench, and verified the protocol on TI CC2530 developing kits.\n\nTECHNICAL SKILLS\nAnalog Circuits Design: Cadence, HSPICE\n\nDigital Circuits Design: VHDL, Verilog, Perl\n\nProgramming: C++, Matlab, Java\n\nLayout: Cadence, Altium Designer, Ledit\n\n\x0cFIRST LAST\n329 Perry Avenue, Apt 3, Bronx, NY\n(347)-651-8235; Email: abc.123@gmail.com;\nEDUCATION:\n\nColumbia University- Fu Foundation School of Engineering and Applied Science, NY, USA\nMaster of Science in Electrical Engineering, Expected May 2013;\n\nGPA: 3.83/4.33\n\nRelevant Coursework: Advanced Logic Design, Computer Architecture, Parallel Computer Architecture, SoC Design,\nEmbedded System Design, VLSI design, Computer HW Design, Resilient HW System, Adv. Digital IC Design\nIslamic University of Technology, Dhaka, Bangladesh\nB.S. in Electrical Engineering, Class of 2010.\n\nGPA: 3.97/4.00\nSKILLS:\n\nPossess academic background in computer system design and microprocessor architecture, digital logic design, RTL design and\nvalidation, System on Chip design, ASIC, FPGA.\nProgramming and CAD tools: Cadence Spectre, Virtuoso, C-to-Silicon, VHDL, Verilog, SystemVerilog, SystemC, C, C++, Perl,\nMATLAB, RTL and waveform debugging tools.\nRELEVANT PROJECTS:\n\nColumbia University\nAsynchronous Design:\nSpring 2013\nEfficient Completion Detectors (CD) for m-of-n Return-to-Zero codes for asynchronous on-chip communication.\nASIC/Semi-custom Design:\nSpring 2013\nNoC: A 4x4 on-chip interconnection network.\nImplemented a 4x4 mesh network using completely synthesizable SystemVerilog HDL on Synopsys 90nm generic library.\nCrypto Core: A DPA tolerant AES Core for Cryptography application.\nImplementing a Differential Power Attack Tolerant AES (Advanced Encryption System) core in TSMS 130nm technology.\nECC: Fault Tolerant Channel Interface Unit for On-Chip Router Node using RTL design flow.\nDesigned an Error Correction and Detection unit to manage a single communication channel attached to a router node.\nCustom Design:\nFall 2012\nFull custom 8-bit microprocessor design.\nDesigned a full custom 8-bit microprocessor core in IBM 90nm technology.\nReconfigurable Computing- FPGA:\nFall 2012\nAn open source FIX (Financial Information Exchange) Engine on FPGA.\nExploring low-latency FPGA based solutions for high frequency trading platform.\nHardware Accelerator for High Frequency Trading Application on FPGA.\nDesigned 100Mbps UDP offload engine on Altera Cyclone II FPGA platform for low latency electronic stock trading.\nSystem level design & simulation:\nFall 2012\nSystemC TLM implementation of AMBA AXI4 protocol on a virtual Network on Chip simulator.\nImplemented network interfaces for an open source heterogeneous SoC simulator (developed by System Level Design\nGroup @CU) based on ARM AMBA AXI-4 protocol.\nDesigning a Microprocessor for Nucleotide Matching.\nImplemented a special purpose multicore processor to speed up the multithreaded Longest Common Subsequence (LCS)\nalgorithm for DNA sequence matching.\nCOAUTHORED RESEARCH PAPER:\n\n\xe2\x80\x9cPerformance Comparison between Round Robin and Proportional Fair Scheduling Methods for LTE,\xe2\x80\x9d Proc of 2010\nInternational Conference on Future Information Technology - IC FIT 2010, Changsha, China.\nLEADERSHIP & ACTIVITIES:\n\nTeam Leader of the high school Math Olympiad team. Won championship in the regional mathematical Olympiad.\nSchool representative on LIFE in 2020- LM Ericsson Ltd. Secured second position for presenting a business model based on\npervasive computing.'