Justia Patents Aravindan J. BUSI Inventions, Patents and Patent Applications
Patents by Inventor Aravindan J. BUSI
Aravindan J. BUSI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
Filed: November 6, 2019
Date of Patent: April 5, 2022
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
PROCESSING UNIT AND METHOD FOR COMPUTING A CONVOLUTION USING A HARDWARE-IMPLEMENTED SPIRAL ALGORITHM
Publication number: 20210192336
Abstract: Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.
Type: Application
Filed: December 23, 2019
Applicant: Marvell International Ltd.
Inventors: Deepak I. Hanagandi, Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi
Filed: August 22, 2019
MULTI-PORT MEMORY ARCHITECTURE FOR A SYSTOLIC ARRAY
Abstract: A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.
Filed: July 31, 2019
Inventors: Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi, Deepak I. Hanagandi, Igor Arsovski
Date of Patent: June 23, 2020
Arbitration for memory diagnostics
Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
Filed: September 28, 2018
Date of Patent: April 14, 2020
Inventors: Aravindan J. Busi, Kevin W. Gorman, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette
Publication date: March 5, 2020
Filed: October 31, 2017
Date of Patent: February 4, 2020
Publication date: December 12, 2019
Memory built-in self-test (MBIST) test time reduction
Abstract: Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.
Filed: February 9, 2016
Date of Patent: November 26, 2019
Assignee: GLOBALFOUNDRIES U.S. INC.
Inventors: Michael R. Ouellette, Deepak I. Hanagandi, Aravindan J. Busi, Kiran K. Narayan, Michael A. Ziegerhofer
Filed: March 26, 2015
Date of Patent: December 11, 2018
Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
Patent number: 9881694
Date of Patent: January 30, 2018
Built-in self-test (BIST) circuit and associated BIST method for embedded memories
Abstract: An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.
Date of Patent: September 12, 2017
Assignee: GLOBALFOUNDRIES INC.
Inventors: Aravindan J. Busi, Deepak I. Hanagandi, Krishnendu Mondal, Michael R. Ouellette
Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.
Filed: June 9, 2015
Date of Patent: July 25, 2017
Abstract: Disclosed is an integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.
Publication date: April 20, 2017
BUILT-IN SELF-TEST (BIST) ENGINE