 As with the Cray J90, each CPU contained a scalar data cache, in addition to the instruction buffering/caching which has always been in Cray architectures.Configurations were available with between four and 32 processors, and with either IEEE 754 or traditional Cray floating point arithmetic; the processors shared an SRAM main memory of up to eight gigabytes, with a bandwidth of three 64-bit words per cycle per CPU (giving a 32-CPU STREAM bandwidth of 360 gigabytes per second).The clock signal is distributed via a fiber-optic harness to the processors.