SmartSpice
SmartSpice is a commercial version of SPICE (Simulation Program with Integrated Circuit Emphasis) developed by Silvaco. SmartSpice is used to design complex analog circuits, analyze critical nets, characterize cell libraries, and verify analog mixed-signal designs. SmartSpice is compatible with popular analog design flows and foundry-supplied device models. It supports a reduced design space simulation environment. Among its usages in the electronics industry is Dynamic Timing Analysis.

Key features

 HSPICE-compatible netlists, models, analysis features, and results
 Can handle up to 400,000 active devices in 32-bit and 8 million active devices in 64-bit version
 Supports multiple threads for parallel operation
 Multiple solvers and stepping algorithms
 Collection of calibrated SPICE models for traditional technologies (bipolar, CMOS) and emerging technologies (e.g., TFT, SOI, HBT, FRAM) 
 Provides an open model development environment and analog behavioral capability with Verilog-A option
 Supports the Cadence analog flow through OASIS
 Offers a transient non-Monte Carlo method to simulate the transient noise in nonlinear dynamic circuits

Supported transistor models
BJT/HBT: 	Gummel-Poon, Quasi-RC, VBIC, MEXTRAM, MODELLA, HiCUM
MOSFET: 	LEVEL 1, LEVEL 2, LEVEL 3, BSIM1, BSIM3, BSIM4, BSIM5, MOS 11, PSP, MOS 20, EKV, HiSIM, HVMOS
TFT: 	Amorphous and Polysilicon TFT models: Berkeley, Leroux, RPI
SOI: 	Berkeley BSIM3SOI PD/DD/FD, UFS, LETISOI
MESFET: 	Statz, Curtice I & II, TriQuint
JFET: 	LEVEL 1, LEVEL 2
Diode: 	Berkeley, Fowler-Nordheim, Philips JUNCAP/Level 500
FRAM: 	Ramtron FCAP

Supported input formats
Berkeley SPICE netlist, HSPICE netlist, W-element RLGC matrix files, S-parameter model files, Verilog-A and AMS, C/C++

Supported output formats
Rawfiles, output listings, Analysis results, Measurement data, Waveforms (portable across unix/windows platforms)

References

External links
Silvaco
SmartSpice

Electronic design automation software
Electronic circuit simulators