gpt-2-medium/bitstreams/opt_kernel_xilinx_u280_full.info

==============================================================================
XRT Build Version: 2.14.384 (2022.2)
       Build Date: 2022-12-09 00:55:08
          Hash ID: 090bb050d570d2b668477c3bd0f979dc3a34b9db
==============================================================================
xclbin Information
------------------
   Generated by:           v++ (2021.2) on 2021-10-14-04:41:01
   Version:                2.14.384
   Kernels:                opt_kernel
   Signature:              
   Content:                Bitstream
   UUID (xclbin):          06dfa191-ba53-780e-16db-fd0655f01fc3
   Sections:               DEBUG_IP_LAYOUT, BITSTREAM, MEM_TOPOLOGY, IP_LAYOUT, 
                           CONNECTIVITY, CLOCK_FREQ_TOPOLOGY, BUILD_METADATA, 
                           EMBEDDED_METADATA, SYSTEM_METADATA, 
                           GROUP_CONNECTIVITY, GROUP_TOPOLOGY
==============================================================================
Hardware Platform (Shell) Information
-------------------------------------
   Vendor:                 xilinx
   Board:                  u280
   Name:                   xdma
   Version:                201920.3
   Generated Version:      Vivado 2019.2 (SW Build: 2742762)
   Created:
               Tue Jan 21 23:21:22 2020   FPGA Device:            xcu280
   Board Vendor:           xilinx.com
   Board Name:             xilinx.com:au280:1.0
   Board Part:             xilinx.com:au280:part0:1.0
   Platform VBNV:          xilinx_u280_xdma_201920_3
   Static UUID:            f2b82d53-372f-45a4-bbe9-3d1c980216da
   Feature ROM TimeStamp:  1579649056

Scalable Clocks
---------------
   Name:      clk_out1_pfm_top_clkwiz_hbm_aclk_0
   Index:     0
   Type:      SYSTEM
   Frequency: 450 MHz

   Name:      DATA_CLK
   Index:     1
   Type:      DATA
   Frequency: 257 MHz

   Name:      KERNEL_CLK
   Index:     2
   Type:      KERNEL
   Frequency: 500 MHz

System Clocks
------
   Name:           _bd_top_clkwiz_kernel2_clk_out1 
   Type:           SCALABLE 
   Default Freq:   500 MHz
   Requested Freq: 500 MHz
   Achieved Freq:  500 MHz

   Name:           _bd_top_clkwiz_kernel_clk_out1 
   Type:           SCALABLE 
   Default Freq:   300 MHz
   Requested Freq: 300 MHz
   Achieved Freq:  257.2 MHz

Memory Configuration
--------------------
   Name:         HBM[0]
   Index:        0
   Type:         MEM_DDR4
   Base Address: 0x0
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[1]
   Index:        1
   Type:         MEM_DDR4
   Base Address: 0x10000000
   Address Size: 0x10000000
   Bank Used:    Yes

   Name:         HBM[2]
   Index:        2
   Type:         MEM_DRAM
   Base Address: 0x20000000
   Address Size: 0x10000000
   Bank Used:    Yes

   Name:         HBM[3]
   Index:        3
   Type:         MEM_DRAM
   Base Address: 0x30000000
   Address Size: 0x10000000
   Bank Used:    Yes

   Name:         HBM[4]
   Index:        4
   Type:         MEM_DRAM
   Base Address: 0x40000000
   Address Size: 0x10000000
   Bank Used:    Yes

   Name:         HBM[5]
   Index:        5
   Type:         MEM_DRAM
   Base Address: 0x50000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[6]
   Index:        6
   Type:         MEM_DRAM
   Base Address: 0x60000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[7]
   Index:        7
   Type:         MEM_DRAM
   Base Address: 0x70000000
   Address Size: 0x10000000
   Bank Used:    Yes

   Name:         HBM[8]
   Index:        8
   Type:         MEM_DRAM
   Base Address: 0x80000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[9]
   Index:        9
   Type:         MEM_DRAM
   Base Address: 0x90000000
   Address Size: 0x10000000
   Bank Used:    Yes

   Name:         HBM[10]
   Index:        10
   Type:         MEM_DRAM
   Base Address: 0xa0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[11]
   Index:        11
   Type:         MEM_DRAM
   Base Address: 0xb0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[12]
   Index:        12
   Type:         MEM_DRAM
   Base Address: 0xc0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[13]
   Index:        13
   Type:         MEM_DRAM
   Base Address: 0xd0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[14]
   Index:        14
   Type:         MEM_DRAM
   Base Address: 0xe0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[15]
   Index:        15
   Type:         MEM_DRAM
   Base Address: 0xf0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[16]
   Index:        16
   Type:         MEM_DRAM
   Base Address: 0x100000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[17]
   Index:        17
   Type:         MEM_DRAM
   Base Address: 0x110000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[18]
   Index:        18
   Type:         MEM_DRAM
   Base Address: 0x120000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[19]
   Index:        19
   Type:         MEM_DRAM
   Base Address: 0x130000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[20]
   Index:        20
   Type:         MEM_DRAM
   Base Address: 0x140000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[21]
   Index:        21
   Type:         MEM_DRAM
   Base Address: 0x150000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[22]
   Index:        22
   Type:         MEM_DRAM
   Base Address: 0x160000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[23]
   Index:        23
   Type:         MEM_DRAM
   Base Address: 0x170000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[24]
   Index:        24
   Type:         MEM_DRAM
   Base Address: 0x180000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[25]
   Index:        25
   Type:         MEM_DRAM
   Base Address: 0x190000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[26]
   Index:        26
   Type:         MEM_DRAM
   Base Address: 0x1a0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[27]
   Index:        27
   Type:         MEM_DRAM
   Base Address: 0x1b0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[28]
   Index:        28
   Type:         MEM_DRAM
   Base Address: 0x1c0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[29]
   Index:        29
   Type:         MEM_DRAM
   Base Address: 0x1d0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[30]
   Index:        30
   Type:         MEM_DRAM
   Base Address: 0x1e0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         HBM[31]
   Index:        31
   Type:         MEM_DRAM
   Base Address: 0x1f0000000
   Address Size: 0x10000000
   Bank Used:    No

   Name:         DDR[0]
   Index:        32
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         DDR[1]
   Index:        33
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         PLRAM[0]
   Index:        34
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         PLRAM[1]
   Index:        35
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         PLRAM[2]
   Index:        36
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         PLRAM[3]
   Index:        37
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         PLRAM[4]
   Index:        38
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No

   Name:         PLRAM[5]
   Index:        39
   Type:         MEM_DRAM
   Base Address: 0x0
   Address Size: 0x0
   Bank Used:    No
==============================================================================
Kernel: opt_kernel

Definition
----------
   Signature: opt_kernel (const int L, const int L_out, const int seq_len, ap_uint<512>* X_acc0, ap_uint<512>* X_acc1, ap_uint<512>* W_acc0, ap_uint<512>* W_acc1, ap_uint<128>* acc0_out, int* cycle_count)

Ports
-----
   Port:          m_axi_X_acc0
   Mode:          master
   Range (bytes): 0xFFFFFFFFFFFFFFFF
   Data Width:    512 bits
   Port Type:     addressable

   Port:          m_axi_X_acc1
   Mode:          master
   Range (bytes): 0xFFFFFFFFFFFFFFFF
   Data Width:    512 bits
   Port Type:     addressable

   Port:          m_axi_W_acc0
   Mode:          master
   Range (bytes): 0xFFFFFFFFFFFFFFFF
   Data Width:    512 bits
   Port Type:     addressable

   Port:          m_axi_W_acc1
   Mode:          master
   Range (bytes): 0xFFFFFFFFFFFFFFFF
   Data Width:    512 bits
   Port Type:     addressable

   Port:          m_axi_acc0_out
   Mode:          master
   Range (bytes): 0xFFFFFFFFFFFFFFFF
   Data Width:    128 bits
   Port Type:     addressable

   Port:          m_axi_cycle_count
   Mode:          master
   Range (bytes): 0xFFFFFFFFFFFFFFFF
   Data Width:    32 bits
   Port Type:     addressable

   Port:          s_axi_control
   Mode:          slave
   Range (bytes): 0x1000
   Data Width:    32 bits
   Port Type:     addressable

--------------------------
Instance:        opt_kernel
   Base Address: 0x1800000

   Argument:          L
   Register Offset:   0x10
   Port:              s_axi_control
   Memory:            <not applicable>

   Argument:          L_out
   Register Offset:   0x18
   Port:              s_axi_control
   Memory:            <not applicable>

   Argument:          seq_len
   Register Offset:   0x20
   Port:              s_axi_control
   Memory:            <not applicable>

   Argument:          X_acc0
   Register Offset:   0x28
   Port:              m_axi_X_acc0
   Memory:            HBM[1] (MEM_DDR4)

   Argument:          X_acc1
   Register Offset:   0x34
   Port:              m_axi_X_acc1
   Memory:            HBM[2] (MEM_DRAM)

   Argument:          W_acc0
   Register Offset:   0x40
   Port:              m_axi_W_acc0
   Memory:            HBM[3] (MEM_DRAM)

   Argument:          W_acc1
   Register Offset:   0x4c
   Port:              m_axi_W_acc1
   Memory:            HBM[4] (MEM_DRAM)

   Argument:          acc0_out
   Register Offset:   0x58
   Port:              m_axi_acc0_out
   Memory:            HBM[7] (MEM_DRAM)

   Argument:          cycle_count
   Register Offset:   0x64
   Port:              m_axi_cycle_count
   Memory:            HBM[9] (MEM_DRAM)
==============================================================================
Generated By
------------
   Command:       v++
   Version:       2021.2 - 2021-10-14-04:41:01 (SW BUILD: 3363252)
   Command Line:  v++ --config /scratch/oswaldhe/hbm_config.ini --connectivity.nk opt_kernel:1:opt_kernel --connectivity.sp opt_kernel.X_acc0:HBM[1] --connectivity.sp opt_kernel.X_acc1:HBM[2] --connectivity.sp opt_kernel.W_acc0:HBM[3] --connectivity.sp opt_kernel.W_acc1:HBM[4] --connectivity.sp opt_kernel.acc0_out:HBM[7] --connectivity.sp opt_kernel.cycle_count:HBM[9] --input_files /scratch/oswaldhe/work.out/run-1/design-point.xo --kernel opt_kernel --link --optimize 3 --output /scratch/oswaldhe/vitis_run_hw/opt_kernel_xilinx_u280_xdma_201920_3.xclbin --platform xilinx_u280_xdma_201920_3 --report_level 2 --save-temps --target hw --temp_dir /scratch/oswaldhe/vitis_run_hw/opt_kernel_xilinx_u280_xdma_201920_3.temp --vivado.prop run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1 --vivado.prop run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-retarget -propconst -sweep -shift_register_opt} --vivado.prop run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=SSI_SpreadSLLs --vivado.prop run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Default --vivado.prop run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Default --vivado.prop run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=/scratch/oswaldhe/work.out/run-1/constraints.tcl --vivado.synth.jobs 8 
   Options:       --config /scratch/oswaldhe/hbm_config.ini
                  --connectivity.nk opt_kernel:1:opt_kernel
                  --connectivity.sp opt_kernel.X_acc0:HBM[1]
                  --connectivity.sp opt_kernel.X_acc1:HBM[2]
                  --connectivity.sp opt_kernel.W_acc0:HBM[3]
                  --connectivity.sp opt_kernel.W_acc1:HBM[4]
                  --connectivity.sp opt_kernel.acc0_out:HBM[7]
                  --connectivity.sp opt_kernel.cycle_count:HBM[9]
                  --input_files /scratch/oswaldhe/work.out/run-1/design-point.xo
                  --kernel opt_kernel
                  --link
                  --optimize 3
                  --output /scratch/oswaldhe/vitis_run_hw/opt_kernel_xilinx_u280_xdma_201920_3.xclbin
                  --platform xilinx_u280_xdma_201920_3
                  --report_level 2
                  --save-temps
                  --target hw
                  --temp_dir /scratch/oswaldhe/vitis_run_hw/opt_kernel_xilinx_u280_xdma_201920_3.temp
                  --vivado.prop run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1
                  --vivado.prop run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-retarget
                  -propconst
                  -sweep
                  -shift_register_opt}
                  --vivado.prop run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=SSI_SpreadSLLs
                  --vivado.prop run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Default
                  --vivado.prop run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Default
                  --vivado.prop run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=/scratch/oswaldhe/work.out/run-1/constraints.tcl
                  --vivado.synth.jobs 8 
==============================================================================
User Added Key Value Pairs
--------------------------
   <empty>
==============================================================================