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Nellyw888
/
VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
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1
Reinforcement Learning
Transformers
Safetensors
Nellyw888/RTL-Coder_7b_reasoning_tb_simple
Nellyw888/RTL-Coder_small
qwen2
text-generation
verilog
reasoning
rtl
text-generation-inference
arxiv:
2505.11849
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VeriReason-Qwen2.5-1.5b-RTLCoder-Verilog-GRPO-reasoning-tb
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initial commit
470fa90
verified
Nellyw888
commited on
May 15
Nellyw888
commited on
